Case 1:19-cv-01006-RGA Document 1 Filed 05/30/19 Page 1 of 106 PageID #: 1
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`IN THE UNITED STATES DISTRICT COURT
`FOR THE DISTRICT OF DELAWARE
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`PACT XPP SCHWEIZ AG
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`Plaintiff,
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`v.
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`INTEL CORPORATION
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`Defendant.
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`Case No. ______________
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`JURY TRIAL DEMANDED
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`Plaintiff PACT XPP Schweiz AG, for its Complaint against Intel Corporation (“Intel” or
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`COMPLAINT
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`“Defendant”), hereby alleges as follows:
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`PARTIES
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`1.
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`Plaintiff PACT XPP Schweiz AG is a Swiss corporation, with its principal place
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`of business in Switzerland. PACT XPP Schweiz AG is the assignee of all patents identified in
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`this Complaint including all rights to sue for past and future damages for infringement of said
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`patents.
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`2.
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`Upon information and belief, Intel is a Delaware corporation with its corporate
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`headquarters in Santa Clara, California and manufacturing facilities in Oregon, Arizona, New
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`Mexico, Massachusetts, and numerous other countries.
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`3.
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`Intel, founded in 1968, has over an 80% market share in computer processor
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`technology, and over $70 Billion in revenues producing $29.4 Billion of cash from operations
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`and returned nearly $16.3 Billion to shareholders in 2018 based on a gross profit margin of
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`61.7% of revenues. Intel’s two major operating segments are the PC Client Group, which
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`produced over $37 Billion in revenue for 2018 and focuses on the processors found in consumer-
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`grade netbooks and desktops, and the Data Center Group, which produced over $32 Billion in
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`revenue and focuses on processors found in enterprise-level servers.
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`NATURE OF THE ACTION
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`4.
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`This is a civil action for patent infringement of the following patents by
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`Defendant Intel: U.S. Patent Nos. 7,928,763 (“the ’763 Patent”), 8,301,872 (“the ’872 Patent”),
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`8,312,301 (“the ’301 Patent”), 8,471,593 (“the ’593 Patent”), 8,686,549 (“the ’549 Patent”),
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`8,819,505 (“the ’505 Patent”), 9,037,807 (“the ’807 Patent”), 9,075,605 (“the ’605 Patent”),
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`9,170,812 (“the ’812 Patent”), 9,250,908 (“the ’908 Patent”), 9,436,631 (“the ’631 Patent”), and
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`9,552,047 (“the ’047 Patent”) (collectively, the “Asserted Patents”). This action is based upon
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`the Patent Laws of the United States, 35 U.S.C. § 1 et seq.
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`JURISDICTION AND VENUE
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`5.
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`This Court has jurisdiction over the subject matter of this action pursuant to 28
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`U.S.C. §§ 1331 and 1338(a).
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`6.
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`This Court has personal jurisdiction over Intel because Intel is incorporated in
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`Delaware. Intel also manufactures products that are and have been used, offered for sale, sold,
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`and purchased in the District of Delaware.
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`7.
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`Under 28 U.S.C. §§ 1391(b)-(d) and 1400(b), venue is proper in this judicial
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`district because Intel is incorporated in this district, has committed acts of infringement within
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`this judicial district giving rise to this action, has previously filed suit in Delaware, and does
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`business in this district. Venue is also proper based on parties’ stipulation to refile the previously
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`dismissed Complaint originally filed in this District on February 7, 2019.
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`FACTUAL BACKGROUND
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`8.
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`PACT XPP Schweiz’s predecessor and assignor PACT XPP TECHNOLOGIES
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`AG (Lichtenstein) (hereinafter collectively referred to as “PACT”) was founded in 1996 in
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`Germany by Martin Vorbach. Mr. Vorbach (the lead inventor on all of PACT’s patents) has
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`been experimenting with parallel computing since the mid-1980s. Mr. Vorbach embarked on the
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`design of a completely different type of a multi-core computer architecture—that was the
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`forerunner of Intel’s multi-core processors. Mr. Vorbach focused his designs on multi-core
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`processing systems including how to handle more complex algorithms with large amounts of
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`data involving multiple processors on a single chip. Because of this, he encountered unique
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`challenges that the general CPU market would not face for years to come and was granted over
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`70 U.S. patents. On information and belief, Intel’s multi-core processors at issue were not
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`released until 2011, years after the priority dates of the Asserted Patents.
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`9.
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`For example, one challenge Mr. Vorbach had to solve was how to move and
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`access data in a multi-core system from one core to the next for large pipelined operations. This
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`led to his development of bus architectures for multicore processors with multiple paths,
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`including those using ring bus systems, for both configuring cores and accessing data in the cores
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`and in local memory including the patents identified herein.
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`10.
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`It was not until 2011 that Intel released its “Sandy Bridge” chip architecture
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`accused of infringement in this Complaint. Sandy Bridge included a ring-based interconnect for
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`communication between multiple processor cores, processor graphics and cache system. The
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`ring bus architecture takes up less space on the die while also scaling well for larger core
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`counts—in contrast to Intel’s earlier dual core designs. Intel coupled this with a last level cache
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`(LLC) that could be alternately shared among the cores. In 2017, Intel introduced a mesh bus
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`architecture, which is a modified version of the ring bus that also implements Mr. Vorbach’s
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`invention.
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`This architecture has been incorporated into most of Intel’s Core Series processor
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`11.
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`family—the i3, i5, i7, and i9 processors—found in computers and on information and belief
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`other processors manufactured and sold by Intel. Starting with the second generation (code-
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`named Sandy Bridge, released 2011), these processors have contained a variant of the above-
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`described ring bus (or equivalents) and LLC feature set including the Sandy Bridge, Ivy Bridge,
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`Haswell, Broadwell, Skylake, Kaby Lake, Coffee Lake architectures and, on information and
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`belief, other processors including ring bus architecture (or equivalents). According to Intel’s
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`most recent reported financial results for 2018,1 its revenue was over $32 Billion for its Data
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`Center Group and $37.0 Billion for its PC center group.
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`12.
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`Another contribution Mr. Vorbach made to the multi-core system is to change the
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`clock frequencies of part of the multi-core system in a particular way to take advantage of the
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`processing power of certain cores and in the meantime achieve power efficiency. This invention
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`was adopted by Intel in its Turbo Boost technology many years later. For example, Turbo Boost
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`2.0 was introduced in 2011 with the Sandy Bridge microarchitecture, and Turbo Boost Max 3.0
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`was introduced in 2016 with the Broadwell microarchitecture. On information and belief,
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`Turbo-Boost-enabled processors have been manufactured since 2008.
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`13.
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`Another contribution Mr. Vorbach made to the multi-core system is a stacking
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`technique, according to which the multi-core processors and the bus system are stacked on a
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`plurality of dies in an efficient way. Intel just adopted this stacking technique in recent
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`announcements.
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`14.
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`In December 2018, Intel hosted an Architecture Day conference in California for
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`analysts and media that allowed Intel’s top executives, architects and fellows to reveal their next-
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`generation technologies to a captive audience. During the conference, Intel announced that it
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`had created a new 3D packaging technology, called “Foveros.” Foveros is expected to extend
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`die stacking beyond passive interposers and stacked memory to high-performance logic, such as
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`CPU. In January 2019, during the CES conference, Intel made further announcement of a new
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`product, Lakefield, that implements the Foveros technology. The Foveros technology, however,
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`1 https://www.intc.com/investor-relations/investor-education-and-news/investor-news/press-
`release-details/2019/Intel-Reports-Fourth-Quarter-2018-Financial-Results/default.aspx
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`takes advantage of PACT’s invention disclosed in U.S. Patent No. 8,686,549, which, on
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`information and belief, Intel has been aware of since 2015.
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`15.
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`PACT does not make or sell products in the United States that implement the
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`asserted patents, and to PACT’s knowledge no PACT licensed products made or sold in the
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`United States implement the asserted patents.
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`INTEL HAS TOUTED THE BENEFITS OF THE INFRINGING TECHNOLOGY
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`16.
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`Intel itself has touted the improvements realized by the incorporation of the
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`accused technologies.
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`17.
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`In Intel’s technical materials, it marketed the ring bus and L3 cache architecture
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`by pointing to their specific advantages, such as robustness, scalability, and modularity:
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`18.
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`Regarding Turbo Boost, Intel states on its official website that “Intel® Turbo
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`Boost Technology 2.0 accelerates processor and graphics performance for peak loads,
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`automatically allowing processor cores to run faster than the rated operating frequency if they’re
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`operating below power, current, and temperature specification limits.” 2 “Turbo Boost Max
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`Technology 3.0 . . . enhances it with a massive frequency boost on your fastest cores for more
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`flexibility to get the best from your processor.”3 “As the name implies, processors with this
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`feature will enable extra performance when you need it most. . . . With this exciting new
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`technology, end users can game faster, be more productive, and do more, because it’s Intel.”4
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`19.
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`Intel also touted the Foveros technology on its official website: “Foveros paves
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`the way for devices and systems combining high-performance, high-density and low-power
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`silicon process technologies. Foveros is expected to extend die stacking beyond traditional
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`passive interposers and stacked memory to high-performance logic, such as CPU, graphics and
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`AI processors for the first time. The technology provides tremendous flexibility as designers
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`seek to ‘mix and match’ technology IP blocks with various memory and I/O elements in new
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`device form factors. It will allow products to be broken up into smaller ‘chiplets,’ where I/O,
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`SRAM and power delivery circuits can be fabricated in a base die and high-performance logic
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`chiplets are stacked on top. . . . Foveros is the next leap forward following Intel’s breakthrough
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`Embedded Multi-die Interconnect Bridge (EMIB) 2D packaging technology, introduced in
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`2018.”5
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`THE ASSERTED PATENTS
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`20.
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`On April 19, 2011, the U.S. Patent and Trademark Office duly and legally issued
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`the ’763 Patent, titled “Multi-Core Processing System.” The ’763 Patent names Martin Vorbach
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`2 https://www.intel.com/content/www/us/en/architecture-and-technology/turbo-boost/turbo-
`boost-technology.html
`3 https://www.intel.com/content/www/us/en/architecture-and-technology/turbo-boost/turbo-
`boost-max-technology.html
`4 https://www.intel.com/content/www/us/en/architecture-and-technology/turbo-boost/turbo-
`boost-max-technology.html
`5 https://newsroom.intel.com/articles/new-intel-architectures-technologies-target-expanded-
`market-opportunities/#gs.uIfUyfYJ
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`as the sole inventor. The ’763 Patent has been in full force and effect since its issuance. PACT
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`owns by assignment the entire right, title, and interest in and to the ’763 Patent, including the
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`right to seek damages for past, current, and future infringement thereof. PACT is the sole owner
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`of the ’763 Patent. A copy of the ’763 Patent is attached hereto as Exhibit A.
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`21.
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`On October 30, 2012, the U.S. Patent and Trademark Office duly and legally
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`issued the ’872 Patent, titled “Pipeline Configuration Protocol and Configuration Unit
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`Communication.” The ’872 Patent names Martin Vorbach, Volker Baumgarte, Gerd Ehlers,
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`Frank May, and Armin Nuckel as co-inventors. The ’872 Patent has been in full force and effect
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`since its issuance. PACT owns by assignment the entire right, title, and interest in and to
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`the ’872 Patent, including the right to seek damages for past, current, and future infringement
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`thereof. PACT is the sole owner of the ’872 Patent. A copy of the ’872 Patent is attached hereto
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`as Exhibit B.
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`22.
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`On November 13, 2012, the U.S. Patent and Trademark Office duly and legally
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`issued the ’301 Patent, titled “Methods and Devices for Treating and Processing Data.”
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`The ’301 Patent names Martin Vorbach and Volker Baumgarte as co-inventors. The ’301 Patent
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`has been in full force and effect since its issuance. PACT owns by assignment the entire right,
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`title, and interest in and to the ’301 Patent, including the right to seek damages for past, current,
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`and future infringement thereof. PACT is the sole owner of the ’301 Patent. A copy of the ’301
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`Patent is attached hereto as Exhibit C.
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`23.
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`On June 25, 2013, the U.S. Patent and Trademark Office duly and legally issued
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`the ’593 Patent, titled “Logic Cell Array and Bus System.” The ’593 Patent names Martin
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`Vorbach, Frank May, Dirk Reichardt, Frank Lier, Gerd Ehlers, Armin Nuckel, Volker
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`Baumgarte, Prashant Rao, and Jens Oertel as co-inventors. The ’593 Patent has been in full
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`force and effect since its issuance. PACT owns by assignment the entire right, title, and interest
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`in and to the ’593 Patent, including the right to seek damages for past, current, and future
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`infringement thereof. PACT is the sole owner of the ’593 Patent. A copy of the ’593 Patent is
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`attached hereto as Exhibit D.
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`24.
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`On April 1, 2014, the U.S. Patent and Trademark Office duly and legally issued
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`the ’549 Patent, titled “Reconfigurable Elements.” The ’549 Patent names Martin Vorbach as
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`the sole inventor. The ’549 Patent has been in full force and effect since its issuance. PACT
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`owns by assignment the entire right, title, and interest in and to the ’549 Patent, including the
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`right to seek damages for past, current, and future infringement thereof. PACT is the sole owner
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`of the ’549 Patent. A copy of the ’549 Patent is attached hereto as Exhibit E.
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`25.
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`On August 26, 2014, the U.S. Patent and Trademark Office duly and legally
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`issued the ’505 Patent, titled “Data Processor Having Disabled Cores.” The ’505 Patent names
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`Martin Vorbach and Robert Munch as co-inventors. The ’505 Patent has been in full force and
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`effect since its issuance. PACT owns by assignment the entire right, title, and interest in and to
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`the ’505 Patent, including the right to seek damages for past, current, and future infringement
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`thereof. PACT is the sole owner of the ’505 Patent. A copy of the ’505 Patent is attached hereto
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`as Exhibit F.
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`26.
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`On May 19, 2015, the U.S. Patent and Trademark Office duly and legally issued
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`the ’807 Patent, titled “Processor Arrangement on a Chip Including Data Processing, Memory,
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`and Interface Elements.” The ’807 Patent names Martin Vorbach as the sole inventor. The ’807
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`Patent has been in full force and effect since its issuance. PACT owns by assignment the entire
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`right, title, and interest in and to the ’807 Patent, including the right to seek damages for past,
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`current, and future infringement thereof. PACT is the sole owner of the ’807 Patent. A copy of
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`the ’807 Patent is attached hereto as Exhibit G.
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`27.
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`On July 7, 2015, the U.S. Patent and Trademark Office duly and legally issued
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`the ’605 Patent, titled “Methods and Devices for Treating and Processing Data.” The ’605
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`Patent names Martin Vorbach and Volker Baumgarte as co-inventors. The ’605 Patent has been
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`in full force and effect since its issuance. PACT owns by assignment the entire right, title, and
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`interest in and to the ’605 Patent, including the right to seek damages for past, current, and future
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`infringement thereof. PACT is the sole owner of the ’605 Patent. A copy of the ’605 Patent is
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`attached hereto as Exhibit H.
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`28.
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`On October 27, 2015, the U.S. Patent and Trademark Office duly and legally
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`issued the ’812 Patent, titled “Data Processing System Having Integrated Pipelined Array Data
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`Processor.” The ’812 Patent names Martin Vorbach, Jurgen Becker, Markus Weinhardt, Volker
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`Baumgarte, and Frank May as co-inventors. The ’812 Patent has been in full force and effect
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`since its issuance. PACT owns by assignment the entire right, title, and interest in and to
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`the ’812 Patent, including the right to seek damages for past, current, and future infringement
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`thereof. PACT is the sole owner of the ’812 Patent. A copy of the ’812 Patent is attached hereto
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`as Exhibit I.
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`29.
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`On February 2, 2016, the U.S. Patent and Trademark Office duly and legally
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`issued the ’908 Patent, titled “Multi-Processor Bus and Cache Interconnection System.”
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`The ’908 Patent names Martin Vorbach, Volker Baumgarte, Frank May, and Armin Nuckel as
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`co-inventors. The ’908 Patent has been in full force and effect since its issuance. PACT owns
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`by assignment the entire right, title, and interest in and to the ’908 Patent, including the right to
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`seek damages for past, current, and future infringement thereof. PACT is the sole owner of
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`the ’908 Patent. A copy of the ’908 Patent is attached hereto as Exhibit J.
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`30.
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`On September 6, 2016, the U.S. Patent and Trademark Office duly and legally
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`issued the ’631 Patent, titled “Chip Including Memory Element Storing Higher Level Memory
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`Data on a Page by Page Basis.” The ’631 Patent names Martin Vorbach as the sole inventor.
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`The ’631 Patent has been in full force and effect since its issuance. PACT owns by assignment
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`the entire right, title, and interest in and to the ’631 Patent, including the right to seek damages
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`for past, current, and future infringement thereof. PACT is the sole owner of the ’631 Patent. A
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`copy of the ’631 Patent is attached hereto as Exhibit K.
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`31.
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`On January 24, 2017, the U.S. Patent and Trademark Office duly and legally
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`issued the ’047 Patent, titled “Multiprocessor Having Runtime Adjustable Clock and Clock
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`Dependent Power Supply.” The ’047 Patent names Martin Vorbach and Volker Baumgarte as
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`co-inventors. The ’047 Patent has been in full force and effect since its issuance. PACT owns
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`by assignment the entire right, title, and interest in and to the ’047 Patent, including the right to
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`seek damages for past, current, and future infringement thereof. PACT is the sole owner of
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`the ’047 Patent. A copy of the ’047 Patent is attached hereto as Exhibit L.
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`THE ACCUSED INTEL INSTRUMENTALITIES
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`32.
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`Intel has infringed the Asserted Patents through the manufacture, use (including
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`testing), sale, offer for sale, advertisement, importation, shipment and distribution, service,
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`installation, and/or maintenance of Intel Core processors with Sandy Bridge and above
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`microarchitectures (the “Accused Core Instrumentalities”), Intel Xeon processors with Sandy
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`Bridge and above microarchitectures (the “Accused Xeon Instrumentalities”), and Intel Celeron
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`Processors with Sandy Bridge and above microarchitectures (the “Accused Celeron
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`Instrumentalities”) and on information and belief other processors incorporating ring bus
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`architecture or equivalents (such as mesh bus architcture).
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`33.
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`The Accused Core Instrumentalities are Intel Core processors with Sandy Bridge
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`and above microarchitectures, including, but not limited to, Core i3, Core i5, Core i7, Core i9,
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`and other core processors with the microarchitectures of Sandy Bridge, Ivy Bridge, Haswell,
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`Broadwell, Skylake, Kaby Lake, Coffee Lake, Cannon Lake, Ice Lake, and above.
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`34.
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`The Accused Xeon Instrumentalities are Intel Xeon processors with Sandy Bridge
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`and above microarchitectures, including, but not limited to, E3, E5, E7, and other Xeon
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`processors with the microarchitectures of Sandy Bridge, Ivy Bridge, Haswell, Broadwell,
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`Skylake, Kaby Lake, and above.
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`35.
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`Other
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`accused
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`instrumentalities
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`include
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`the Accused Turbo Boost
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`Instrumentalities,
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`the Accused Stacking
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`Instrumentalities, and
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`the Accused
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`’505
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`Instrumentalities as defined and discussed in corresponding sections below.
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`COUNT I – INFRINGEMENT OF U.S. PATENT NO. 7,928,763
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`36.
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`PACT incorporates each of the above paragraphs 1-35 as though fully set forth
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`herein.
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`37.
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`PACT is informed and believes, and thereon alleges, that Intel has infringed and
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`unless enjoined will continue to infringe one or more claims of the ’763 Patent, in violation of 35
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`U.S.C. § 271, by, among other things, making, using (including testing), offering to sell, and
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`selling within the United States, supplying or causing to be supplied in or from the United States,
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`and importing into the United States, without authority or license, Intel products with the
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`infringing features,
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`including
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`the Accused Core Instrumentalities,
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`the Accused Xeon
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`Instrumentalities, and the Accused Celeron Instrumentalities.
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`38.
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`For example,
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`the Accused Core
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`Instrumentalities,
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`the Accused Xeon
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`Instrumentalities, and the Accused Celeron Instrumentalities embody every limitation of at least
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`claim 1 of the ’763 Patent, literally or under the doctrine of equivalents, as set forth below. The
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`further descriptions below, which are based on publicly available information, are preliminary
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`examples and are non-limiting.
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`“A multi-processor chip, comprising”
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`39.
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`The Accused Core Instrumentalities, the Accused Xeon Instrumentalities, and the
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`Accused Celeron Instrumentalities are multi-core processors, and hence, a multi-processor chip.
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`“a plurality of data processing cells, each adapted for sequentially executing at least one of
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`algebraic and logic functions and having”
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`40.
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`The Accused Core Instrumentalities, the Accused Xeon Instrumentalities, and the
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`Accused Celeron Instrumentalities include a plurality of cores, each of which is adapted for
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`sequentially executing at least one of algebraic and logic functions as shown in the figure below:
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`“at least one arithmetic logic unit; at least one data register file; a program pointer; and at
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`least one instruction decoder”
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`41.
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`The Accused Core Instrumentalities, the Accused Xeon Instrumentalities, and the
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`Accused Celeron Instrumentalities include multi-core processors further including multiple
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`ALUs, general purpose registers, instruction pointer, and decoders, thus, including the recited
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`arithmetic logic unit, at least one data register file, a program pointer, and at least one instruction
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`decoder.
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`“a plurality of memory cells”
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`42.
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`The Accused Core Instrumentalities, the Accused Xeon Instrumentalities, and the
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`Accused Celeron Instrumentalities include Last Level Caches that constitute a plurality of
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`memory cells.
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`“at least one interface unit”
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`43.
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`The Accused Core Instrumentalities, the Accused Xeon Instrumentalities, and the
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`Accused Celeron Instrumentalities include a System Agent and/or components within or
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`connected or attached to the System Agent and/or the Last Level Caches (such as cache box) that
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`constitute at least one interface unit.
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`“at least one Memory Management Unit (MMU); and”
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`44.
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`The Accused Core Instrumentalities, the Accused Xeon Instrumentalities, and the
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`Accused Celeron Instrumentalities include memory management functionalities, and thus, at
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`least one Memory Management Unit (MMU).
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`“a bus system for interconnecting the plurality of data processing cells, the plurality of
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`memory cells, and the at least one interface unit, wherein the bus system is adapted for
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`programmably interconnecting at runtime at least one of data processing cells and memory
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`cells with at least one of memory cells and one or more of the at least one interface unit.”
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`45.
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`The Accused Core Instrumentalities, the Accused Xeon Instrumentalities, and the
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`Accused Celeron Instrumentalities include a ring bus system (or equivalents) programmably
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`interconnecting at runtime the cores, the LLCs and/or the interface unit identified above as
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`shown in the figure below:
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`46.
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`In violation of 35 U.S.C. § 271, Intel has infringed and is currently infringing,
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`directly and/or through intermediaries, the ’763 Patent by making, using, selling, offering for
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`sale, and/or importing into the United States, without authority, products that practice at least
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`claim 1 of the ’763 Patent. These products include the Accused Core Instrumentalities, the
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`Accused Xeon Instrumentalities, and the Accused Celeron Instrumentalities, and any other
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`products
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`that
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`incorporate
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`the Accused Core
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`Instrumentalities,
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`the Accused Xeon
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`Instrumentalities, and the Accused Celeron Instrumentalities. Intel has infringed and is currently
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`infringing literally and/or under the doctrine of equivalents.
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`47.
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`On information and belief, PACT asserts that Intel was aware of this patent before
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`this lawsuit was filed, and at least as of the service of the Complaint in PACT XPP Schweiz AG v.
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`Intel Corporation, 1-19-cv-00267 (DED), Intel had actual knowledge of its infringement of
`
`the ’763 Patent.
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`Case 1:19-cv-01006-RGA Document 1 Filed 05/30/19 Page 16 of 106 PageID #: 16
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`48.
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`PACT is informed and believes, and thereon alleges, that Intel, subsequent to the
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`time it first learned of the ’763 Patent and at least as of the time of service of the Complaint in
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`PACT XPP Schweiz AG v. Intel Corporation, 1-19-cv-00267 (DED), specifically intended to
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`induce patent infringement by third-party original equipment manufacturers (OEMs), customers,
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`and users of the Accused Core Instrumentalities, the Accused Xeon Instrumentalities, and the
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`Accused Celeron Instrumentalities and had knowledge that the inducing acts would cause
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`infringement or is willfully blind to the possibility that their inducing acts would cause
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`infringement. Intel has sold and continues to sell the Accused Core Instrumentalities, the
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`Accused Xeon Instrumentalities, and the Accused Celeron Instrumentalities to OEMs making
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`OEM products (e.g., computers, servers, laptops, tablets, etc.), knowing that the Accused Core
`
`Instrumentalities,
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`the Accused Xeon
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`Instrumentalities, and
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`the Accused Celeron
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`Instrumentalities will be included in the OEM products and sold to customers in the United
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`States in violation of U.S. patent law, and/or to original design manufacturers (ODMs), knowing
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`that the Accused Core Instrumentalities, the Accused Xeon Instrumentalities, and the Accused
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`Celeron Instrumentalities will ultimately be included in OEM products and sold to customers in
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`the United States.
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`49.
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`Indeed, Intel’s “Intel Inside” campaign has informed customers through
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`advertising and stickers on the OEM products themselves that the products contain the Accused
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`Core Instrumentalities, the Accused Xeon Instrumentalities, and the Accused Celeron
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`Instrumentalities. Intel also knows that many such OEM products that contain the Accused Core
`
`Instrumentalities,
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`the Accused Xeon
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`Instrumentalities, and
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`the Accused Celeron
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`Instrumentalities are made outside the United States and are imported into the United States in
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`violation of U.S. patent law. Intel also knows that U.S. customers of the OEMs use the OEM
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`Case 1:19-cv-01006-RGA Document 1 Filed 05/30/19 Page 17 of 106 PageID #: 17
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`
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`products containing the Accused Core Instrumentalities, the Accused Xeon Instrumentalities, and
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`the Accused Celeron Instrumentalities in the United States in violation of U.S. patent law.
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`50.
`
`Intel also publicly provides documentation, including datasheets available through
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`Intel’s publicly accessible ARK service and software developer’s manuals, instructing customers
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`on uses of Intel’s products that infringe the ’763 Patent. See, e.g., http://ark.intel.com. In
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`addition, Intel specifically advertises and promotes the infringing use of Intel’s products,
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`including the ring bus system and its equivalent. See, e.g., https://software.intel.com/en-
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`us/articles/how-memory-is-accessed.
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`51.
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`On information and belief, Intel’s customers directly infringe the ’763 Patent by,
`
`for example, making, using, offering to sell, and selling within the United States, and importing
`
`into the United States, without authority or license, products containing the Accused Core
`
`Instrumentalities,
`
`the Accused Xeon
`
`Instrumentalities, and
`
`the Accused Celeron
`
`Instrumentalities.
`
`52.
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`Intel contributes to the infringement of the ’763 Patent in violation of 35 U.S.C.
`
`§ 271(c). As stated above, on information and belief Intel was aware of the ’763 Patent before
`
`this lawsuit was filed but Intel was aware of the ’763 Patent at least as of the time of service of
`
`the Complaint in PACT XPP Schweiz AG v. Intel Corporation, 1-19-cv-00267 (DED). Intel thus
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`offers to sell and sells within the United States the Accused Core Instrumentalities, the Accused
`
`Xeon Instrumentalities, and the Accused Celeron Instrumentalities knowing that those products
`
`constitute a material part of the claimed invention because Intel incorporates the accused
`
`components (ring bus system, multi-cores, LLCs, etc.) into the Accused Core Instrumentalities,
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`the Accused Xeon Instrumentalities, and the Accused Celeron Instrumentalities.
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`Case 1:19-cv-01006-RGA Document 1 Filed 05/30/19 Page 18 of 106 PageID #: 18
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`53.
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`Intel knows that the Accused Core Instrumentalities, the Accused Xeon
`
`Instrumentalities, and the Accused Celeron Instrumentalities are especially made or especially
`
`adapted for use in infringing the ’763 Patent because the Accused Core Instrumentalities, the
`
`Accused Xeon Instrumentalities, and the Accused Celeron Instrumentalities all contain the
`
`infringing components (ring bus system, multi-cores, LLCs, etc.). Furthermore, because the
`
`Accused Core Instrumentalities, the Accused Xeon Instrumentalities, and the Accused Celeron
`
`Instrumentalities contain the infringing components (ring bus system, multi-cores, LLCs, etc.),
`
`they are not a staple article or commodity of commerce suitable for substantial non-infringing
`
`use.
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`54.
`
`In addition, Intel offers to sell and sells the Accused Core Instrumentalities, the
`
`Accused Xeon Instrumentalities, and the Accused Celeron Instrumentalities to Original
`
`Equipment Manufacturers (OEMs) and/or Original Design Manufacturers (ODMs) who then
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`incorporate the Accused Core Instrumentalities, the Accused Xeon Instrumentalities, and the
`
`Accused Celeron Instrumentalities into infringing products which are used, sold, offered for sale,
`
`and/or imported in the United States in an infringing manner. Accordingly, Intel is liable as a
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`contributory infringer.
`
`55.
`
`In the alternative, to the extent Intel does not meet all of the limitations of
`
`the ’763 Patent by making
`
`the Accused Core Instrumentalities,
`
`the Accused Xeon
`
`Instrumentalities, and the Accused Celeron Instrumentalities in the United States, Intel infringes
`
`under 35 U.S.C. § 271(f)(1) and (f)(2) by supplying from the United States a substantial portion
`
`of the components of the Accused Core Instrumentalities, the Accused Xeon Instrumentalities,
`
`and the Accused Celeron Instrumentalities (for example, structures or components contained in
`
`semiconductor wafers or dies or the like), and actively induces the combination of components
`
`
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`outside the United States in a manner t