Case 1:16-cv-00290-MN Document 103-4 Filed 10/17/18 Page 1 of 100 PageID #: 2552
`
`U.S. Patent
`
`Dec.20,2005
`
`Sheet 31 of 44
`
`US 6,977,684 Bl
`
`FIG. 34
`
`557
`r----------------------- --------------r---------- -----------------
`'
`
`,
`Q41
`Q42
`Q43
`q44 ~
`L _______________________ - - - - - - - - - - - - -~~ - - - - - - - - - - -----------•----~L..-
`
`' , - -
`
`' ' ' ' ' ' '
`
`S1
`
`S2
`
`A2
`
`HORIZONTAL SHIFT
`REGISTER
`
`559
`
`App. 0694
`
`

`

`Case 1:16-cv-00290-MN Document 103-4 Filed 10/17/18 Page 2 of 100 PageID #: 2553
`
`U.S. Patent
`
`Dec.20,2005
`
`Sheet 32 of 44
`
`US 6,977,684 Bl
`
`FIG. 35
`
`1 111 11111 1111 1111 I
`1111 111111 I 11 11111
`I 111 I 1111 I 111 1111 I
`
`I 1111 I 11111 I I
`I I I I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I 11 I 1111
`I 111 I 1111 I
`I
`I
`I
`I 111 I
`1111 I
`I
`I 11 I
`I
`I
`I
`I
`I
`I
`I
`I
`I 11111
`1111 I
`I
`I I t I
`I
`I
`111111
`
`''
`
`1111 I
`I
`I 111
`
`''
`
`cp HBLK
`¢L
`
`C/:>TXoo
`<PTXoe
`
`¢TN1
`
`¢TN2
`
`¢Ts1
`
`¢Ts2
`cp So
`¢Hn
`
`¢He
`
`'
`
`'
`
`11111
`I
`I
`I
`I
`I
`I 1111
`I 1111
`
`I
`I
`I
`I
`I 1111111 1111 I
`I 11 I.I
`I 1111111
`I
`I
`I
`I
`I
`111 I
`I 11 I
`11111 11111 t 11
`f 111
`
`I
`I
`
`I
`I
`
`App. 0695
`
`

`

`Case 1:16-cv-00290-MN Document 103-4 Filed 10/17/18 Page 3 of 100 PageID #: 2554
`
`U.S. Patent
`
`Dec.20,2005
`
`Sheet 33 of 44
`
`US 6,977,684 Bl
`
`FIG. 36
`
`<PHBL
`
`<PTXRo-1
`
`<PTXRo-2
`
`<PTXRo-3
`
`<PTXR0-4
`
`App. 0696
`
`

`

`Case 1:16-cv-00290-MN Document 103-4 Filed 10/17/18 Page 4 of 100 PageID #: 2555
`
`U.S. Patent
`
`Dec. 20, 2005
`
`Sheet 34 of 44
`
`US 6,977,684 Bl
`
`M
`
`■
`
`"
`C, -
`
`LL
`
`a:
`0
`I-
`<( a:
`<(
`a.
`~
`0
`0
`
`T
`
`v
`0
`r-....
`
`C')
`.....JQ
`<( ,-.....
`I- C: Zw
`w_
`a: LL
`w ::J
`LL a,_
`!:!::~
`0 <(
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`~
`I
`)
`>- C\J a:o
`Or--,..
`~
`w
`~
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`0
`,-.....
`
`a:
`w
`u:::
`::J a.
`
`~
`<(
`
`T
`
`T
`
`App. 0697
`
`

`

`Case 1:16-cv-00290-MN Document 103-4 Filed 10/17/18 Page 5 of 100 PageID #: 2556
`
`U.S. Patent
`
`Dec. 20, 2005
`
`Sheet 35 of 44
`
`US 6,977,684 Bl
`
`FIG. 38
`
`SIG
`
`Voo
`
`SELECT
`
`RESET
`
`PD
`
`AMP
`
`App. 0698
`
`

`

`Case 1:16-cv-00290-MN Document 103-4 Filed 10/17/18 Page 6 of 100 PageID #: 2557
`
`U.S. Patent
`
`Dec.20,2005
`
`Sheet 36 of 44
`
`US 6,977,684 Bl
`
`FIG. 39
`
`CsEL
`
`,.__ ______ ....__--++-----+-------.
`
`Mrx2
`
`MTX1
`PD1
`
`Mrx3
`
`PD3
`
`PD2
`
`PD4
`
`App. 0699
`
`

`

`Case 1:16-cv-00290-MN Document 103-4 Filed 10/17/18 Page 7 of 100 PageID #: 2558
`
`U.S. Patent
`
`Dec. 20, 2005
`
`Sheet 37 of 44
`
`US 6,977,684 Bl
`
`FIG. 40
`
`173 174
`
`~------. CM
`a
`
`- - - - - • - •
`CM
`
`a
`_.__ ___ - .
`CM
`
`•
`CM
`
`App. 0700
`
`

`

`Case 1:16-cv-00290-MN Document 103-4 Filed 10/17/18 Page 8 of 100 PageID #: 2559
`
`U.S. Patent
`
`Dec.20,2005
`
`Sheet 38 of 44
`
`US 6,977,684 Bl
`
`FIG. 41
`
`MsF
`
`MsEL
`
`Mrx2
`
`PD2
`
`App. 0701
`
`

`

`Case 1:16-cv-00290-MN Document 103-4 Filed 10/17/18 Page 9 of 100 PageID #: 2560
`
`U.S. Patent
`
`Dec.20,2005
`
`Sheet 39 of 44
`
`US 6,977,684 Bl
`
`FIG. 42
`
`JMrx1
`
`iPD1
`
`Mrx3
`
`PD3
`
`-
`
`-
`
`PD2
`
`Mrx4
`
`PD4
`
`-
`
`-
`
`MSEL
`
`I
`
`App. 0702
`
`

`

`Case 1:16-cv-00290-MN Document 103-4 Filed 10/17/18 Page 10 of 100 PageID #: 2561
`
`U.S. Patent
`
`Dec. 20, 2005
`
`Sheet 40 of 44
`
`US 6,977,684 Bl
`
`FIG. 43
`
`201 204
`
`203
`
`App. 0703
`
`

`

`Case 1:16-cv-00290-MN Document 103-4 Filed 10/17/18 Page 11 of 100 PageID #: 2562
`
`U.S. Patent
`
`Dec.20,2005
`
`Sheet 41 of 44
`
`US 6,977,684 Bl
`
`FIG. 44
`
`App. 0704
`
`

`

`Case 1:16-cv-00290-MN Document 103-4 Filed 10/17/18 Page 12 of 100 PageID #: 2563
`
`U.S. Patent
`
`Dec.20,2005
`
`Sheet 42 of 44
`
`US 6,977,684 Bl
`
`FIG. 45A
`
`FIG. 458
`
`R
`
`G
`
`R
`
`G
`
`8
`
`G
`
`R
`
`G
`
`R
`
`G
`
`B
`
`G
`
`Cy
`
`Ye
`
`Mg
`
`G
`
`Cy
`
`Ye
`
`G
`
`Mg
`
`App. 0705
`
`

`

`Case 1:16-cv-00290-MN Document 103-4 Filed 10/17/18 Page 13 of 100 PageID #: 2564
`
`U.S. Patent
`
`Dec.20,2005
`
`Sheet 43 of 44
`
`US 6,977,684 Bl
`
`FIG. 46
`
`172
`
`---------,_-----173
`174
`
`•
`
`171
`
`b21
`•
`
`•
`
`•
`
`b22
`• -----4----
`
`. ---------~
`
`•
`
`App. 0706
`
`

`

`Case 1:16-cv-00290-MN Document 103-4 Filed 10/17/18 Page 14 of 100 PageID #: 2565
`
`U.S. Patent
`
`Dec. 20, 2005
`
`Sheet 44 of 44
`
`US 6,977,684 Bl
`
`FIG. 47
`
`182c
`
`182d
`
`Voo
`
`App. 0707
`
`

`

`Case 1:16-cv-00290-MN Document 103-4 Filed 10/17/18 Page 15 of 100 PageID #: 2566
`
`US 6,977,684 Bl
`
`1
`ARRANGEMENT OF CIRCUITS IN PIXELS,
`EACH CIRCUIT SHARED BY A PLURALITY
`OF PIXELS, IN IMAGE SENSING
`APPARATUS
`
`BACKGROUND OF THE INVENTION
`
`The present invention relates to an image sensing appa(cid:173)
`ratus in which a plurality of pixels share a common circuit
`and an image sensing system using the apparatus.
`Conventionally, as an image sensing apparatus using a
`gain cell, or an active pixel sensor (APS), there are image
`sensing apparatuses utilizing MOS FET, JFET, bipolar tran(cid:173)
`sistor.
`These image sensing apparatuses amplify photo-charges
`generated by photodiodes, that are photoelectric conversion
`elements, by various methods, then output the amplified
`photo-charge signals as image information. Since an ampli(cid:173)
`fier for amplifying photo-charge exists in each pixel, the
`pixel is called a gain cell or an APS.
`An APS includes an amplifier and its controller in each
`pixel, therefore, the percentage of an area reserved for the
`photoelectric conversion element in a pixel ( area ratio) or
`area where light incidents in a pixel (aperture) tends to be
`small. This may cause deterioration of the dynamic range, 25
`sensitivity, and the SIN ratio of an image sensing apparatus.
`As described above, when an amplifier is provided in each
`pixel, as shown in FIG. 40, the aperture decreases. To
`prevent the decrease in the area or the aperture caused by the
`amplifier, methods of sharing an amplifier by a plurality of 30
`pixels, as disclosed in the Japanese Patent Application
`Laid-Open Nos. 63-100879 and 9-46596, have been pro(cid:173)
`posed.
`FIGS. 41 and 42 illustrate configurations shown in the
`above documents. Referring to FIGS. 41 and 42, reference 35
`PDl to PD4 denote photodiodes as photoelectric conversion
`elements; M=1 to Mrx4 are MOS transistors for transferring
`photo-charges generated by the photodiodes PDl to PD4;
`MREs is a MOS transistor for resetting the MOS transistors
`Mrx1 to M=4 ; and MsF and MsEL are MOS transistors 40
`configuring an amplifier (source follower). MsEL also func(cid:173)
`tions as a selection switch for selecting a pixel.
`However, in the Japanese Patent Application Laid-Open
`Nos. 63-100879 and 9-46596, no practical layout of the
`foregoing elements on a chip when a plurality of pixels share 45
`a single amplifier is discussed.
`Further, there is no description about a layout in a case
`where an amplifier, shared by a plurality of pixels, is
`replaced by another unit.
`
`SUMMARY OF THE INVENTION
`
`The present invention has been made in consideration of
`the above situation, and has as its first object to provide an
`image sensing apparatus, in which a common circuit, such as
`an amplifier, is shared by a plurality of pixels, achieving
`good performance without deterioration in resolution.
`Further, it is the second object of the present invention to
`provide an image sensing apparatus having a noise reduction
`system, preferably used in the image sensing apparatus, in
`which a common circuit is shared by a plurality of pixels.
`It is the third object of the present invention to provide an
`image sensing system using the foregoing image sensing
`apparatuses as a sensor unit.
`According to the present invention, the foregoing first 65
`object is attained by providing an image sensing apparatus
`having a plurality of unit cells, each including a plurality of
`
`2
`photoelectric conversion elements and a common circuit
`shared by the plurality of photoelectric conversion elements,
`arranged in either one or two dimensions, wherein the
`plurality of photoelectric conversion elements are arranged
`5 at a predetermined interval.
`The first object is also attained by providing an image
`sensing apparatus having a plurality of unit cells, each
`including a plurality of photoelectric conversion elements
`and a common circuit shared by the plurality of photoelec-
`10 tric conversion elements, arranged in two dimensions,
`wherein photoelectric conversion elements, out of the plu(cid:173)
`rality of photoelectric conversion elements, which are cov(cid:173)
`ered by a color filter that contributes mostly to forming a
`luminance signal are arranged in a same interval both in the
`15 horizontal and vertical directions by arranging adjoining
`rows or columns of photoelectric conversion elements
`shifted from each other.
`Further, the first object is also attained by providing an
`image sensing apparatus having a plurality of unit cells, each
`20 including a plurality of photoelectric conversion elements
`and a common circuit shared by the plurality of photoelec(cid:173)
`tric conversion elements, arranged in either one or two
`dimensions, characterized by comprising adjustment means
`for adjusting centers of mass of light-receiving areas of the
`plurality of photoelectric conversion elements provided in a
`central portion of the image sensing apparatus, so as to be
`apart at a same spatial interval.
`Furthermore, the first object is also attained by providing
`an image sensing apparatus having a plurality of unit cells,
`each including a plurality of photoelectric conversion ele(cid:173)
`ments and a common circuit shared by the plurality of
`photoelectric conversion elements, arranged in either one or
`two dimensions, characterized by comprising adjustment
`means for adjusting centers of mass of light-receiving areas
`of photoelectric conversion elements selected from the plu(cid:173)
`rality of photoelectric conversion elements, provided in a
`central portion of the image sensing apparatus, on the basis
`of a predetermined condition, so as to be apart at a same
`spatial interval.
`Further, to achieve the second object of the present
`invention, noise reading means for reading a noise of the
`common circuit; first signal reading means for reading a first
`signal through the common circuit; second signal reading
`means for reading a second signal through the common
`circuit; and noise reduction means for reducing the noise
`from the first and second signals are further provided.
`Alternatively, noise reading means for reading a noise of
`the common circuit; signal reading means for reading a
`plurality of signals through the common circuit; and noise
`50 reduction means for reducing the noise from the plurality of
`signals are further provided.
`Further, the third object of the present invention is
`achieved by providing an image sensing system having the
`image sensing apparatus as described above, a lens system
`55 for forming an image on the image sensing apparatus, and a
`signal processing circuit for processing an output signal
`from the image sensing apparatus.
`Other features and advantages of the present invention
`will be apparent from the following description taken in
`60 conjunction with the accompanying drawings, in which like
`reference characters designate the same or similar parts
`throughout the FIG. 5res thereof.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`The accompanying drawings, which are incorporated in
`and constitute a part of the specification, illustrate embodi-
`
`App. 0708
`
`

`

`Case 1:16-cv-00290-MN Document 103-4 Filed 10/17/18 Page 16 of 100 PageID #: 2567
`
`US 6,977,684 Bl
`
`3
`ments of the invention and, together with the description,
`serve to explain the principles of the invention.
`FIG. 1 is a block diagram illustrating a configuration of
`the image sensing system according to an embodiment of the
`present invention;
`FIG. 2A shows a layout of amplifiers in pixels according
`to a first embodiment of the present invention;
`FIG. 2B shows another layout of amplifiers in pixels
`according to the first embodiment of the present invention;
`FIG. 3 shows a practical pattern layout of two photo- 10
`diodes and an amplifier according to the first embodiment of
`the present invention;
`FIG. 4 is a brief view of FIG. 3 from which a part of lines
`are omitted;
`FIG. 5 shows another practical pattern layout of two 15
`photodiodes and an amplifier according to the first embodi(cid:173)
`ment of the present invention;
`FIG. 6 is a brief view of FIG. 5 from which a part of lines
`are omitted;
`FIG. 7 is an enlarged view showing vicinity of a floating
`diffusion portion according to the first embodiment of the
`present invention;
`FIG. 8 is an enlarged view showing vicinity of the floating
`diffusion portion according to the first embodiment of the
`present invention;
`FIG. 9 is a circuit diagram of a unit cell of a CMOS sensor
`in which two photodiodes share one amplifier according to
`the first embodiment of the present invention;
`FIG. 10 is a circuit diagram of the image sensing appa- 30
`ratus including a signal processing circuit according to the
`first embodiment of the present invention;
`FIG. 11 is a timing chart for operating an image sensing
`apparatus according to the first and second embodiments of
`the present invention;
`FIG. 12 is a timing chart for operating the apparatus
`according to the first and second embodiments of the present
`invention;
`FIG. 13 shows a layout of common circuits in pixels
`according to the second embodiment of the present inven(cid:173)
`tion;
`FIG. 14 shows another layout of common circuits in
`pixels according to the second embodiment of the present
`invention;
`FIG. 15 is a practical pattern layout of the common
`circuits each shared by two photodiodes according to the
`second embodiment of the present invention;
`FIG. 16 is a circuit diagram of the image sensing appa(cid:173)
`ratus including a signal processing circuit according to the
`second embodiment of the present invention;
`FIG. 17 is a circuit diagram of a unit cell configured with
`a common circuit and photodiodes according to the second
`embodiment of the present invention;
`FIG. 18 is an explanatory view for explaining a signal
`processing circuit;
`FIG. 19 is a layout of amplifiers in pixels according to a
`third embodiment of the present invention;
`FIG. 20 is another layout of amplifiers in pixels according
`to the third embodiment of the present invention;
`FIG. 21 is another layout of amplifiers in pixels according
`to the third embodiment of the present invention;
`FIG. 22 is another layout of amplifiers in pixels according
`to the third embodiment of the present invention;
`FIG. 23 is a practical pattern layout of four photodiodes 65
`and an amplifier according to the third embodiment of the
`present invention;
`
`25
`
`35
`
`40
`
`4
`FIG. 24 is another practical pattern layout of four photo(cid:173)
`diodes and an amplifier according to the third embodiment
`of the present invention;
`FIG. 25 is an explanatory view for explaining a variation
`5 of a layout;
`FIG. 26 shows a practical pattern layout according to the
`third embodiment of the present invention;
`FIG. 27 shows another layout of light-receiving areas
`according to the third embodiment of the present invention;
`FIG. 28 shows another practical pattern layout of four
`photodiodes and an amplifier according to the third embodi(cid:173)
`ment of the present invention;
`FIG. 29 is an example when on-chip lens according to the
`third embodiment of the present invention;
`FIG. 30 is a circuit diagram of a unit cell of a CMOS
`sensor having the aforesaid configurations according to the
`third embodiment of the present invention;
`FIG. 31 is a circuit diagram of the image sensing appa(cid:173)
`ratus including a signal processing unit according to the
`20 third embodiment of the present invention;
`FIG. 32 is a timing chart for operating an image sensing
`apparatus according to the third embodiment of the present
`invention;
`FIG. 33 is a circuit diagram of an image sensing apparatus
`including the signal processing unit according to a first
`modification of the third embodiment of the present inven(cid:173)
`tion;
`FIG. 34 is a circuit diagram of an image sensing apparatus
`including a signal processing unit according to a second
`modification of the third embodiment of the present inven(cid:173)
`tion;
`FIG. 35 is a timing chart for operating the image sensing
`apparatus shown in FIG. 34 according to the second modi(cid:173)
`fication of the third embodiment of the present invention;
`FIG. 36 is a timing chart during a vertical blanking period
`according to the second configuration of the third embodi(cid:173)
`ment of the present invention;
`FIG. 37 shows a configuration of a common circuit
`according to a fourth embodiment of the present invention;
`FIG. 38 is a circuit diagram of a unit cell of another image
`sensor to which the present invention is applied;
`FIG. 39 is a circuit diagram of a configuration of an
`amplifier shared by four photodiodes according to an
`45 embodiment of the present invention;
`FIG. 40 shows a conventional layout of amplifiers in
`pixels;
`FIG. 41 is a circuit diagram of a conventional configu(cid:173)
`ration;
`FIG. 42 is a circuit diagram of another conventional
`configuration;
`FIG. 43 shows a layout of common circuits in pixels when
`each common circuit is shared by two pixels;
`FIG. 44 shows a practical pattern layout of two photo(cid:173)
`diodes and an amplifier shown in FIG. 43;
`FIGS. 45A and 45B shows color filter arrangements;
`FIG. 46 is a layout of common circuits in pixels when
`each common circuit is shared by four pixels; and
`FIG. 47 shows a practical pattern layout of four photo-
`60 diodes and an amplifier.
`
`50
`
`55
`
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENTS
`
`Preferred embodiments of the present invention will be
`described in detail below in accordance with the accompa(cid:173)
`nying drawings.
`
`App. 0709
`
`

`

`Case 1:16-cv-00290-MN Document 103-4 Filed 10/17/18 Page 17 of 100 PageID #: 2568
`
`US 6,977,684 Bl
`
`5
`
`5
`<Possible Arrangements of Pixels and Common Circuit>
`First, possible arrangements of a plurality of pixels and a
`common circuit, shared by the pixels, based on the disclo(cid:173)
`sure of the Japanese Patent Application Laid-Open Nos.
`63-100879 and 9-46596, are described below. In the follow-
`ing explanation, an amplifier is used as an example of the
`common circuit in an image sensing apparatus.
`FIG. 43 shows an example of a layout of common circuits
`in pixels, when each common circuit is shared by two pixels.
`In FIG. 43, a case where each amplifier, as the common 10
`circuit, is shared by two pixels in two rows is shown, and,
`more specifically, each amplifier 204 is arranged between
`two photodiodes 203 above and below the row of the
`amplifiers 204 (such as, pairs of photodiodes a11 and a21 , a42
`and a22, a31 and a41 , a32 and a42, and so on). Note, a 15
`photodiode 203, which is a photoelectric conversion ele(cid:173)
`ment, and one half of the amplifier 204 configure a pixel.
`Reference numeral 201 indicates a unit cell repeated in the
`column direction, and reference numeral 202 indicates the
`unit cell repeated in the row direction.
`FIG. 44 shows a practical pattern layout of two photo(cid:173)
`diodes and an amplifier (a signal unit cell). The image
`sensing apparatus is a CMOS sensor, in this case.
`Referring to FIG. 44, reference numeral 221 denotes the
`unit cell (area surrounded by a dash line), which are referred 25
`to by reference numerals 201 and 202 in FIG. 43, having a
`size of two pixels, and repeatedly arranged in both the row
`and column directions. Light incidents on photodiodes 222a
`and 222b ( areas surrounded by bold lines, correspond to the
`photodiode pairs a11 and a21 , a12 and a22, a31 and a41 , a32 and 30
`a42, and so on, shown in FIG. 43) is converted into electrical
`charges (photo-charges), and accumulated within the pho(cid:173)
`todiodes 222a and 222b. The accumulated photo-charges are
`respectively transferred to a floating diffusion portion 225
`( also surrounded by a bold line) via a transfer gate 223 for 35
`an odd row and a transfer gate 224 for an even row, further
`transferred to the gate (floating gate) 226 of a MOS-type
`amplifier, which is the amplifier 204. Current flowing
`through the MOS-type amplifier is modulated, and the
`output current is taken out from the pixel array via a vertical 40
`signal line 227.
`X-Y addressing of the two dimensional pixel array, as
`shown in FIG. 43, in the image sensing apparatus is realized
`by the vertical signal line 227, an odd-row scanning line 228,
`an even-row scanning line 229, and a row selection line 230. 45
`In addition, a power line 231 for supplying electric power
`V DD and a reset line 232 for resetting the floating diffusion
`portion 225 and the gate 226 to a predetermined voltage are
`also arranged in the horizontal direction.
`The lines 228 to 232 are arranged above the wiring of the 50
`unit cells, and the lines are basically wide. The area under
`these five opaque lines 228 to 232 does not receive light,
`therefore, the amplifier 204 is arranged under the lines 228
`to 232. For the above reason, the two photodiodes sharing
`the amplifier are considered to be arranged on the upper and 55
`lower sides of the amplifier.
`With this layout, however, since the centers of mass (CM)
`of the photodiodes are not equal, as seen in FIG. 43, the
`following problems arise.
`First, if the pixel array outputs signals of a single color, 60
`since spatial frequency and resolution are different in one
`part from the other, the resolution deteriorates, and more(cid:173)
`over, moire appears.
`It is possible to cover the pixel array with a color filter
`whose color arrangement is as shown in FIG. 45A or 45B.
`In designing the color filter, colors may be arranged so that
`difference between intervals between pixels corresponding
`
`6
`to each color is minimized. In this case, however, the color
`arrangement is strictly limited.
`Further, if the Bayer filter as shown in FIG. 45A is used,
`intervals between pixels corresponding to green ( G) filter,
`which contributes most to luminance (Y) signals that the
`human eye is most sensitive to, are not equal. More spe-
`cifically, considering the positions of the photodiodes, e.g.,
`a12, a23, and a32 corresponding to the green filter, the
`distance between the photodiodes a12 and a23 in the column
`direction is different from the distance between the photo(cid:173)
`diodes a23 and a32 in the column direction. Thus, the filter
`arrangement causes different intervals between pixels cor(cid:173)
`responding to green filter, resulting in a moire problem;
`therefore, the quality of an obtained image is not good.
`Next, referring to FIG. 46, an example of a layout of
`common circuits in pixels when each common circuit is
`shared by four pixels, is explained.
`In this case, an amplifier, i.e., the common circuit, is
`shared by adjoining four pixels in two rows and two columns
`20 (2x2), and each amplifier 174 is surrounded by four photo(cid:173)
`diodes 173 (such as 2x2 photodiodes bw bw b21 , and b22,
`and b31 b32, b41 , and b42). In FIG. 46, reference numeral 171
`indicates a unit cell repeated in the column direction, and
`reference numeral 172 indicates the unit cell repeated in the
`row direction.
`FIG. 47 shows a practical pattern layout of four photo(cid:173)
`diodes and an amplifier. The image sensing apparatus is a
`CMOS sensor in this case, too.
`Referring to FIG. 47, reference numeral 181 denotes the
`unit cell (area surrounded by a dash line), which is referred
`to by reference numerals 171 and 172 in FIG. 46, having a
`size of four pixels, and repeatedly arranged in both the row
`and column directions. Light incidents on photodiodes 182a
`to 182d ( correspond to either one of groups of the photo-
`diodes, b11 , b12, b21 , and b22, and b31 , b32, b41 , and b42
`shown in FIG. 46) is converted into electrical charges
`(photo-charges), and accumulated within the photodiodes
`182a to 182d. The accumulated charges are respectively
`transferred to a floating diffusion portion 185 via transfer
`gates 183a to 183d, respectively, further transferred to the
`gate 186 of a MOS-type amplifier, which is the amplifier
`174. Current flowing through the MOS-type amplifier is
`modulated, and the output current is taken out from the pixel
`array via a vertical signal line 187.
`X-Y addressing of the two dimensional pixel array, as
`shown in FIG. 46, in the image sensing apparatus is realized
`by the vertical signal line 187, scanning lines 188a to 188d,
`and a row selection line 190. In addition, a power line 191
`for supplying electric power V DD is arranged in the column
`direction, and a reset line 192 for resetting the floating
`diffusion portion 185 and the gate 186 to a predetermined
`voltage are arranged in the horizontal direction.
`The lines 188 to 192 are arranged above the wiring of the
`unit cells, and the lines are basically wide. The area under
`these six opaque lines 188 to 192 does not receive light,
`therefore, the amplifier 174 is arranged under the lines 188
`to 182. For the above reason, the four photodiodes sharing
`the amplifier are considered to be arranged around the
`amplifier.
`With this layout, however, since the intervals between the
`centers of mass (CM) of photodiodes are not equal, as seen
`in FIG. 46, the following problem arises.
`If the pixel array outputs signals of a single color, since
`spatial frequency and resolution are different in one part
`65 from another, the resolution deteriorates, and moreover,
`moire appears. The moire is a serious problem, and an image
`sensing apparatus with a moire problem does not sell on the
`
`App. 0710
`
`

`

`Case 1:16-cv-00290-MN Document 103-4 Filed 10/17/18 Page 18 of 100 PageID #: 2569
`
`US 6,977,684 Bl
`
`8
`
`[Layout 1]
`FIG. 3 shows a practical pattern layout of two photo(cid:173)
`diodes and an amplifier in the CMOS sensor 22, and FIG. 4
`is a brief view of FIG. 3 from which a part of lines are
`5 omitted.
`The CMOS sensor, as shown in FIG. 3, is formed on a
`singlecrystalline silicon substrate based on a layout rule 0.4
`µm. Each pixel is a square, 8 µm each side, and a source
`follower amplifier, as the amplifier 12, is shared by two
`10 adjoining pixels arranged in the column direction. There(cid:173)
`fore, the size of a unit cell 31, shown by a dash line and is
`referred to by reference numerals 13 and 14 in FIG. 2A, is
`8 µmxl6 µm. A plurality of unit cells 31 are arranged in two
`dimensions.
`The photodiodes 32a and 32b, i.e., the photoelectric
`conversion elements, are formed on the right portion of
`respective pixels, and the shapes of the photodiodes 32a and
`32b are almost mirror images. Further, the photodiodes 32a
`and 32b are designed so that the center of masses (CM) of
`light-receiving areas of the photodiodes 32a and 32b are
`located at a substantially identical position of each pixel. In
`FIG. 3, the areas of the photodiodes 32a and 32b, and the
`area of a floating diffusion (FD) portion 35 are shown by
`bold lines. Further, in FIG. 3, reference numeral 38 denotes
`an odd-row scanning line for controlling each transfer gate
`33 in an odd-number row; 39, an even-row scanning line for
`controlling each transfer gate 34 in an even-number row; 40,
`a row selection line; and 42, a reset line for controlling the
`gate 43 of a MOS transistor. In FIG. 4, the lines 38 to 42 are
`not shown.
`Photo-charges accumulated in the photodiodes 32a and
`32b are transferred to the FD portion 35 via the transfer gate
`33 for the odd-number row and the transfer gate 34 for the
`even-number row. The size of the both transfer gates 33 and
`35 34 is L=0.4 µm, W=l.0 µm (Lis a channel length and Wis
`a channel width). The FD portion 35 is connected to the gate
`36 of a source follower via an aluminum (Al) wire having a
`width of 0.4 µm, and the photo-charge transferred to the FD
`portion 35 modulates the gate voltage of the gate 36. The
`40 size of the MOS transistor of the gate 36 is L=0.8 µm, W=l.0
`µm, and the total capacitance of the FD portion 35 and the
`gate 36 is about 5 fF. Since Q=CV; the gate voltage of the
`gate 36 changes by 3.2 volts in response to the transference
`of 105 electrons.
`Current flowing in from a V DD terminal 41 is modulated
`by the MOS transistor of the gate 36, and transferred to a
`vertical signal line 37. Current flowing through the vertical
`signal line 37 is processed by a signal processing circuit (not
`shown) and formed into image information.
`Thereafter, in order to set the potentials of the photodiodes
`32a and 32b, the FD portion 35, and the gate 36 to the
`predetermined potential V DD, the gate 43 of the MOS
`transistor connected to the reset line 42 is opened ( at this
`time, the transfer gate 33 for the add-number row and the
`55 transfer gate 34 for the even-number row are also opened),
`thereby the photodiodes 32a and 32b, the FD portion 35, and
`the gate 36 are electrically connected to the V DD terminal 41.
`Thereafter, the transfer gates 35 and 36 are closed, thereby
`the accumulation of photo-charges in the photodiodes 32a
`60 and 32b start again.
`The total number of the lines arranged in each unit cell in
`the horizontal direction is four, specifically, the odd-row
`scanning line 38, the even-row scanning line 39, the row
`selection line 40, and the reset line 42. The four lines are
`65 arranged in such a manner that two lines each are arranged
`on the upper and lower ends of each pixel, as shown in FIG.
`3.
`
`7
`market. This can be said for any image sensing apparatus
`having a configuration in which any number of pixels share
`a single common circuit.
`Accordingly, the inventors of the present application have
`developed image sensing apparatuses having improved
`arrangements of pixels and circuits shared by a plurality of
`pixels.
`The image sensing apparatuses will be described below in
`detail.
`<Basic Configuration of Image Sensing Apparatus>
`FIG. 1 is a block diagram illustrating a configuration of
`the image sensing apparatus according to an embodiment of
`the present invention.
`As shown in FIG. 1, light incoming through an optical
`system 21 forms an optical image on a CMOS sensor 22, and
`converted into electric charges by a pixel array arranged on
`the CMOS sensor. The photo-charges are further converted,
`processed and outputted by a signal processing circuit 23 in 20
`a predetermined method. The processed signals are recorded
`on an information storage medium or outputted by a record(cid:173)
`ing/transmission system 24. The recorded or transmitted
`information is retrieved by a retrieving system 27. The
`CMOS sensor 22 and the signal processing circuit 23 are 25
`controlled by a timing controller 25, and the optical system
`21, the timing controller 25, the recording/transmission
`system 24, and the retrieving system 27 are controlled by a
`system controller 26.
`Next, the CMOS sensor 22 according to the present 30
`invention will be described in detail.
`
`15
`
`First Embodiment
`
`FIG. 2A shows a layout of amplifiers 12 in pixels when
`each amplifier 12 is shared by two pixels adjoining in the
`column direction, and FIG. 2B shows a layout of amplifiers
`12 in pixels when each amplifier 12 is shared by two pixels
`adjoining in the row direction.
`In FIG. 2A, two photoelectric conversion elements 11
`(such as, pairs of the elements P 11, and P 21, P 31 and P 41, P 12
`and P 22, P 32 and P 42, and so on) sharing one amplifier 12 are
`arranged next to each other in the column direction, and the
`amplifier 12 is arranged along the adjoining pixels. In this 45
`manner, intervals between the centers of mass of the pho(cid:173)
`toelectric conversion elements 11 ( e.g., P 11, P 21, P 31, P 41,
`P 12, P 22, P 32, P 42) in both the row and column directions
`become equal. Reference numeral 13 indicates a unit cell
`repeated in the column direction, and reference numeral 14 50
`indicates the unit cell repeated in the row direction.
`Further, in FIG. 2B, two photoelectric conversion ele(cid:173)
`ments 11 (such as, pairs of the elements P 11 and P 12, P 13 and
`P14, P21 and P22, P23 and P24, P31 and P32, P33 and P34, and
`so on) sharing one amplifier 12 are arranged next to each
`other in the row direction, and the amplifier 12 is arranged
`along the adjoining pixels. In this manner, intervals between
`the centers of mass of the photoelectric conversion elements
`11 (P11, P12, P13, P14, P21, P22, P23, P24, P31, P32, P33, P34)
`in both the row and column directions also become equal.
`Reference numeral 15 indicates a unit cell repeated in the
`column direction, and reference numeral 16 indicates the
`unit cell repeated in the row direction.
`In the first embodiment, the number, N, of photoelectric
`conversion elements 11 sharing each amplifier 12 is two
`(N=2), however