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`Case 1:16-cv-00290-MN Document 1-9 Filed 04/22/16 Page 1 of 16 PageID #: 244
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`EXHIBIT |
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`Case 1:16-cv-00290-MN Document 1-9 Filed 04/22/16 Page 2 of 16 PageID #: 245
`
`US007709900B2
`
`(12) United States Patent
`Ikoma et al.
`
`(10) Patent N0.:
`(45) Date of Patent:
`
`US 7,709,900 B2
`*May 4, 2010
`
`(54) SEMICONDUCTOR DEVICE
`
`(75) Inventors: Daisaku Ikoma, Osaka (JP); Atsuhiro
`Kajiya, Hyogo (JP); Katsuhiro Ootani,
`Nara (JP); Kyoji Yamashita, Kyoto (JP)
`
`8/1995 EgaWa et a1.
`5,438,214 A
`3/1996 Komatsuzaki et a1.
`5,498,897 A
`5,847,421 A 12/1998 Yamaguchi
`
`(Continued)
`
`(73) Assignee: Panasonic Corporation, Osaka (JP)
`
`FOREIGN PATENT DOCUMENTS
`
`( * ) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 121 days.
`
`This patent is subject to a terminal dis-
`Claimer-
`
`(21) Appl. No.: 11/892,053
`
`(22) Flled:
`(65)
`
`Aug‘ 20’ 2007
`Prior Publication Data
`
`US 2008/0042214A1
`
`Feb. 21, 2008
`
`Related US. Application Data
`
`(62) Division of application No, 1 1/148,208, ?led on Jun, 9,
`2005, now Pat, No, 7,279,727
`
`(30)
`
`Foreign Application Priority Data
`_
`........................... .. 2004 213903
`
`(JP)
`
`Jul. 22, 2004
`(51) Int Cl
`(2006 01)
`HO'IL 3/62
`(52) us. Cl. .............. .. 257/369; 257/371; 257/E27.064
`58 F M f Cl _?
`_
`s
`h
`257/369
`(
`)
`1e
`0
`assl canon earc ""
`1 E27 064’
`S
`1,
`_
`?l f
`1
`h h, ’
`'
`ee app lcanon e or Comp ete Seam lstory'
`References Cited
`
`(56)
`
`U.S. PATENT DOCUMENTS
`
`JP
`
`64'50443
`
`2/1989
`
`(Continued)
`
`OTHER PUBLICATIONS
`Japanese Of?ce Action, With English translation, issued in Japanese
`Patent Application No. JP 2004-213903, mailed Apr. 1, 2008.
`
`(Continued)
`Primary ExamineriPhat X Cao
`Attorney, Agent, or FzrmiMcDermott W111 & Emery
`
`(57)
`
`ABSTRACT
`
`A semiconductor device includes a semiconductor substrate;
`a diffusion region Which is formed in the semiconductor
`substrate and serves as a region for the formation of a MIS
`transistor; an element isolation region surrounding the diffu
`sion region; at least one gate conductor ?lm Which is formed
`across the diffusion region and the element isola tion region’
`includes a gate electrode part located on the diffusion region
`and a gate interconnect part located on the element isolation
`feglon’ and has a Consent dmlenslon “1 the gate length mm‘
`t1on; and an mterlayer msulatmg ?lm covermg the gate elec
`trode. The semiconductor device further includes a gate con
`tact Which passes through the interlayer insulating ?lm, is
`connectedto the gate interconnect part, andhas the dimension
`in the gate length direction larger than the gate interconnect
`part.
`
`5,420,447 A
`
`5/ 1995 Waggoner
`
`10 Claims, 7 Drawing Sheets
`
`P-type
`Well Region
`‘
`11 (3 G1 0
`\
`\,
`<1
`G12a
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`Isolation
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`Well Region
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`Well Region
`
`P—type
`Well Region
`
`

`

`Case 1:16-cv-00290-MN Document 1-9 Filed 04/22/16 Page 3 of 16 PageID #: 246
`
`US 7,709,900 B2
`Page 2
`
`US. PATENT DOCUMENTS
`
`4/2001 Higashide
`6,222,758 B1
`6,376,351 B1* 4/2002 Tsai ......................... .. 438/592
`7,279,727 B2 * 10/2007 Ikoma et al.
`257/204
`7,405,450 B2 *
`7/2008 Lyu et a1. .................. .. 257/388
`2007/0063288 A1
`3/2007 Furuta et a1.
`
`FOREIGN PATENT DOCUMENTS
`
`JP
`JP
`JP
`
`64-89468
`05-006965
`08-272075
`
`4/1989
`1/1993
`10/1996
`
`JP
`JP
`JP
`JP
`JP
`JP
`
`9-246541
`10-032253
`11_297850
`2001427158
`2002_026125 A
`2003_218117
`
`9/1997
`2/1998
`10/1999
`5/2001
`1/2002
`7/2003
`
`OTHER PUBLICATIONS
`
`Chinese Of?ce Action, With English Translation, issued in Chinese
`Patent Application No. CN 2005100859849, issued on Apr. 14,
`2008.
`
`* cited by examiner
`
`

`

`Case 1:16-cv-00290-MN Document 1-9 Filed 04/22/16 Page 4 of 16 PageID #: 247
`
`US. Patent
`
`May 4, 2010
`
`Sheet 1 of7
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`US 7,709,900 B2
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`Case 1:16-cv-00290-MN Document 1-9 Filed 04/22/16 Page 5 of 16 PageID #: 248
`Case 1 16 cv 00290 MN Document 1 9 Flled 04/22/16 Page 5 of 16 PageID # 248
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`U.S. Patent
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`US 7,709,900 B2
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`Case 1:16-cv-00290-MN Document 1-9 Filed 04/22/16 Page 6 of 16 PageID #: 249
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`US. Patent
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`May 4, 2010
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`Sheet 3 of7
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`US 7,709,900 B2
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`Case 1:16-cv-00290-MN Document 1-9 Filed 04/22/16 Page 7 of 16 PageID #: 250
`Case 1:16-cv-00290-MN Document 1-9 Filed 04/22/16 Page 7 of 16 PageID #: 250
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`US. Patent
`
`May 4, 2010
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`Sheet 4 of7
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`US 7,709,900 B2
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`Case 1:16-cv-00290-MN Document 1-9 Filed 04/22/16 Page 8 of 16 PageID #: 251
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`US. Patent
`
`May 4, 2010
`
`Sheet 5 of7
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`US 7,709,900 B2
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`Case 1:16-cv-00290-MN Document 1-9 Filed 04/22/16 Page 10 of 16 PageID #: 253
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`US. Patent
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`May 4, 2010
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`Sheet 7 of7
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`US 7,709,900 B2
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`Case 1:16-cv-00290-MN Document 1-9 Filed 04/22/16 Page 11 of 16 PageID #: 254
`
`US 7,709,900 B2
`
`1
`SEMICONDUCTOR DEVICE
`
`This application is a Divisional of Us. application Ser. No.
`11/148,208, ?led Jun. 9, 2005, noW U.S. Pat. No. 7,279,727
`claiming priority of Japanese Application No. 2004-213903,
`?led Jul. 22, 2004, the entire contents of each of Which are
`hereby incorporated by reference.
`
`CROSS-REFERENCE TO RELATED
`APPLICATIONS
`
`The present application claims priority under 35 USC 1 19
`(a) to Japanese Patent Application No. 2004-213903 ?led on
`Jul. 22, 2004 the entire contents of Which are hereby incor
`porated by reference.
`
`BACKGROUND OF THE INVENTION
`
`(a) Field of the Invention
`The present invention relates to a semiconductor device
`having a miniaturized transistor, and particularly to a measure
`against an optical proximity effect.
`(b) Description of the Related Art
`Main factors causing variations in propagation delay time
`in a design of a semiconductor integrated circuit (LSI) include
`variations in operating poWer supply voltage, temperature,
`process, etc. The LSI should be designed so that its operation
`is ensured even When all the factors are Worst. Among deter
`minants of a transistor, the gate length is a particularly impor
`tant determinant Which de?nes the operation of the transistor.
`The variations in the gate length thus affect variations in
`process greatly. As the transistor is reduced in siZe, the gate
`length has been becoming much shorter and the variations in
`the gate length have been Widening. As a result, the variations
`in propagation delay time have also Widened and the design
`margin has increased, and thereby it has become di?icult to
`provide the LSI having high performance.
`In general, in a semiconductor fabricating process, a pho
`tolithographic step including resist application, light expo
`sure and development, an etching step for patterning the
`elements With a resist mask, and a resist removing step are
`repeated to form an integrated circuit on a semiconductor
`substrate. In forming a gate of the transistor, the photolitho
`graphic step, the etching step and the resist removing step are
`also performed. In the expo sure of the photolithographic step,
`if the pattern dimension is not more than the exposure Wave
`length, the optical proximity effect generated by the in?uence
`of diffracted light causes a large error betWeen the pattern
`dimension in the layout design and the actual pattern dimen
`sion on the semiconductor substrate.
`Techniques for solving the above problems include a super
`resolution technique using a phase shift mask and an OPC
`(Optical Proximity Correction) technique for correcting the
`in?uence of the optical proximity effect by modifying a cir
`cuit pattern draWn on the mask (see e. g., Japanese Unexam
`ined Patent Publication No. H08-272075). HoWever, the opti
`cal proximity effect inevitably occurs, and it is di?icult to
`prevent the optical proximity effect only by manufacturing
`and process techniques such as the super resolution technique
`and the OPC technique. Therefore, a structure of the semi
`conductor device Which can utiliZe to the optical proximity
`effect is desired at the design stage.
`As previously mentioned, as the transistor is reduced in
`siZe, the gate length becomes shorter and the optical proxim
`ity effect caused by diffracted light more affects the gate in
`exposing the gate to light. The optical proximity effect in the
`formation of the gate occurs depending on the layout pattern
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`2
`of the gate of the transistor, and causes not only variations in
`the gate length among the transistors but variations in the gate
`length along the gate Width direction. Particularly, assume
`that a continuous gate polysilicon ?lm includes a gate elec
`trode part Which is a transistor element existing on an active
`region; a gate interconnect part extending from the gate elec
`trode part onto an element isolation region; and a pad for
`forming a contact Which connects the gate interconnect and
`an interconnect provided in an upper level. In this case, a
`re?ex angle at the boundary betWeen the pad and the gate
`interconnect part is rounded due to the optical proximity
`effect, Which causes errors in the dimension of the gate elec
`trode part provided on the active region, namely in the gate
`length of the transistor.
`FIGS. 7A and 7B are a plan vieW illustrating the design
`geometry of a knoWn semiconductor device (e.g., standard
`cell) and a plan vieW illustrating the geometry of the knoWn
`semiconductor device after fabricated, respectively.
`As shoWn in FIG. 7A, in the knoWn semiconductor device,
`a gate polysilicon ?lm is provided across a P-type diffusion
`region and an N-type diffusion region Which are surrounded
`With an element isolation region made of STI or the like. Of
`the gate polysilicon ?lm provided across the P-type and
`N-type diffusion regions and the element isolation region,
`parts located on the P-type and N-type diffusion regions serve
`as gate electrode parts (gates) G101, a part located on the
`element isolation region serves as a gate interconnect part
`G1 02. A rectangular enlarged part having a large area near the
`center of the gate interconnect part G102 serves as a contact
`pad G103, and the contact pad G103 includes a contact C103
`connecting the gate interconnect part G102 and an intercon
`nect provided in an upper level. The P-type diffusion region is
`provided With a P-type transistor With a gate G101 having a
`gate Width W1 and a gate length L, and the N-type diffusion
`region is provided With an N-type transistor With a gate G101
`having a gate Width W2 and a gate length L. In addition, the
`P-type diffusion region is provided With source/ drain contacts
`C101 and C102 and the N-type diffusion regions is provided
`With source/drain contacts C104 and C105.
`FIG. 7B illustrates the geometry of a semiconductor device
`Which has been actually formed on the semiconductor sub
`strate by subjecting the semiconductor device having the
`design geometry illustrated in FIG. 7A to a semiconductor
`device manufacturing process including a photolithographic
`step, an etching step and a resist removing step. As shoWn in
`FIG. 7A, the boundary betWeen the gate interconnect part
`G102 and the contact pad G103 has a re?ex angle rounded
`under the in?uence of the optical proximity effect When
`exposed to light. Accordingly, as shoWn in FIG. 7B, the end of
`the diffusion region located on the side near the contact pad
`G103 has a gate length of L'+AL of Which AL is an error With
`respect to the desired gate length L' on the design geometry. It
`is possible to suppress the error of the gate length caused by
`the optical proximity effect by keeping a su?icient distance
`betWeen the contact pad G103 and the diffusion region. HoW
`ever, this increases the area of the semiconductor device,
`decreases integration density, and hence is not practical.
`
`SUMMARY OF THE INVENTION
`
`The obj ect of the present invention is to provide a structure
`of a semiconductor device Which can suppress variations in
`gate length caused by an optical proximity effect and realiZe
`an LSI having high performance even in a miniaturization
`process.
`The semiconductor device of the present invention is pro
`vided With a gate conductor ?lm of constant dimension in the
`
`

`

`Case 1:16-cv-00290-MN Document 1-9 Filed 04/22/16 Page 12 of 16 PageID #: 255
`
`US 7,709,900 B2
`
`3
`gate length direction including a gate electrode part located
`on a diffusion region and a gate interconnect part located on
`an element isolation region, Wherein the dimension of the
`gate contact in the gate length direction is larger than that of
`the gate interconnect part in the gate length direction.
`According to the present invention, the gate conductor ?lm
`has no re?ex angle in the plan geometry. This provides a
`semiconductor device Which can suppress variations in the
`gate length of a MIS transistor caused by the optical proxim
`ity effect.
`In the case Where a plurality of gate conductor ?lms are
`provided on a single diffusion region, a plurality of gate
`contacts are provided so as to be in contact With gate inter
`connect parts, respectively, and an interconnect in contact
`With the plurality of gate contacts is provided. Thus, the
`semiconductor device achieves the same function as the MIS
`transistor having a comb gate While preventing the variations
`in the gate length of the MIS transistor Which Wouldbe caused
`by the optical proximity effect in the knoWn comb gates.
`Moreover, in the case Where the plurality of gate conductor
`?lms are provided on a single diffusion region, a common
`gate contact extending across the gate interconnect parts is
`used as the gate contact, thereby simplifying the structure.
`In the case Where the gate conductor ?lm has an N-type
`polysilicon ?lm and a P-type polysilicon ?lm, a pair of gate
`contacts are provided Which are individually connected to
`gate interconnect parts for the N-type and P-type polysilicon
`?lms, and an interconnect connected to the pair of gate con
`tacts is provided. According to this structure, it is possible to
`maintain electrical connection of the gate conductor ?lm even
`When the gate conductor ?lm is broken at the P-N boundary.
`In the semiconductor device of the present invention, a
`conductor pad having a larger plane area than the gate contact
`may be further provided on each gate interconnect part to
`bring the gate contact into contact With the conductor pad.
`According to this structure, in forming a gate contact hole and
`source/drain contact holes simultaneously, the gate contact
`hole can be prevented from reaching the element isolation
`region.
`As mentioned above, according to the present invention, it
`is possible to suppress variations in gate length of various
`MIS transistors caused by the generation of the optical prox
`imity effect in the photolithographic step of the MIS transis
`tors. As a result, the design margin can be reduced, and hence
`the LSI having high performance can be provided.
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIGS. 1A and 1B are a plan vieW of the design geometry of
`a semiconductor device according to a ?rst embodiment of
`the present invention, and a plan vieW of the geometry of the
`semiconductor device after fabricated, respectively;
`FIGS. 2A, 2B and 2C are a plan vieW of the geometry of a
`gate polysilicon ?lm provided on an element isolation region
`prior to the formation of an interconnect of a semiconductor
`device according to a second embodiment of the invention, a
`plan vieW of the geometry of the gate polysilicon ?lm and
`other features after the formation of the interconnect, and a
`cross sectional vieW of the geometry thereof taken along line
`IIc-IIc of FIG. 2B, respectively;
`FIGS. 3A and 3B are a plan vieW of a gate polysilicon ?lm
`and other features of a semiconductor device according to a
`third embodiment of the invention, and a cross sectional vieW
`thereof taken along line IIIb-IIIb of FIG. 3A, respectively;
`FIGS. 4A and 4B are a plan vieW illustrating a ?rst modi
`?cation of the third embodiment, and a cross sectional vieW
`illustrating a second modi?cation thereof, respectively;
`
`50
`
`55
`
`60
`
`65
`
`4
`Left sides of FIGS. 5A to 5C are cross sectional vieWs
`illustrating parts of a manufacturing process of a semicon
`ductor device according to a fourth embodiment of the inven
`tion, and right sides of FIGS. 5A to 5C are plan vieWs thereof;
`FIGS. 6A, 6B and 6C are a plan vieW of the geometry of the
`gate polysilicon ?lm provided on the element isolation region
`prior to the formation of the interconnect of the semiconduc
`tor device according to a modi?cation of the fourth embodi
`ment, a plan vieW of the geometry of the gate polysilicon ?lm
`and other features after the formation of the interconnect, and
`a cross sectional vieW of the geometry thereof taken along
`line VIc-VIc of FIG. 6B, respectively; and
`FIGS. 7A and 7B are a plan vieW illustrating the design
`geometry of a knoWn semiconductor device (e.g., standard
`cell) and a plan vieW illustrating the geometry of the knoWn
`semiconductor device after fabricated, respectively.
`
`DETAILED DESCRIPTION OF THE INVENTION
`
`First Embodiment
`
`A ?rst embodiment of the present invention Will be
`described beloW With reference to the draWings. FIGS. 1A
`and 1B are a plan vieW of the design geometry of a semicon
`ductor device (e. g., standard cell) according to the ?rst
`embodiment of the invention, and a plan vieW of the geometry
`thereof after fabricated, respectively.
`As shoWn in FIG. 1A, in the semiconductor device of the
`?rst embodiment, a gate polysilicon ?lm is provided across a
`P-type diffusion region and an N-type diffusion region Which
`are surrounded With an element isolation region made of STI
`or the like. Of the gate polysilicon ?lm G0 Which is used as a
`gate conductor ?lm provided across the P-type and N-type
`diffusion regions and the element isolation region, its parts
`located on the P-type and N-type diffusion regions serve as
`gate electrode parts (gates) G1, and its part located on the
`element isolation region serves as a gate interconnect part G2.
`The gate interconnect part G2 is provided With a contact C3
`for connecting the gate interconnect part G2 to an intercon
`nect provided in an upper level. The P-type diffusion region is
`provided With a P-type transistor With a gate G1 having a gate
`Width W1 and a gate length L, and the N-type diffusion region
`is provided With an N-type transistor With a gate G1 having a
`gate Width W2 and a gate length L. In addition, the P-type
`diffusion region is provided With source/drain contacts C1
`and C2, and the N-type diffusion region is provided With
`source/drain contacts C4 and C5.
`Here, as shoWn in FIG. 1A, the features of the design
`geometry of the semiconductor device according to the ?rst
`embodiment reside in that a contact pad is not provided in the
`gate interconnect part While it is provided in the knoWn semi
`conductor devices, and that the plan geometry of the gate
`polysilicon ?lm G0 is linear (rectangular). In addition, the
`contact C3 provided on the gate polysilicon ?lm G0 has a
`diameter R (especially a dimension in the gate length direc
`tion) larger than the dimension of the gate polysilicon ?lm G0
`in the gate length direction.
`FIG. 1B illustrates the geometry of a semiconductor device
`Which has been actually formed on the semiconductor sub
`strate by subjecting the semiconductor device having the
`design geometry illustrated in FIG. 1A to a semiconductor
`device manufacturing process including a photolithographic
`step, an etching step and a resist removing step.
`As shoWn in FIG. 1B, the gate polysilicon ?lm G0 formed
`on the semiconductor substrate maintains a linear (rectangu
`lar) shape. This is because the design geometry of the gate
`polysilicon ?lm G0 shoWn in FIG. 1A has no re?ex angle, and
`
`

`

`Case 1:16-cv-00290-MN Document 1-9 Filed 04/22/16 Page 13 of 16 PageID #: 256
`
`US 7,709,900 B2
`
`5
`thereby no optical proximity effect occurs. Accordingly, in
`the semiconductor device of the ?rst embodiment, the dimen
`sion of the gate polysilicon ?lm in the gate length direction
`has a substantially constant value L' in all over the element
`isolation region and the P-type and the N-type diffusion
`regions.
`In the ?rst embodiment, the plan design geometry of the
`gate polysilicon ?lm G0 is made linear (rectangular) and the
`dimension thereof in the gate length direction is made con
`stant. Therefore, it is possible to keep the dimensions of gate
`electrode parts G1' in the gate length direction, Which are
`provided on the diffusion regions, constant Without Widening
`the Width of the element isolation region separating the active
`regions. As a result, it is possible to suppress variations in the
`dimension in the gate length direction due to the optical
`proximity effect While keeping the integration density of the
`semiconductor device high.
`
`Second Embodiment
`
`The above ?rst embodiment has described the structure of
`the semiconductor device Which suppresses variations in the
`gate length of the MIS transistor due to the optical proximity
`effect by making the gate electrode linear (rectangular) and
`the dimension thereof in the gate length direction constant.
`NoW, in a CMOS device having a dual-gate structure, a
`p-type impurity is doped into the gate electrode of a P-channel
`MIS transistor, and an n-type impurity is doped into a gate
`electrode of an N-channel MIS transistor. Therefore, a gate
`polysilicon ?lm includes part that provides an N-type poly
`silicon ?lm on a P-type Well region and part that provides a
`P-type polysilicon ?lm on an N-type Well region. Therefore,
`When the dimension of the gate polysilicon ?lm in the gate
`length direction at the boundary betWeen the N-type and the
`P-type polysilicon ?lms is smaller than a certain value, the
`gate polysilicon ?lm may be broken.
`A second embodiment of the invention Will describe a
`structure that can maintain electrical connection even at the
`breakage of the gate polysilicon ?lm While having a gate
`polysilicon ?lm of linear (rectangular) plan geometry.
`FIGS. 2A, 2B and 2C are a plan vieW of the geometry of a
`gate polysilicon ?lm provided on an element isolation region
`prior to the formation of an interconnect of a semiconductor
`device according to the second embodiment, a plan vieW of
`the geometry of the gate polysilicon ?lm and a metal inter
`connect after the formation of the interconnect, and a cross
`sectional vieW thereof taken along line IIc-IIc of FIG. 2B,
`respectively. In FIG. 2C, an interlayer insulating ?lm on
`Which a contact is formed is not shoWn.
`As shoWn in FIG. 2A, a gate interconnect part G12 of a gate
`polysilicon ?lm G10 Which is used as a linear (rectangular)
`gate conductor ?lm having a constant dimension in the gate
`length direction includes an N-type polysilicon ?lm G1211
`located on a P-type Well region and a P-type polysilicon ?lm
`G12b located on an N-type Well region. A ?rst contact C1311
`is provided on the N-type polysilicon ?lm G1211 and a second
`contact C131) is on the P-type polysilicon ?lm G12b. Each
`diameter R of the ?rst and the second contacts C1311, C131) is
`larger than the dimension L of the gate polysilicon ?lm G10
`in the gate length direction.
`As shoWn in FIGS. 2B and 2C, after the formation of the
`interconnect, a metal interconnect M11 is formed on the ?rst
`and the second contacts C1311, C1311 to connect them to each
`other.
`The semiconductor device of the second embodiment is
`provided With the linear (rectangular) gate polysilicon ?lm
`G10 having the ?rst and the second contacts C1311, C131) and
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`the metal interconnect M11, Whereby electrical connection
`betWeen the N-type polysilicon ?lm G1211 and the P-type
`polysilicon ?lm G12b can be maintained even When the
`boundary therebetWeen is broken.
`According to this structure, even When the gate polysilicon
`?lm G10 has a linear (rectangular) plan geometry and has a
`constant dimension in the gate length direction, the breakage
`of the gate polysilicon ?lm G10 can be prevented in the
`boundary region betWeen the P-type Well and the N-type Well
`regions, i.e., betWeen the N-type polysilicon ?lm and the
`P-type polysilicon ?lm.
`
`Third Embodiment
`
`FIGS. 3A and 3B are a plan vieW illustrating the plan
`geometry of a gate polysilicon ?lm and a metal interconnect
`of a semiconductor device according to a third embodiment of
`the invention, and a cross sectional vieW thereof taken along
`line IIIb-IIIb of FIG. 3A, respectively. In FIG. 3B, an inter
`layer insulating ?lm on Which a contact is formed is not
`shoWn.
`As shoW in FIGS. 3A and 3B, the third embodiment
`employs, instead of the comb gate, a structure in Which gate
`interconnect parts G2111 to G210 of a plurality of linear (rect
`angular) gate polysilicon ?lms G2011 to G200 are electrically
`connected to one another via a metal interconnect M21.
`In the semiconductor device of the third embodiment, the
`gate polysilicon ?lms are provided across a P-type diffusion
`region and an N-type diffusion region Which are surrounded
`With an element isolation region made of STI or the like. Of
`the gate polysilicon ?lms G2011 to G200 formed across the
`P-type and the N-type diffusion regions and the element iso
`lation region, their parts located on the P-type diffusion
`region serve as gate electrode parts (gates) G2111 to G210,
`respectively, and their parts located on the N-type region
`serve as gate interconnect parts G2211 to G220, respectively.
`The semiconductor device has gate contacts C2311 to C230
`that pass through the interlayer insulating ?lm and is then
`connected to the gate interconnect parts G2211 to G220 to
`connect an upper interconnect to the gate polysilicon ?lms
`G2011 to G200. In addition, the semiconductor device has the
`metal interconnect M21 that is connected to the gate contact
`C2311 to C230. The gate contacts C2311 to C230 have a diam
`eter R (especially a dimension in the gate length direction)
`larger than the dimension L of the gate polysilicon ?lm G20
`in the gate length direction.
`The P-type diffusion region is provided With a P-type MIS
`transistor With gates G2111 to G210 having a gate Width W1
`and a gate length L, and the N-type diffusion region is pro
`vided With an N-type MIS transistor With the gates G2111 to
`G210 having a gate Width W2 and a gate length L. In addition,
`each of the P-type and N-type diffusion regions is provided
`With source/ drain contacts C26.
`The knoWn comb gate electrode has a structure in Which a
`re?ex angle alWays exists at the connection part of each gate,
`Which generates variations in the gate length of the MIS
`transistor due to the optical proximity effect in the manufac
`turing process. On the other hand, in the third embodiment,
`the plurality of gate polysilicon ?lms are electrically con
`nected to one another by the metal interconnect via the con
`tacts provided on the gate interconnect parts, and therefore it
`is possible to make each gate polysilicon ?lm linear (rectan
`gular) and keep the constant dimension in the gate length
`direction. As a result, the variations in the gate length of the
`MIS transistor due to the optical proximity effect can be
`suppressed.
`
`

`

`Case 1:16-cv-00290-MN Document 1-9 Filed 04/22/16 Page 14 of 16 PageID #: 257
`
`US 7,709,900 B2
`
`7
`Note that When the third embodiment is applied to cells
`requiring exacting tolerances for the gate length of a MIS
`transistor, such as a clock cell, signi?cant effects can be
`achieved.
`
`iModi?cations of Third Embodimenti
`FIGS. 4A and 4B are a plan vieW illustrating a ?rst modi
`?cation of the third embodiment, and a cross sectional vieW
`illustrating a second modi?cation thereof, respectively.
`As shoWn in FIG. 4A, a semiconductor device according to
`the ?rst modi?cation of the third embodiment has, instead of
`the contacts provided on the gate interconnect parts and on
`part of the element isolation region located betWeen the
`P-type and the N-type diffusion regions, pairs of contacts
`C2311, C2311 to C230, C230 provided on the gate interconnect
`parts G2211 to G220 and on parts of the element isolation
`region betWeen Which the P-type diffusion region and the
`N-type diffusion region are interposed. The semiconductor
`device also has a metal interconnect M21 provided on the
`pairs of contacts C2311, C2311 to C230, C230 to electrically
`connect the contacts C2311, C2311 to C230, C230 to one
`another. The structures of the gate polysilicon ?lms G2011 to
`G200, the P-type diffusion region and the N-type diffusion
`region and the source/drain contacts C26 are the same as in
`the third embodiment.
`Although not shoWn, an N-type Well region and a P-type
`Well region are provided beloW the P-type and the N-type
`diffusion regions, respectively, and the gate polysilicon ?lms
`G2011 to G200 serve as the P-type polysilicon ?lm on the
`N-type Well region and as the N-type polysilicon ?lm on the
`P-type Well region. Therefore, each of the gate polysilicon
`?lms G2011 to G200 has the boundary betWeen the P-type
`polysilicon ?lm and the N-type polysilicon ?lm in the vicinity
`of the middle betWeen the N-type and P-type Well regions.
`According to the ?rst modi?cation, like the third embodi
`ment, it is possible to suppress the variations in the gate length
`of the MIS transistor Which Would be caused by the optical
`proximity effect in comb gates. In addition to the effect
`obtained in the third embodiment, like the second embodi
`ment, it is possible to maintain electrical connection of each
`of the gate polysilicon ?lms G2011 to G200 even When the
`boundary region betWeen the N-type polysilicon ?lm and the
`P-type polysilicon ?lm is broken.
`As shoWn in FIG. 4B, in the semiconductor device accord
`ing to a second modi?cation of the third embodiment, the gate
`interconnect parts G2211 to G220 of the gate polysilicon ?lms
`G2011 to G200 are electrically connected to one another via a
`common gate contact P21 Which is formed thereon. In other
`Words, a common gate contact P21 is provided instead of the
`contacts C2311 to C230 and the metal interconnect M21 of the
`third embodiment.
`According to the second modi?cation, like the third
`embodiment, it is possible to suppress the variations in the
`gate length of the MIS transistor Which Would be caused by
`the optical proximity effect in comb gates.
`It can be considered that a mask is not aligned in introduc
`ing p-type and n-type impurities for a dual gate into the gate
`polysilicon ?lm G20. To cope With this, the common gate
`contact P21 is set to have such a dimension in the direction
`perpendicular to the gate length that the common gate contact
`P21 is overlapped With both the N-type polysilicon ?lm and
`the P-type polysilicon ?lm in plan vieW. Thereby, in addition
`to the effect obtained in the third embodiment and like the
`second embodiment, it is possible to maintain electrical con
`nection of each of the gate polysilicon ?lms G2011 to G200
`even When the boundary region betWeen the N-type polysili
`con ?lm and the P-type polysilicon ?lm is broken.
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`Note that in the third embodiment, the semiconductor
`device may be