Case 1:16-cv-00290-MN Document 1-2 Filed 04/22/16 Page 1 of 22 PageID #: 60
`Case 1:16-cv-OO290-MN Document 1-2 Filed 04/22/16 Page 1 of 22 PageID #: 60
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`
`
`EXHIBIT B
`
`
`
`

`

`Case 1:16-cv-00290-MN Document 1-2 Filed 04/22/16 Page 2 of 22 PageID #: 61
`
`(12) United States Patent
`Tamaki et al.
`
`(10) Patent N0.:
`(45) Date of Patent:
`
`US 6,794,677 B2
`Sep. 21, 2004
`
`US006794677B2
`
`(54) SEMICONDUCTOR INTEGRATED CIRCUIT
`DEVICE AND METHOD FOR FABRICATING
`THE SAME
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`5,410,161 A *
`5,598,010 A
`5,698,902 A
`5,847,421 A
`5,943,256 A
`5,952,698 A
`
`*****
`
`Narita ....................... .. 257/41
`
`4/1995
`1/1997
`257/48
`Uematsu ...... ..
`12/1997
`257/773
`Uehara et a1. .
`12/1998
`257/207
`Yamaguchi ..... ..
`365/145
`8/1999 Shimizu et al.
`9/1999 Wong et al. .............. .. 257/401
`
`FOREIGN PATENT DOCUMENTS
`
`JP
`JP
`JP
`JP
`JP
`
`60124941
`03 18004 1
`07335844
`10-200109
`2000-150828
`
`7/1985
`8/1991
`12/1995
`7/1998
`5/2000
`
`* cited by examiner
`Primary Examiner—Duy-Vu Deo
`(74) Attorney, Agent, or Firm—McDermott, Will & Emery
`(57)
`ABSTRACT
`
`Variations in the siZe of a linear pattern resulting from
`difference in mask pattern layout are prevented by setting the
`perimeter of the linear pattern per unit area in a speci?ed
`range irrespective of the type of a semiconductor integrated
`circuit device or by adjusting a process condition in accor
`dance With type-to-type difference in the perimeter of the
`linear pattern per unit area.
`
`6 Claims, 9 Drawing Sheets
`
`El iDRAM Unmounted Type
`I IDRAM Mounted Type
`
`(75) Inventors: Tokuhiko Tamaki, Osaka (JP); Koichi
`Kawashima, Kyoto (JP); Yasuo
`Sakurai, Kyoto (JP); Kenji TateiWa,
`Osaka (JP)
`
`(73) Assignee:
`
`Matsushita Electric Industrial Co.,
`Ltd., Osaka (JP)
`
`( * ) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`USC 154(b) by 168 days.
`
`(21)
`(22)
`(65)
`
`Appl. No.: 09/964,868
`Filed:
`Sep. 28, 2001
`
`Prior Publication Data
`
`US 2002/0061652 A1 May 23, 2002
`Foreign Application Priority Data
`
`(30)
`Oct. 2, 2000
`
`(JP) ..................................... .. 2000-302277
`
`(51) Int. Cl.7 .................... .. H01L 29/06; H01L 31/0352
`(52) us. Cl. ........................... .. 257/41; 257/2; 257/390;
`257/401
`(58) Field of Search ..................... .. 257/41, 2, 202—211,
`257/390, 401
`
`40
`
`30
`
`20
`
`a:
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`3
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`>4
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`g 10
`#4
`LL
`
`J1
`~
`J
`
`~
`
`~
`
`-O. 02 -O. 01 0.00
`CD Loss (u m)
`
`+0.01 +0.02 +0.03 +0. 04
`
`

`

`Case 1:16-cv-00290-MN Document 1-2 Filed 04/22/16 Page 3 of 22 PageID #: 62
`
`U.S. Patent
`
`Sep. 21, 2004
`
`Sheet 1 0f 9
`
`US 6,794,677 B2
`
`FIG.1
`
`FIG. 2
`
`

`

`Case 1:16-cv-00290-MN Document 1-2 Filed 04/22/16 Page 4 of 22 PageID #: 63
`Case 1:16-cv-OO290-MN Document 1-2 Filed 04/22/16 Page 4 of 22 PageID #: 63
`
`US. Patent
`
`Sep. 21, 2004
`
`Sheet 2 0f 9
`
`US 6,794,677 B2
`
`FIG.3A
`
`12
`
`11
`
`
`
`IIZII<
`
`,IZIIIZII
`
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`11 12
`
`12
`
`FIG.3B
`
`
`
`

`

`Case 1:16-cv-00290-MN Document 1-2 Filed 04/22/16 Page 5 of 22 PageID #: 64
`
`U.S. Patent
`
`Sep. 21, 2004
`
`Sheet 3 0f 9
`
`US 6,794,677 B2
`
`FIG. 4
`
`I I I I
`
`+0. 005
`
`K
`
`i
`
`m
`O
`
`6
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`—0.005
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`:
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`1
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`’
`0.06
`
`0.08
`
`0. l0
`
`HBr Flow Rate (SLM)
`
`

`

`Case 1:16-cv-00290-MN Document 1-2 Filed 04/22/16 Page 6 of 22 PageID #: 65
`
`U.S. Patent
`
`Sep. 21, 2004
`
`Sheet 4 0f 9
`
`US 6,794,677 B2
`
`24
`
`21
`
`FIG. 5A
`
`FIG. 5B
`
`FIG.
`
`,
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`
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`PM’ ////////// 21
`
`

`

`Case 1:16-cv-00290-MN Document 1-2 Filed 04/22/16 Page 7 of 22 PageID #: 66
`Case 1:16-cv-OO290-MN Document 1-2 Filed 04/22/16 Page 7 of 22 PageID #: 66
`
`US. Patent
`
`Sep. 21, 2004
`
`Sheet 5 0f 9
`
`US 6,794,677 B2
`
`FIG. 6
`
`+0.030
`
`”+5
`1
`
`m
`U)
`
`3
`Q
`Q
`
`+0.025
`
`+0.020
`
`+0. 015
`_
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`+0.010
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`
`'1
`
`DRAM
`Unmounted ,
`’
`‘
`
`/’
`x Type
`
`O
`
`50
`
`100
`
`DRAM Area~Occupying Rate (%)
`
`

`

`Case 1:16-cv-00290-MN Document 1-2 Filed 04/22/16 Page 8 of 22 PageID #: 67
`
`U.S. Patent
`
`Sep. 21, 2004
`
`Sheet 6 6f 9
`
`US 6,794,677 B2
`
`+0. 030 _
`
`+0. 025 n
`E
`+0. 020 j :
`
`
`
`2 +0. 015 I 5 1
`
`
`
`I/
`,/
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`/'.
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`
`
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`
`
`a s C2
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`
`+0. 010 +0.
`
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`\__ xUnmounted
`—0. 005 I
`We
`
`_0' 010 0
`
`50
`
`100
`
`DRAM Area-Occupying Rate (%)
`
`

`

`Case 1:16-cv-00290-MN Document 1-2 Filed 04/22/16 Page 9 of 22 PageID #: 68
`
`U.S. Patent
`
`Sep. 21, 2004
`
`Sheet 7 0f 9
`
`US 6,794,677 B2
`
`
`
`
`
`Frequency (Arbitrary Unit)
`
`FIG. 8
`
`El IDRAM Unmounted Type
`I IDRAM Mounted Type
`
`40
`
`[\D O
`
`—O. 02 -O. 01
`
`O. 00 +0. 01 +0. 02 +0. 03 +0. 04
`
`CD Loss (um)
`
`

`

`Case 1:16-cv-00290-MN Document 1-2 Filed 04/22/16 Page 10 of 22 PageID #: 69
`
`U.S. Patent
`
`Sep. 21, 2004
`
`Sheet 8 0f 9
`
`US 6,794,677 B2
`
`FIG. 9
`
`2 1 1
`
`O O O O O 5 O 5
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`ANEEBEV mm; is: 5mm mwo?ogm gnu we umpmscwm
`
`
`
`
`
`

`

`Case 1:16-cv-00290-MN Document 1-2 Filed 04/22/16 Page 11 of 22 PageID #: 70
`
`U.S. Patent
`
`Sep. 21, 2004
`
`Sheet 9 0f 9
`
`US 6,794,677 B2
`
`+0. 015 _
`
`E
`+0010
`:
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`c»
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`0
`500
`1000
`1500
`2000
`Perimeter of Gate Electrode Per Unit Area (mm/m2)
`
`

`

`Case 1:16-cv-00290-MN Document 1-2 Filed 04/22/16 Page 12 of 22 PageID #: 71
`
`US 6,794,677 B2
`
`1
`SEMICONDUCTOR INTEGRATED CIRCUIT
`DEVICE AND METHOD FOR FABRICATING
`THE SAME
`
`BACKGROUND OF THE INVENTION
`
`The present invention relates to a semiconductor inte
`grated circuit device and a method for fabricating the same.
`More particularly, it relates to technology for forming a
`linear pattern composed of the gate electrode and Wires of a
`MOS transistor, or metal Wires, and the like in a system LSI
`in Which a group of elements having an extremely ?ne
`repetitive pattern, such as DRAMs (Dynamic Random
`Access Memories), can be merged.
`As an eXample of a semiconductor integrated circuit
`device in Which DRAMs are merged, a system LSI on Which
`DRAMs having a capacity over 20 megabits are mounted
`has been mass-produced in recent years.
`In the fabrication steps for a semiconductor integrated
`circuit device represented by the system LSI in Which the
`mounting rate of memory circuits such as DRAMs, SRAMs
`(Static Random Access Memories), or ROMs (Read Only
`Memories) on a single semiconductor chip (rate of an area
`occupied by the memory circuits to an area of the entire
`chip; hereinafter also referred to as an area-occupying rate)
`differs according to usage or speci?cations, the formation of
`a mask pattern having not only unit circuits Which are simply
`and repeatedly arranged therein but also a variety of layouts
`has been required.
`There has conventionally been knoWn a phenomenon in
`Which the con?guration or siZe of a pattern obtained by
`etching a target ?lm by using a mask pattern (hereinafter
`referred to as a formed pattern) differs depending on a mask
`pattern layout, i.e., the placement of an element pattern.
`As an eXample of the phenomenon, a pattern proXimity
`effect occurring during the formation of a resist pattern in a
`photolithographic step can be listed. This is the phenomenon
`in Which even a pattern having the same design con?gura
`tion and the same design siZe has different con?gurations
`and siZes after it is formed depending on the degree of
`proXimity betWeen the pattern and a pattern adjacent thereto
`or on the con?guration of the adjacent pattern.
`As another eXample, there can be listed a loading effect or
`a microloading effect occurring in a dry etching step. The
`loading effect is a phenomenon in Which an etching rate
`varies depending on the siZe of a total etched area of a
`semiconductor chip, Which may slightly affect variations in
`pattern siZe. The microloading effect is a phenomenon in
`Which, When a pattern laid out in a single semiconductor
`chip shoWs an arrangement Which is locally sparse and
`dense, an etching rate differs locally due to the locally dense
`and sparse arrangement. That is, the etching rate for even the
`single chip differs from the portion thereof on Which the
`pattern is sparsely placed to the portion thereof on Which the
`pattern is densely placed, Which also indirectly affects
`variations in pattern siZe.
`To solve the foregoing problem of variations in pattern
`siZe depending on the mask pattern layout, there have
`conventionally been adopted such design rules as to correct
`variations in pattern siZe only at a portion of a mask Where
`the pattern siZe is considered to vary remarkably depending
`on the mask pattern layout due to the proXimity effect or the
`loading effect.
`On the other hand, the fabrication of a system LSI in
`Which DRAMs can be merged has used the same processing
`
`10
`
`15
`
`25
`
`35
`
`40
`
`45
`
`55
`
`65
`
`2
`method or the same processing condition irrespective of the
`presence or absence of a mounted DRAM or of a DRAM
`area-occupying rate (the rate of an area occupied by the
`DRAMs to the area of an entire chip).
`With the increasing miniaturiZation of the LS1, speci?
`cally as the siZe of an integrated circuit pattern is reduced to
`0.25 pm or less, particularly to 0.15 pm or less, higher
`precision siZe control has been required so that siZe varia
`tions resulting from difference in mask pattern layout are no
`more negligible.
`FIG. 8 shoWs the frequency distribution of a CD (critical
`dimension) loss Which is the difference betWeen the siZe of
`a resist pattern prior to etching and the siZe of a completed
`gate electrode When the gate electrode is formed by dry
`etching by using the resist pattern as a mask in the fabrica
`tion of each of semiconductor integrated circuit devices on
`Which 24 Mb DRAMs are mounted (hereinafter referred to
`as a DRAM mounted type) and a semiconductor integrated
`circuit device on Which DRAMs are not mounted
`(hereinafter referred to as a DRAM unmounted type). The
`result shoWn in FIG. 8 Was obtained by using the same
`gate-electrode forming process in the fabrication of each of
`the DRAM mounted type and the DRAM unmounted type.
`Each of the CD losses Was calculated by subtracting the siZe
`of the completed gate electrode from the siZe of the resist
`pattern prior to etching.
`As shoWn in FIG. 8, mask-pattern-layout dependency is
`observed in pattern siZe though the same gate-electrode
`forming process Was used to fabricate each of the types.
`This indicates that, in accordance With the conventional
`method for fabricating a semiconductor integrated circuit
`device, the gate electrode siZe varies With difference in mask
`pattern layout associated With different types of semicon
`ductor integrated circuit devices even if the same gate
`electrode forming process is used. In other Words, type
`dependency occurs in gate electrode siZe. As a result, the
`characteristics of a MOS transistor deviate from design
`speci?cations in a speci?ed type of semiconductor inte
`grated circuit device fabricated by using a speci?ed mask,
`Which causes the problem of a narroWer operating margin.
`The problem cannot be ignored especially When the design
`rules are 0.18 pm or less.
`
`SUMMARY OF THE INVENTION
`In vieW of the foregoing, it is therefore an object of the
`present invention to prevent a siZe variation resulting from
`difference in mask pattern layout during the formation of a
`linear pattern composed of the gate electrode and Wires of a
`MOS transistor, or metal Wires, and the like.
`To attain the object the present inventors have examined
`the cause of siZe variations resulting from difference in mask
`pattern layout.
`As a result the examination, the present inventors have
`found that, in a semiconductor integrated circuit device on
`Which a logic circuit composed of a CMOS (Complementary
`Metal-Oxide Semiconductor) is mounted and a memory
`circuit such as a DRAM composed of the gate electrode and
`Wires that are densely arranged is mounted, pattern siZe
`varies With the area-occupying rate of the memory circuit.
`The present inventors have also found that the phenom
`enon in Which siZe variations result from difference in mask
`pattern layout is different in nature from the foregoing
`loading effect Which results from the siZe of the etched area,
`i.e., the area of the pattern. As is obvious from FIG. 8, the
`phenomenon is a phenomenon of novel nature in Which the
`pattern siZe varies over the entire chip, Which is also
`
`

`

`Case 1:16-cv-00290-MN Document 1-2 Filed 04/22/16 Page 13 of 22 PageID #: 72
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`US 6,794,677 B2
`
`3
`different from the microloading effect resulting from the
`in-chip local denseness and sparseness of the pattern.
`As described above, the type dependency of the siZe of the
`formed gate electrode or the like results from the CD loss.
`On the other hand, a dry etching step currently performed
`uses an etching gas having a sideWall protecting effect
`(hereinafter referred to as a deposition gas) or forms an
`etching reaction product having the sideWall protecting
`effect to achieve anisotropic dry etching by preventing side
`etching. If a gate electrode is formed by performing dry
`etching With respect to a polysilicon ?lm, a chlorine
`containing gas, e.g., is used frequently as the etching gas and
`HBr gas is used frequently as the deposition gas. As a result,
`a sideWall protecting ?lm composed of SiBr4, Which is a
`reaction product betWeen HBr and polysilicon and has loW
`volatility, is formed on a sideWall of the polysilicon ?lm. In
`the case of forming aluminium Wires by performing dry
`etching With respect to an aluminium ?lm, a CHF3 gas has
`been used frequently as the deposition gas in recent years.
`The CHF3 gas containing ?uorine is a depositive gas added
`to form the sideWall protecting ?lm but does not contribute
`to the etching of the aluminium ?lm.
`The present inventors have found that, if the con?guration
`of the target ?lm after etching is to be controlled With the
`sideWall protecting effect in the case of using the same
`gate-electrode forming process irrespective of the mask
`pattern layout, the sideWall protecting effect per unit area is
`reduced as the area of the sideWall of the target ?lm to be
`protected increases, Which increases the CD loss.
`FIG. 9 shoWs the relationship betWeen the perimeter of a
`gate electrode per unit area (the length of the peripheral
`portion of the gate electrode) and the DRAM area
`occupying rate in each of various types of semiconductor
`integrated circuit devices having different DRAM area
`occupying rates including the DRAM unmounted type. In
`the graph of FIG. 9, “Perimeter of Gate Electrode Per Unit
`Area” represented by the vertical aXis indicates the value
`obtained by dividing the total perimeter of the gate elec
`trodes in a speci?ed circuit region by the area of the
`speci?ed circuit region. The speci?ed circuit region may be
`the entire chip.
`As shoWn in FIG. 9, the perimeter of the gate electrode
`per unit area increases as the DRAM area-occupying rate
`increases.
`FIG. 10 shoWs the relationship betWeen the perimeter of
`the gate electrode per unit area and the CD loss in each of
`the various types.
`As shoWn in FIG. 10, the siZe of the gate electrode
`decreases as the perimeter of the gate electrode per unit area
`increases (the CD loss becomes positive). Conversely, the
`siZe of the gate electrode increases as the perimeter of the
`gate electrode per unit area decreases (the CD loss becomes
`negative). This is because the area of the sideWall to be
`protected increases as the perimeter of the gate electrode per
`unit area increases so that the sideWall protecting effect per
`unit area is reduced accordingly.
`The present inventors have focused attention on the fact
`that the CD loss changes monotonously from a negative
`value to a positive value as the perimeter of the gate
`electrode per unit area increases (see FIG. 10) and found that
`siZe variations in gate electrode pattern resulting from
`difference in mask pattern layout can be prevented by setting
`the perimeter of the gate electrode per unit area in a speci?ed
`range irrespective of the type or adjusting a process condi
`tion in accordance With type-to-type difference in the perim
`eter per unit area of the gate electrode.
`
`10
`
`15
`
`25
`
`35
`
`40
`
`45
`
`55
`
`65
`
`4
`Speci?cally, a ?rst semiconductor integrated circuit
`device according to the present invention assumes a semi
`conductor integrated circuit device comprising: a circuit
`pattern having a linear pattern, a perimeter of the linear
`pattern per unit area being set in a speci?ed range.
`In the ?rst semiconductor integrated circuit device, the
`perimeter of the linear pattern per unit area is set in the
`speci?ed range. Accordingly, even if a mask pattern layout
`differs greatly from one type of semiconductor integrated
`circuit device to another, siZe variations in linear pattern
`resulting from difference in mask pattern layout can be
`prevented. In a system LSI in Which the mounting rate of
`DRAMs or the like is different depending on use or speci
`?cations also, it is possible to form gate electrode patterns,
`metal Wires, or the like of uniform siZes irrespective of the
`mask pattern layout, so that a semiconductor integrated
`circuit device free of variations in operating margin is
`provided.
`A second semiconductor integrated circuit device accord
`ing to the present invention assumes a semiconductor inte
`grated circuit device comprising: a circuit pattern having a
`linear pattern, a dummy pattern being inserted in a region in
`Which the circuit pattern is placed such that a sum perimeter
`of the linear pattern and the dummy pattern per unit area is
`set in a speci?ed range.
`In the second semiconductor integrated circuit device, the
`sum perimeter of the linear pattern and the dummy pattern
`per unit area is set in the speci?ed range. Accordingly, even
`if a mask pattern layout differs greatly from one type of
`semiconductor integrated circuit device to another, siZe
`variations in linear pattern resulting from difference in mask
`pattern layout can be prevented. In a system LSI in Which the
`mounting rate of DRAMs or the like is different depending
`on use or speci?cations also, it is possible to form gate
`electrode patterns, metal Wires, or the like of uniform siZes
`irrespective of the mask pattern layout, so that a semicon
`ductor integrated circuit device free of variations in operat
`ing margin is provided.
`In the second semiconductor integrated circuit device, the
`dummy pattern preferably has a strip-like con?guration.
`This alloWs easy formation of the dummy pattern.
`A third semiconductor integrated circuit device according
`to the present invention assumes a semiconductor integrated
`circuit device comprising: a ?rst circuit pattern having a ?rst
`linear pattern and placed in a region in Which a group of
`elements having a repetitive pattern are formed; and a
`second circuit pattern having a second linear pattern and
`placed in a region in Which components other than the group
`of elements are formed, a dummy pattern being inserted in
`the region in Which the second circuit pattern is placed such
`that a sum perimeter of the ?rst linear pattern, the second
`linear pattern, and the dummy pattern per unit area is equal
`to or less than a perimeter of the ?rst linear pattern per unit
`area.
`In the third semiconductor integrated circuit device, the
`dummy pattern is inserted in the region in Which the second
`circuit pattern corresponding to the components other than
`the group of elements is placed, Whereby the sum perimeter
`per unit area of the ?rst linear pattern of the ?rst circuit
`pattern corresponding to the group of elements, the second
`linear pattern of the second circuit pattern, and the dummy
`pattern is set to the perimeter of the ?rst linear pattern per
`unit area, i.e., the largest perimeter per unit area or less.
`Speci?cally, the sum perimeter per unit area is preferably set
`to 70% to 100% of the perimeter per unit area of the ?rst
`linear pattern. Since the sum perimeter per unit area is set in
`
`

`

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`US 6,794,677 B2
`
`5
`the speci?ed range, even if a mask pattern layout differs
`greatly from one type of semiconductor integrated circuit
`device to another, siZe variations in linear pattern resulting
`from difference in mask pattern layout can be prevented. In
`a system LSI in Which the mounting rate of DRAMs or the
`like is different depending on use or speci?cations also, it is
`possible to form gate electrode patterns, metal Wires, or the
`like of uniform siZes irrespective of the mask pattern layout,
`so that a semiconductor integrated circuit device free of
`variations in operating margin is provided.
`In the third the semiconductor integrated circuit, the
`group of elements are preferably memories.
`In the third the semiconductor integrated circuit, a perim
`eter of the dummy pattern per unit area is preferably 70% or
`more of the perimeter of the ?rst linear pattern per unit area.
`The insertion of the dummy pattern ensures the setting of
`the sum perimeter per unit area in the speci?ed range,
`speci?cally 70% to 100% of the perimeter of the ?rst linear
`pattern per unit area.
`A ?rst method for fabricating a semiconductor integrated
`circuit device assumes a method for fabricating a plurality of
`semiconductor integrated circuit devices each comprising a
`circuit pattern having a linear pattern, at least one of
`fabrication steps for the semiconductor integrated circuit
`devices being common, the fabrication steps including the
`step of: inserting a dummy pattern in a region in Which the
`circuit pattern is placed such that a sum perimeter of the
`linear pattern and the dummy pattern per unit area is set in
`a speci?ed range.
`In accordance With the ?rst method for fabricating a
`semiconductor integrated circuit device, the dummy pattern
`is inserted such that the sum perimeter of the linear pattern
`and the dummy pattern per unit area is set in the speci?ed
`range. Speci?cally, it is desirable to assume, as the speci?ed
`range, 70% to 100% of the perimeter of the linear pattern per
`unit area in a memory circuit. To satisfy the standard, the
`perimeter of the inserted dummy pattern per unit area should
`be 70% or more of the perimeter of the linear pattern per unit
`area in the memory circuit. The present inventors have found
`that the CD loss in the formed pattern or the siZe of the
`formed pattern changes depending on the perimeter of the
`formed pattern per unit area. Accordingly, even if a mask
`pattern layout differs greatly from one type of semiconduc
`tor integrated circuit device to another, the sum perimeter of
`the linear pattern and the dummy pattern per unit area can be
`set in the speci?ed range by forming an additional dummy
`pattern having a perimeter per unit area of 70% or more of
`that of the linear pattern of the memory circuit in a vacant
`region. For example, the perimeter of the gate electrode per
`unit area over the entire chip is largely dependent on a
`speci?ed circuit such as a memory circuit since the speci?ed
`circuit has a large perimeter of the gate electrode per unit
`area. Even if the in-chip area-occupying rate of such a
`speci?ed circuit varies from one type to another, variations
`in the perimeter of the gate electrode per unit area over the
`entire chip can be suppressed by using the dummy pattern,
`as described above. As a result, siZe variations resulting
`from difference in mask pattern layout can be prevented. In
`short, the linear pattern can constantly be formed by etching
`With high precision. In a system LSI in Which the mounting
`rate of DRAMs, SRAMs, ROMS, or the like is different
`depending on use or speci?cations also, it is possible to form
`the gate electrode and Wires for MOS transistors, metal
`Wires, or the like of uniform siZes irrespective of the mask
`pattern layout, so that a semiconductor integrated circuit
`device free of variations in operating margin is provided.
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`A second method for fabricating a semiconductor inte
`grated circuit device assumes a method for fabricating a
`semiconductor integrated circuit device, the method com
`prising the steps of: exposing each of a plurality of ?rst
`regions of a semiconductor substrate to transfer a circuit
`pattern having a linear pattern onto the ?rst region; exposing
`each of a plurality of second regions of the semiconductor
`substrate other than the ?rst regions to transfer a dummy
`pattern onto the second region; and adjusting a ratio betWeen
`the number of exposing shots for transferring the circuit
`pattern and the number of exposing shots for transferring the
`dummy pattern such that a sum perimeter of all the linear
`patterns transferred and all the dummy patterns transferred
`per unit area is set in a speci?ed range.
`In accordance With the second method for fabricating a
`semiconductor integrated circuit device, the ratio betWeen
`the number of exposing shots for transferring the circuit
`pattern and the number of exposing shots for transferring the
`dummy pattern is adjusted such that the sum perimeter of all
`the linear patterns transferred and all the dummy patterns
`transferred per unit area is set in the speci?ed range.
`Accordingly, even if a mask pattern layout differs greatly
`from one type of semiconductor integrated circuit device to
`another, siZe variations in linear pattern resulting from
`difference in mask pattern layout can be prevented. In a
`system LSI in Which the mounting rate of DRAMs or the
`like is different depending on use or speci?cations also, it is
`possible to form gate electrode patterns, metal Wires, or the
`like of uniform siZes irrespective of the mask pattern layout,
`so that a semiconductor integrated circuit device free of
`variations in operating margin is provided.
`A third method for fabricating a semiconductor integrated
`circuit devices assumes a method for fabricating a plurality
`of semiconductor integrated circuit devices each comprising
`a circuit pattern having a linear pattern, at least one of
`fabrication steps for the semiconductor integrated circuit
`devices being common, the fabrication steps including the
`step of: performing dry etching With respect to a target ?lm
`While adjusting a dry etching condition in accordance With
`a perimeter of the linear pattern per unit area.
`In accordance With the third method for fabricating a
`semiconductor integrated circuit device, dry etching is per
`formed With respect to the target ?lm While adjusting the dry
`etching condition in accordance With the perimeter of the
`linear pattern per unit area. Accordingly, even if a mask
`pattern layout differs greatly from one type of semiconduc
`tor integrated circuit device to another, the siZe of the linear
`pattern can be held constantly at a speci?ed value. In a
`system LSI in Which the mounting rate of DRAMs or the
`like is different depending on use or speci?cations also, it is
`possible to form gate electrode patterns, metal Wires, or the
`like of uniform siZes irrespective of the mask pattern layout,
`so that a semiconductor integrated circuit device free of
`variations in operating margin is provided.
`In the third method for fabricating a semiconductor inte
`grated circuit device, the step of adjusting the dry etching
`condition preferably includes the step of: determining one
`dry etching condition When the perimeter of the linear
`pattern per unit area is Within one range.
`The arrangement alloWs easy adjustment of the dry etch
`ing condition.
`A fourth method for fabricating a semiconductor inte
`grated circuit device assumes a method for fabricating a
`plurality of semiconductor integrated circuit devices each
`comprising a circuit pattern having a linear pattern, at least
`one of fabrication steps for the semiconductor integrated
`
`

`

`Case 1:16-cv-00290-MN Document 1-2 Filed 04/22/16 Page 15 of 22 PageID #: 74
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`US 6,794,677 B2
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`7
`circuit devices being common, the fabrication steps includ
`ing the step of: forming a resist pattern corresponding to the
`linear pattern While adjusting a siZe of the resist pattern in
`accordance With a perimeter of the linear pattern per unit
`area.
`In accordance With the fourth method for fabricating a
`semiconductor integrated circuit device, the resist pattern
`corresponding to the linear pattern is formed While the siZe
`of the resist pattern is adjusted in accordance With the
`perimeter of the linear pattern per unit area. Accordingly,
`even if a mask pattern layout differs greatly from one type
`of semiconductor integrated circuit device to another, the
`siZe of the linear pattern can be held constantly at a speci?ed
`value. In a system LSI in Which the mounting rate of
`DRAMs or the like is different depending on use or speci
`?cations also, it is possible to form gate electrode patterns,
`metal Wires, or the like of uniform siZes irrespective of the
`mask pattern layout, so that a semiconductor integrated
`circuit device free of variations in operating margin is
`provided.
`A?fth method for fabricating a semiconductor integrated
`circuit devices assumes a method for fabricating a plurality
`of semiconductor integrated circuit devices each comprising
`a circuit pattern having a linear pattern, at least one of
`fabrication steps for the semiconductor integrated circuit
`devices being common, the fabrication steps including: a
`?rst step of forming a resist pattern corresponding to the
`linear pattern on a target ?lm; and a second step of perform
`ing dry etching With respect to the target ?lm by using the
`resist pattern as a mask, the second step including the step
`of: using an etching gas having an effect of protecting a
`sideWall formed in the target ?lm through the etching or
`forming an etching reaction product having the sideWall
`protecting effect, a processing method or a processing con
`dition in at least one of the ?rst and second steps being
`adjusted in accordance With a ratio betWeen an area occu
`pied by a group of elements contained in the circuit pattern
`and having a repetitive pattern and an area of a region in
`Which the circuit pattern is placed.
`In the ?rst step of forming the resist pattern corresponding
`to the linear pattern or in the second step of performing dry
`etching With respect to the target ?lm by using the resist
`pattern as a mask, the ?fth method for fabricating a semi
`conductor integrated circuit device changes the processing
`method or the processing condition in accordance With the
`rate of the area occupied by the group of elements having the
`repetitive pattern to the area of the region in Which the
`circuit pattern is placed (hereinafter referred to as a group
`of-elements area-occupying rate). Accordingly, even if the
`area of the sideWall formed in the target ?lm through etching
`differs according to difference in group-of-elements area
`occupying rates, i.e., difference in mask pattern layout, it is
`possible to adjust the siZe of the resist pattern in the ?rst step
`so as to eliminate difference in sideWall protecting effects
`per unit area in the second step or adjust the etching
`condition in the second step to achieve a desired sideWall
`protecting effect per unit area. This prevents siZe variations
`resulting from difference in mask pattern layout during the
`formation of the circuit pattern by using a lithographic or dry
`etching technique and thereby alloWs high-precision forma
`tion of a gate electrode or Wires.
`In the ?fth method for fabricating a semiconductor inte
`grated circuit device, the group of elements are preferably
`memories such as DRAMs.
`In the ?fth method for fabricating a semiconductor inte
`grated circuit device, the ?rst step preferably includes the
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`step of: increasing a siZe of the resist pattern as the group
`of-elements area-occupying rate increases.
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`In the arrangement, the area of the sideWall formed in the
`target ?lm through etching increases as the group-of
`elements area-occupying rate increases. Accordingly, even if
`the sideWall protecting effect per unit area decreases in the
`second step, the decrement in sideWall protecting effect can
`be compensated for so that siZe varia