`Case 1:16-cv-00290-MN Document 1-18 Filed 04/22/16 Page 1 of 5 PageID #: 349
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`EXHIBIT R
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`Case 1:16-cv-00290-MN Document 1-18 Filed 04/22/16 Page 2 of 5 PageID #: 350
`EXHIBIT R - USP 7,279,727 - OmniVision Technologies, Inc. OV8858 (PureCel)
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`1. A semiconductor device, comprising:
`(A) a semiconductor substrate;
`(B) a diffusion region which is formed in the semiconductor substrate and serves as a region for the formation of a MIS transistor;
`(C) an element isolation region surrounding the diffusion region;
`at least one (D) gate conductor film which is formed across the diffusion region and the element isolation region, includes (D1) a
`gate electrode part located on the diffusion region and (D2) a gate interconnect part located on the element isolation region, and
`has (X) a constant dimension in a gate length direction;
`(E) an interlayer insulating film covering (D1) the gate electrode part; and
`(F) a gate contact which passes through the (E) interlayer insulating film, is connected to (D2) the gate interconnect part, and has
`a dimension in the gate length direction larger than (D2) the gate interconnect part.
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`SUBJECT TO CHANGE
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`1
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`Case 1:16-cv-00290-MN Document 1-18 Filed 04/22/16 Page 3 of 5 PageID #: 351
`EXHIBIT R - USP 7,279,727 - OmniVision Technologies, Inc. OV8858 (PureCel)
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`Claim 1
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`A semiconductor device, comprising: (A) a semiconductor substrate; (B) a diffusion region which is formed in the semiconductor
`substrate and serves as a region for the formation of a MIS transistor; (C) an element isolation region surrounding the diffusion
`region;
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`(Cross section : gate length direction )
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`(Plane : diffusion level)
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`(B)
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`(C)
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`(C)
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`(B)
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`(A)
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`(C)
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`SUBJECT TO CHANGE
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`2
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`Case 1:16-cv-00290-MN Document 1-18 Filed 04/22/16 Page 4 of 5 PageID #: 352
`EXHIBIT R - USP 7,279,727 - OmniVision Technologies, Inc. OV8858 (PureCel)
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`Claim 1
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`at least one (D) gate conductor film which is formed across the diffusion region and the element isolation region, includes (D1) a
`gate electrode part located on the diffusion region and (D2) a gate interconnect part located on the element isolation region, and
`has (X) a constant dimension in a gate length direction;
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`(Plane : gate level)
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`(D)
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`(D1)
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`(D2)
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`(X)
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`a gate length direction
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`(C)
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`(C)
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`(C) an element
`isolation region
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`(B) a diffusion region
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`SUBJECT TO CHANGE
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`3
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`Case 1:16-cv-00290-MN Document 1-18 Filed 04/22/16 Page 5 of 5 PageID #: 353
`EXHIBIT R - USP 7,279,727 - OmniVision Technologies, Inc. OV8858 (PureCel)
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`Claim 1
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`(E) an interlayer insulating film covering (D1) the gate electrode part; and
`(F) a gate contact which passes through the (E) interlayer insulating film, is connected to (D2) the gate interconnect part, and has
`a dimension in the gate length direction larger than (D2) the gate interconnect part.
`
`
`(Plane : gate level)
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`(Cross section : gate length direction )
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`(D) gate conductor film
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`(D1)
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`(D2)
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`(F)
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`(D1)
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`(E)
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`a gate length direction
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`(D2)
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`(F)
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`(B)
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`SUBJECT TO CHANGE
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`4
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