Case 1:16-cv-00290-MN Document 1-13 Filed 04/22/16 Page 1 of 7 PageID #: 287
`Case 1:16-cv-OO290-MN Document 1-13 Filed 04/22/16 Page 1 of 7 PageID #: 287
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`EXHIBIT M
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`Case 1:16-cv-OO290-MN Document 1-13 Filed 04/22/16 Page 1 of 7 PageID #: 287
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`EXHIBIT M
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`Case 1:16-cv-00290-MN Document 1-13 Filed 04/22/16 Page 2 of 7 PageID #: 288
`EXHIBIT M - USP 6,709,950 - OmniVision Technologies, Inc. OV8858 (PureCel)
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`12. A method of manufacturing a semiconductor device comprising:
`a first step of forming (A) a trench isolation on (B) [a] semiconductor substrate, the trench isolation having (C1) a top surface at a
`higher level than (C2) a surface of the semiconductor substrate;
`a second step of forming (D) a gate insulating film on (E) an active area surrounded by the trench is[o]lation on the semiconductor
`substrate;
`a third step of forming (F) a gate electrode on the gate insulating film;
`after the third step, a fourth step of forming (X) an insulating film on the substrate;
`a fifth step of anisotropically etching the insulating film so as to form (X1) first sidewalls on both side surfaces of the gate electrode
`and form (X2) second sidewalls on a side surface of a step portion in the boundary between the trench isolation and the active area;
`and
`after the fifth step, a sixth step of forming (G) a laminated film made of (G1) a silicon oxide film and (G2) a silicon nitride film on
`the entire top surface of the substrate;
`a seventh step of forming (H) an interlayer insulating film on the silicon nitride film;
`an eighth step of forming (I) a hole by selectively removing the interlayer insulating film and the laminated film; and
`a ninth step of forming (J) a buried conductive layer by filling the hole with a conductive material.
`
`
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`SUBJECT TO CHANGE
`
`1
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`
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`Case 1:16-cv-00290-MN Document 1-13 Filed 04/22/16 Page 3 of 7 PageID #: 289
`EXHIBIT M - USP 6,709,950 - OmniVision Technologies, Inc. OV8858 (PureCel)
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`Claim 12
`
`A method of manufacturing a semiconductor device comprising: a first step of forming (A) a trench isolation on (B) [a]
`semiconductor substrate, the trench isolation having (C1) a top surface at a higher level than (C2) a surface of the semiconductor
`substrate; a second step of forming (D) a gate insulating film on (E) an active area surrounded by the trench is[o]lation on the
`
`semiconductor substrate;
`
`(C1)
`
`(C2)
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`(C1)
`
`(Cross section: gate length direction)
`
`(A)
`
` (E)
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` (B)
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`(A)
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`(A)
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` (E)
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`(A)
`
` (B)
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` (E)
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`(A)
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`(D)
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`SUBJECT TO CHANGE
`
`2
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`Case 1:16-cv-00290-MN Document 1-13 Filed 04/22/16 Page 4 of 7 PageID #: 290
`EXHIBIT M - USP 6,709,950 - OmniVision Technologies, Inc. OV8858 (PureCel)
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`Claim 12
`
`a third step of forming (F) a gate electrode on the gate insulating film; after the third step, a fourth step of forming (X) an insulating
`film on the substrate; a fifth step of anisotropically etching the insulating film so as to form (X1) first sidewalls on both side surfaces
`of the gate electrode and form (X2) second sidewalls on a side surface of a step portion in the boundary between the trench isolation
`
`and the active area; and
`
`(X)
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`(X2)
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`(X1)
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`(F)
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`(X1)
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`(X2)
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`(A) a trench isolation
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`(E) an active area
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`(A)
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`(E)
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`(A)
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`(D) a gate insulating film
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`SUBJECT TO CHANGE
`
`3
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`
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`Case 1:16-cv-00290-MN Document 1-13 Filed 04/22/16 Page 5 of 7 PageID #: 291
`EXHIBIT M - USP 6,709,950 - OmniVision Technologies, Inc. OV8858 (PureCel)
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`Claim 12
`
`a third step of forming (F) a gate electrode on the gate insulating film; after the third step, a fourth step of forming (X) an insulating
`film on the substrate; a fifth step of anisotropically etching the insulating film so as to form (X1) first sidewalls on both side surfaces
`of the gate electrode and form (X2) second sidewalls on a side surface of a step portion in the boundary between the trench isolation
`
`and the active area; and
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`(source follower (T6)：gate length direction)
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`(source follower (T6)：gate width direction)
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`(X)
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`(X)
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`(X2)
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`(X1)
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`(F)
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`(X1)
`(X2)
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`(F)
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`(X)
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`(X1) (X2)
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`(A) a trench isolation
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`(E) an active area
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`(E)
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`(A)
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`(D)
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`(E)
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`(A)
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`(E)
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`(D) a gate insulating film
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`SUBJECT TO CHANGE
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`4
`
`
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`Case 1:16-cv-00290-MN Document 1-13 Filed 04/22/16 Page 6 of 7 PageID #: 292
`EXHIBIT M - USP 6,709,950 - OmniVision Technologies, Inc. OV8858 (PureCel)
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`Claim 12
`
`after the fifth step, a sixth step of forming (G) a laminated film made of (G1) a silicon oxide film and (G2) a silicon nitride film on
`the entire top surface of the substrate; a seventh step of forming (H) an interlayer insulating film on the silicon nitride film;
`
`
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`(F)
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`Metal 1
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`SiCNO
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`(H) : SiO
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`(G2) : CESL SiN
`(G1) : pad oxide
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`(G)
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`(A) a trench isolation
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`(A)
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`(D) a gate insulating film
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`SUBJECT TO CHANGE
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`5
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`Case 1:16-cv-00290-MN Document 1-13 Filed 04/22/16 Page 7 of 7 PageID #: 293
`EXHIBIT M - USP 6,709,950 - OmniVision Technologies, Inc. OV8858 (PureCel)
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`Claim 12
`
`an eighth step of forming (I) a hole by selectively removing the interlayer insulating film and the laminated film; and
`a ninth step of forming (J) a buried conductive layer by filling the hole with a conductive material.
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`(J)
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`(J)
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`(I)
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`(H) a interlayer insulating film
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`(G2)
`(G1)
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`(G) a laminated film
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`SUBJECT TO CHANGE
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`6
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`
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