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`EXHIBIT 1
`EXHIBIT 1
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`I 1111111111111111 11111 1111111111 11111 lllll 111111111111111 111111111111111111
`US008907499B2
`
`c12) United States Patent
`Leedy
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 8,907,499 B2
`*Dec. 9, 2014
`
`(54) THREE DIMENSIONAL STRUCTURE
`MEMORY
`
`(71) Applicant: Glenn J Leedy, Carmel, CA (US)
`
`(72)
`
`Inventor: Glenn J Leedy, Carmel, CA (US)
`
`( * ) Notice:
`
`Subject to any disclaimer, the term ofthis
`patent is extended or adjusted under 35
`U.S.C. 154(b) by O days.
`
`This patent is subject to a terminal dis(cid:173)
`claimer.
`
`(21) Appl. No.: 13/734,874
`
`(22) Filed:
`
`Jan.4,2013
`
`(2013.01); H0JL 2315226 (2013.01); H0JL
`27/10897 (2013.01); H0JL 231481 (2013.01);
`GllC 5106 (2013.01)
`USPC ............ 257/777; 257/778; 257/685; 438/977
`(58) Field of Classification Search
`USPC .............. 257/777-778, 685-686; 365/63, 51,
`365/230.06; 438/455, 977, 107, 108
`See application file for complete search history.
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`2,915,722 A
`3,202,948 A
`
`12/1959 Foster
`8/1965 Farrand
`(Continued)
`
`(65)
`
`Prior Publication Data
`
`FOREIGN PATENT DOCUMENTS
`
`US 2013/0187290Al
`
`Jul. 25, 2013
`
`Related U.S. Application Data
`
`DE
`EP
`
`3/1983
`3233195
`8/1986
`189976
`(Continued)
`
`OTHER PUBLICATIONS
`
`(60)
`
`(51)
`
`(52)
`
`Continuation of application No. 12/788,618, filed on
`May 27, 2010, which is a continuation of application
`No. 10/143,200, filed on May 13, 2002, now
`abandoned, which is a continuation of application No.
`09/607,363, filed on Jun. 30, 2000, now Pat. No.
`6,632,706, which is a continuation of application No.
`08/971,565, filed on Nov. 17, 1997, now Pat. No.
`6,133,640, which is a division of application No.
`08/835,190, filed on Apr. 4, 1997, now Pat. No.
`5,915,167.
`
`(2006.01)
`(2006.01)
`(2006.01)
`(2006.01)
`(2006.01)
`(2006.01)
`(2006.01)
`(2006.01)
`
`Int. Cl.
`H0JL23/48
`G11C5/02
`H0JL25/065
`H0JL27/06
`H0JL21/768
`H0JL23/522
`H0JL27/108
`G11C5/06
`U.S. Cl.
`CPC ........... GllC 5102 (2013.01); H0JL 2224/8083
`(2013.01); H0JL 2510657 (2013.01); H0JL
`2710688 (2013.01); H0JL 21/76898 (2013.01);
`YJ0S 438/977 (2013.01); H0JL 2924/01079
`
`Bollmann et al., Tlnee Dimensional Metallization for Vertically Inte(cid:173)
`grated Circuits, MAM'97-Materials for Advanced Metallization.
`
`(Continued)
`
`Primary Examiner - David Lam
`(74) Attorney, Agent, or Firm - Useful Arts IP
`
`ABSTRACT
`(57)
`A Three-Dimensional Structure (3DS) Memory allows for
`physical separation of the memory circuits and the control
`logic circuit onto different layers such that each layer may be
`separately optimized. One control logic circuit suffices for
`several memory circuits, reducing cost. Fabrication of 3DS
`memory involves thinning of the memory circuit to less than
`50 microns in thickness and bonding the circuit to a circuit
`stack while still in wafer substrate form. Fine-grain high
`density inter-layer vertical bus connections are used. The 3DS
`memory manufacturing method enables several performance
`and physical size efficiencies, and is implemented with estab(cid:173)
`lished semiconductor processing techniques.
`
`165 Claims, 9 Drawing Sheets
`
`

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`necessary, in order to accommodate the storage ofECC syn(cid:173)
`drome bits, additional memory array layers could be added to
`the circuit.
`Advantageous 3DS Memory Device Controller Capabilities
`As compared to a conventional memory circuit, the 3DS
`memory controller circuit can have various advantageous
`capabilities due the additional area available for controller
`circuitry and the availability of various mixed signal process
`fabrication technologies. Some of these capabilities are self-
`IO test of memory cells with dynamic gate-line address assign(cid:173)
`ment, virtual address translation, progranmiable address win(cid:173)
`dowing or mapping, ECC, data compression and multi-level
`storage.
`Dynamic gate-line address assignment is the use of pro-
`grammable gates to enable the layer and gate-line for a read/
`write operation. This allows the physical order of memory
`storage to be separate or different from the logical order of
`stored memory.
`The testing of each generation of memory devices has
`resulted in significantly increased test costs. The 3DS
`memory controller reduces the cost of testing by incorporat(cid:173)
`ing sufficient control logic to perform an internal test (self(cid:173)
`test) of the various memory array blocks. Circuit testing in the
`conventional ATE manner is required only for verification of
`controller circuit functions. The scope of the internal test is
`further extended to the programmable (dynamic) assignment
`of unique addresses corresponding to the various gate-lines of
`each memory array block on each layer. Self-test capability of
`the 3DS controller circuit can be used anytime during the life
`of the 3DS memory circuit as a diagnostic tool and as a means
`to increase circuit reliability by reconfiguring ( sparing) the
`addresses of gate-lines that fail after the 3DS memory circuit
`is in use in a product.
`ECC is a circuit capability that, if included in the controller
`circuit, can be enabled or disabled by a programming signal
`or made a dedicated function.
`Data compression logic will allow the total amount of data
`that can be stored in the 3DS memory array to be increased.
`There are various generally known data compression meth(cid:173)
`ods available for this purpose.
`Larger sense amps allow greater dynamic performance and
`enable higher speed read operations from the memory cells.
`Larger sense amps are expected to provide the capability to
`store more than one bit (multi-level storage) ofinformation in
`each memory cell; this capability has already been demon(cid:173)
`strated in non-volatile memory circuits such as flash EPRO M.
`Multi-level storage has also been proposed for use in the 4
`Gbit DRAM generation circuits.
`It will be appreciated by those of ordinary skill in the art
`that the invention can be embodied in other specific forms
`without departing from the spirit or essential character
`thereof. The presently disclosed embodiments are therefore
`considered in all respects to be illustrative and not restrictive.
`The scope of the invention is indicated by the appended
`claims rather than the foregoing description, and all changes
`which come within the meaning and range of equivalents
`thereof are intended to be embraced therein.
`
`11
`or a conventional die), or a pattern for conventional insertion
`interconnect, DCA (Direct Chip Attach) or FCA (Flip-Chip
`Attach). If another circuit layer is to be bonded to the 3DScir(cid:173)
`cuit stack, steps 1 through 4 are repeated.
`6. Perform step SA or 5B of Method A.
`3DS Memory Device Yield Enhancement Methods
`The 3DS circuit may be considered a vertically assembled
`MCM (Multi-Chip Module) and as with an MCM the final
`yield is the product of the yield probabilities of each compo(cid:173)
`nent circuit (layer) in the completed 3DS circuit. The 3DS
`circuit uses several yield enhancement methods that are syn(cid:173)
`ergistic in their combined usage within a single memory IC.
`The yield enhancement methods used in the 3DS memory
`circuit include small memory array block size, memory array
`block electrical isolation through physically unique or sepa-
`rate vertical bus interconnections, intra memory array block
`gate-line sparing, memory array layer sparing (inter-block
`gate-line sparing), controller sparing and ECC (Error Cor(cid:173)
`recting Codes). The term sparing is used to mean substitution
`by a redundant element.
`The selected size of the memory array block is the first
`component in the yield equation for the 3DS memory circuit.
`Each memory array block is individually (uniquely) accessed
`and powered by the controller circuit and is physically inde(cid:173)
`pendent of each and every other memory array block includ- 25
`ing those on the same memory array layer in addition to those
`on a different memory array layer. The size of the memory
`array block is typically less than 5 mm2 and preferably less
`than 3 mm2
`, but is not limited to a specific size. The size of
`memory array block, the simplicity of its NMOS or PMOS 30
`fabrication process and its physical independence from each
`of the other memory array blocks, fornearly all production IC
`processes, provides a conservatively stated nominal yield of
`greater than 99.5%. This yield assumes that most point
`defects in the memory array block such as open or shorted 35
`interconnect lines or failed memory cells can be spared (re(cid:173)
`placed) from the intra-block or inter-block set of redundant
`gate-lines. Major defects in a memory array block which
`render the complete memory array block unusable result in
`the complete sparing of the block from a redundant memory 40
`array layer or the rejection of the 3DS circuit.
`In the example of a 3DS DRAM circuit the yield of a stack
`of memory array blocks is calculated from the yield equation
`Ys=((l-(1-PY)2)n)b, where n is the number DRAM array
`layers, b is the number of blocks per DRAM array and Py is 45
`the effective yield (probability) of a DRAM array block less
`than 3 mm2 in area. Assuming a DRAM array block redun(cid:173)
`dancy of 4 % for gate-lines in the DRAM array block lines and
`one redundant DRAM array layer, and assuming further that
`the number of blocks per layer is 64, the number of memory 50
`array layers in the stack is 17 and the effective value for Py is
`0.995, then the stack yield Y s for the complete memory array
`(including all memory array block stacks) is 97.47%.
`The Y s memory array stack yield is then multiplied by the
`yield of the controller Y c. Assuming a die size ofless than 50 55
`mm2
`, a reasonable Ye for a controller fabricated from a 0.5
`micron BiCMOS or mixed signal process would be between
`65% and 85%, giving a net 3DS memory circuit yield of
`between 63.4% and 82.8%. If a redundant controller circuit
`layer is added to the 3DS memory stack, the yield probabili-
`ties would be between 85.7% and 95.2%.
`The effective yield of a memory array block can be further
`increased by the optional use of ECC logic. ECC logic cor(cid:173)
`rects data bit errors for some group size of data bits. The
`syndrome bits necessary for the operation of ECC logic 65
`would be stored on redundant gate-lines of any of the memory
`array layers in a vertically associated block stack. Further, if
`
`20
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`60
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`The invention claimed is:
`1. A thin and substantially flexible structure comprising:
`a thin, substantially flexible monocrystalline semiconduc-
`tor layer of one piece; and
`a silicon-based dielectric layer formed on the thin semi(cid:173)
`conductor layer and having a stress of less than 5xl 0 8
`dynes/cm2 tensile.
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`2. The thin and substantially flexible structure of claim 1,
`further comprising:
`a vertical interconnect conductor extending vertically
`through the thin semiconductor layer; and
`a vertical silicon-based dielectric insulator extending ver(cid:173)
`tically through the thin semiconductor layer and around
`the interconnect conductor and having a stress of less
`than 5xl08 dynes/cm2 tensile.
`3. The thin and substantially flexible structure of claim 2,
`wherein:
`the thin semiconductor layer comprises vertical holes
`etched therethrough; and
`the vertical interconnect conductor and the vertical silicon(cid:173)
`based dielectric insulator are formed in one of the verti-
`cal holes of the thin semiconductor layer.
`4. The thin and substantially flexible structure of claim 2,
`wherein the thin semiconductor layer is formed from a semi(cid:173)
`conductor wafer.
`5. The thin and substantially flexible structure of claim 2, 20
`wherein the thin semiconductor layer has a thickness of 50
`microns or less.
`6. The thin and substantially flexible structure of claim 4,
`wherein the semiconductor wafer comprises monocrystalline
`silicon, and the thin semiconductor layer comprises monoc(cid:173)
`rystalline silicon formed from the semiconductor wafer.
`7. The thin and substantially flexible structure of claim 2,
`wherein the thin semiconductor layer is unitary.
`8. The thin and substantially flexible structure of claim 2,
`wherein the thin semiconductor layer extends from edge to 30
`edge of the dielectric layer.
`9. The thin and substantially flexible structure of claim 8,
`wherein the dielectric layer extends from edge to edge of the
`thin semiconductor layer.
`10. The thin and substantially flexible structure of claim 1, 35
`wherein the thin semiconductor layer comprises a polished
`surface formed by removing semiconductor material during
`thinning of the thin semiconductor layer to expose a surface
`thereof and then polishing the exposed surface, wherein the
`thin semiconductor layer is substantially flexible based on 40
`being thinned and having the polished surface.
`11. The thin and substantially flexible structure of claim 2,
`further comprising:
`a bottomside surface and a topside surface;
`a contact formed on the bottomside surface and electrically 45
`connected to the vertical interconnect conductor; and
`an interconnect, contact or circuit formed on or near the
`topside surface and electrically connected to the vertical
`interconnect conductor;
`wherein the interconnect, contact or circuit is electrically 50
`connected to the contact on the bottomside surface via
`the vertical interconnect.
`12. A thin and substantially flexible circuit comprising:
`a thin monocrystalline semiconductor layer of one piece;
`a silicon-based dielectric layer formed on the thin semi- 55
`conductor layer and having a stress of less than 5xl 0 8
`dynes/cm2 tensile; and
`circuitry supported by the thin semiconductor layer and the
`dielectric layer defining an integrated circuit die having
`an area, wherein the thin semiconductor layer extends 60
`throughout a substantial portion of the area of the inte(cid:173)
`grated circuit die.
`13. The thin and substantially flexible circuit of claim 12,
`comprising:
`a vertical interconnect conductor extending vertically 65
`through the thin semiconductor layer and coupled to said
`circuitry; and
`
`14
`a vertical silicon-based dielectric insulator extending ver(cid:173)
`tically through the thin semiconductor layer and around
`the interconnect conductor and having a stress of less
`than 5xl 08 dynes/cm2 tensile.
`14. The thin and substantially flexible circuit of claim 13,
`wherein the thin semiconductor layer is formed from a semi(cid:173)
`conductor wafer.
`15. The thin and substantially flexible circuit of claim 13,
`wherein the thin semiconductor layer has a thickness of 50
`microns or less.
`16. The thin and substantially flexible circuit of claim 14,
`wherein the semiconductor wafer comprises monocrystalline
`silicon, and the thin semiconductor layer comprises monoc-
`rystalline silicon formed from the semiconductor wafer.
`17. The thin and substantially flexible circuit of claim 13,
`wherein the thin semiconductor layer is unitary.
`18. The thin and substantially flexible circuit of claim 13,
`wherein the thin semiconductor layer extends from edge to
`edge of the dielectric layer.
`19. The thin and substantially flexible circuit of claim 18,
`wherein the dielectric layer extends from edge to edge of the
`thin semiconductor layer.
`20. The thin and substantially flexible circuit of claim 12,
`wherein the thin semiconductor layer comprises a polished
`25 surface formed by removing semiconductor material during
`thinning of the thin semiconductor layer to expose a surface
`thereof and then polishing the exposed surface, wherein the
`thin semiconductor layer is substantially flexible based on
`being thinned and having the polished surface.
`21. The thin and substantially flexible circuit of claim 13,
`further comprising:
`a bottomside surface and a topside surface;
`a contact formed on the bottomside surface and electrically
`connected to the vertical interconnect conductor; and
`an interconnect, contact or circuit formed on or near the
`topside surface and electrically connected to the vertical
`interconnect conductor;
`wherein the interconnect, contact or circuit is electrically
`connected to the contact on the bottomside surface via
`the vertical interconnect.
`22. A structure comprising:
`a monocrystalline semiconductor layer of one piece; and
`a silicon-based dielectric layer formed on the semiconduc-
`tor layer and having a stress of less than 5xl 0 8 dynes/
`cm2 tensile;
`wherein the semiconductor layer is capable of being
`thinned to obtain a thin and substantially flexible sub(cid:173)
`strate.
`23. The structure of claim 22, comprising:
`a vertical interconnect conductor extending vertically
`through the thin semiconductor layer and coupled to said
`circuitry; and
`a vertical silicon-based dielectric insulator extending ver(cid:173)
`tically through the thin semiconductor layer and around
`the interconnect conductor and having a stress of less
`than 5xl 08 dynes/cm2 tensile.
`24. A thin and substantially flexible integrated circuit com(cid:173)
`prising:
`a thin, substantially flexible monocrystalline semiconduc(cid:173)
`tor layer of one piece comprising integrated circuit
`devices; and
`a silicon-based dielectric layer formed on the thin semi(cid:173)
`conductor layer and having a stress of less than 5xl 0 8
`dynes/cm2 tensile.
`25. The structure of claim 23, wherein:
`the thin semiconductor layer comprises vertical holes
`etched therethrough; and
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`Case 1:14-cv-01430-CJB Document 521-1 Filed 06/06/22 Page 30 of 46 PageID #: 28731
`Case 1:14-cv-01430-CJB Document 521-1 Filed 06/06/22 Page 30 of 46 PagelD #: 28731
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`Case 1:14-cv-01430-CJB Document 521-1 Filed 06/06/22 Page 31 of 46 PageID #: 28732
`Case 1:14-cv-01430-CJB Document 521-1 Filed 06/06/22 Page 31 of 46 PagelD #: 28732
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`EXHIBIT 15
`EXHIBIT 15
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`Case 1:14-cv-01430-CJB Document 521-1 Filed 06/06/22 Page 32 of 46 PageID #: 28733
`Case 1:14-cv-01430-CJB Document 521-1 Filed 06/06/22 Page 32 of 46 PagelD #: 28733
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`Case 1:14-cv-01430-CJB Document 521-1 Filed 06/06/22 Page 33 of 46 PageID #: 28734
`Case 1:14-cv-01430-CJB Document 521-1 Filed 06/06/22 Page 33 of 46 PagelD #: 28734
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`EXHIBIT 16
`EXHIBIT 16
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`Case 1:14-cv-01430-CJB Document 521-1 Filed 06/06/22 Page 34 of 46 PageID #: 28735
`Case 1:14-cv-01430-CJB Document 521-1 Filed 06/06/22 Page 34 of 46 PagelD #: 28735
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`Case 1:14-cv-01430-CJB Document 521-1 Filed 06/06/22 Page 35 of 46 PageID #: 28736
`Case 1:14-cv-01430-CJB Document 521-1 Filed 06/06/22 Page 35 of 46 PagelD #: 28736
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`EXHIBIT 17
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`Case 1:14-cv-01430-CJB Document 521-1 Filed 06/06/22 Page 36 of 46 PageID #: 28737
`Case 1:14-cv-01430-CJB Document 521-1 Filed 06/06/22 Page 36 of 46 PagelD #: 28737
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`Case 1:14-cv-01430-CJB Document 521-1 Filed 06/06/22 Page 37 of 46 PageID #: 28738
`Case 1:14-cv-01430-CJB Document 521-1 Filed 06/06/22 Page 37 of 46 PagelD #: 28738
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`EXHIBIT 18
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`Case 1:14-cv-01430-CJB Document 521-1 Filed 06/06/22 Page 38 of 46 PageID #: 28739
`Case 1:14-cv-01430-CJB Document 521-1 Filed 06/06/22 Page 38 of 46 PagelD #: 28739
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`Case 1:14-cv-01430-CJB Document 521-1 Filed 06/06/22 Page 39 of 46 PageID #: 28740
`Case 1:14-cv-01430-CJB Document 521-1 Filed 06/06/22 Page 39 of 46 PagelD #: 28740
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`EXHIBIT 19
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`Case 1:14-cv-01430-CJB Document 521-1 Filed 06/06/22 Page 40 of 46 PageID #: 28741
`Case 1:14-cv-01430-CJB Document 521-1 Filed 06/06/22 Page 40 of 46 PagelD #: 28741
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`Case 1:14-cv-01430-CJB Document 521-1 Filed 06/06/22 Page 41 of 46 PageID #: 28742
`Case 1:14-cv-01430-CJB Document 521-1 Filed 06/06/22 Page 41 of 46 PagelD #: 28742
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`EXHIBIT 20
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`Case 1:14-cv-01430-CJB Document 521-1 Filed 06/06/22 Page 42 of 46 PageID #: 28743
`Case 1:14-cv-01430-CJB Document 521-1 Filed 06/06/22 Page 42 of 46 PagelD #: 28743
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`Case 1:14-cv-01430-CJB Document 521-1 Filed 06/06/22 Page 43 of 46 PageID #: 28744
`Case 1:14-cv-01430-CJB Document 521-1 Filed 06/06/22 Page 43 of 46 PagelD #: 28744
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`EXHIBIT 21
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`Case 1:14-cv-01430-CJB Document 521-1 Filed 06/06/22 Page 44 of 46 PageID #: 28745
`Case 1:14-cv-01430-CJB Document 521-1 Filed 06/06/22 Page 44 of 46 PagelD #: 28745
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`Case 1:14-cv-01430-CJB Document 521-1 Filed 06/06/22 Page 45 of 46 PageID #: 28746
`Case 1:14-cv-01430-CJB Document 521-1 Filed 06/06/22 Page 45 of 46 PagelD #: 28746
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`EXHIBIT 22
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`Case 1:14-cv-01430-CJB Document 521-1 Filed 06/06/22 Page 46 of 46 PageID #: 28747
`Case 1:14-cv-01430-CJB Document 521-1 Filed 06/06/22 Page 46 of 46 PagelD #: 28747
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