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`Three dimensional structure integrated circuit
`US 7193239 B2
`ABSTRACT
`
`A Three-Dimensional Structure (3DS) Memory allows for physical separation of
`the memory circuits and the control logic circuit onto different layers such that
`each layer may be separately optimized. One control logic circuit suffices for
`several memory circuits, reducing cost. Fabrication of 3DS memory involves
`thinning of the memory circuit to less than 50 μm in thickness and bonding the
`circuit to a circuit stack while still in wafer substrate form. Fine-grain high density
`inter-layer vertical bus connections are used. The 3DS memory manufacturing
`method enables several performance and physical size efficiencies, and is
`implemented with established semiconductor processing techniques.
`
`Publication number
`US7193239 B2
`Publication type
`Grant
`Application number
`US 10/614,067
`Publication date
`Mar 20, 2007
`Filing date
`Jul 3, 2003
`Priority date
`Apr 4, 1997
`Fee status
`Paid
`Also published as
`CN1155050C, 22 More »
`Glenn J Leedy
`Inventors
`Original Assignee
`Elm Technology Corporation
`Export Citation
`BiBTeX, EndNote, RefMan
`Patent Citations (104), Non-Patent Citations (47), Referenced by (45),
`Classifications (53), Legal Events (5)
`External Links: USPTO, USPTO Assignment, Espacenet
`
`IMAGES (10)
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`DESCRIPTION
`
`CROSS REFERENCE TO RELATED APPLICATIONS
`This application is a division of, commonly assigned U.S. patent application Ser.
`No. 09/607,363, filed Jun. 30, 2000 now U.S. Pat. No. 6,632,706, which is a
`continuation of U.S. patent application Ser. No. 08/971,565, filed Nov. 17, 1997,
`now U.S. Pat. No. 6,133,640, which is a division of U.S. patent application Ser.
`No. 08/835,190, filed Apr. 4, 1997, now U.S. Pat. No. 5,915,167, all of which are
`incorporated by reference herein in their entireties.
`BACKGROUND OF THE INVENTION
`1. Field of the Invention
`The present invention relate s to stacked integrated circuit memory.
`2. State of the Art
`Manufacturing methods for increasing the performance and decreasing the cost
`of electronic circuits, nearly without exception, are methods that increase the
`integration of the circuit and decrease its physical size per equivalent number of
`circuit devices such as transistors or capacitors. These methods have produced
`as of 1996 microprocessors capable of over 100 million operations per second
`that cost less than $1,000 and 64 Mbit DRAM circuits that access data in less
`than 50 ns and cost less than $50. The physical size of such circuits is less than
`2 cm2. Such manufacturing methods support to a large degree the economic
`standard of living in the major industrialized countries and will most certainly
`continue to have significant consequences in the daily lives of people all over the
`world.
`
`CLAIMS (79)
`1. Circuitry comprising:
`a plurality of monolithic substrates having integrated circuits formed thereon
`and stacked in layers such that each layer comprises only one of the
`substrates, wherein at least one of the plurality of substrates is a
`substantially flexible substrate, and wherein a major portion of the monolithic
`substrate is removed; and
`between adjacent substrates, a bonding layer bonding together the adjacent
`substrates, the bonding layer being formed by bonding first and second
`substantially planar surfaces having a bond-forming material throughout a
`majority of the surface area thereof.
`2. The apparatus of claim 1, further comprising vertical interconnects
`having vertical interconnect segments formed of a first metal contact on
`a first substrate bonded to a second aligned metal contact on a second
`adjacent substrate.
`3. The apparatus of claim 2, wherein the plurality of aligned vertical
`interconnect segments are joined to form a vertical interconnect
`between non-adjacent substrates.
`4. The apparatus of claim 1, wherein at least one of said substrates is a
`substantially rigid substrate having a first thickness.
`5. The apparatus of claim 4, wherein a plurality of substrates have a
`reduced second thickness substantially less than said first thickness.
`6. The apparatus of claim 5, wherein a ratio of said first thickness to
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`said second thickness is approximately 10:1.
`Circuit manufacturing methods take two primary forms: process integration and
`assembly integration. Historically the line between these two manufacturing
`7. The apparatus of claim 5, wherein a ratio of said first thickness to
`disciplines has been clear, but recently with the rise in the use of MCMs (Multi-
`said second thickness is at least 10:1.
`Chip Modules) and flip-chip die attach, this clear separation may soon disappear.
`(The predominate use of the term Integrated Circuit (IC) herein is in reference to
`8. The apparatus of claim 1, further comprising vertical interconnects
`an Integrated Circuit in singulated die form as sawed from a circuit substrate
`formed between the adjacent bonded substrates to interconnect the
`such as s semiconductor wafer versus, for example, an Integrated Circuit in
`integrated circuits in subsequent processing steps.
`packaged form.) The majority of ICs when in initial die form are presently
`9. The apparatus of claim 1, further comprising vertical interconnects
`individually packaged, however, there is an increasing use of MCMs. Die in an
`formed between the adjacent bonded substrates to interconnect the
`MCM are normally attached to a circuit substrate in a planar fashion with
`integrated circuits in subsequent processing steps.
`conventional IC die I/O interconnect bonding methods such as wire bonding,
`DCA (Direct Chip Attach) or FCA (Flip-Chip Attach).
`10. The apparatus of claim 1, wherein the circuitry is formed with a low
`stress dielectric.
`Integrated circuit memory such as DRAM, SRAM, flash EPROM, EEPROM,
`Ferroelectric, GMR (Giant MagnetoResistance), etc. have the common
`11. The apparatus of claim 10, wherein the low stress dielectric is at
`architectural or structural characteristic of being monolithic with the control
`least one of a silicon dioxide dielectric, an oxide of silicon dielectric, and
`circuitry integrated on the same die with the memory array circuitry. This
`
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`caused to have stress of about 5×108 dynes/cm2 or less.
`established (standard or conventional) architecture or circuit layout structure
`creates a design trade-off constraint between control circuitry and memory array
`12. The apparatus of claim 11, wherein the stress of the low stress
`circuitry for large memory circuits. Reductions in the fabrication geometries of
`dielectric is tensile.
`memory cell circuitry has resulted in denser and denser memory ICs, however,
`these higher memory densities have resulted in more sophisticated control
`13. An integrated circuit structure comprising:
`circuitry at the expense of increased area of the IC. Increased IC area means at
`a first substrate having a first surface; and
`least higher fabrication costs per IC (fewer ICs per wafer) and lower IC yields
`(fewer working ICs per wafer), and in the worst case, an IC design that cannot
`a second substrate bonded to the first surface of the first substrate to form
`be manufactured due to its non-competitive cost or unreliable operation.
`conductive paths between the first substrate and the second substrate
`wherein the second substrate is a substantially flexible monolithic
`As memory density increases and the individual memory cell size decreases
`monocrystalline semiconductor substrate having active circuitry formed
`more control circuitry is required. The control circuitry of a memory IC as a
`thereon, wherein no other substrates are bonded to the first surface, and
`percentage of IC area in some cases such as DRAMs approaches or exceeds
`wherein a major portion of the second substantially flexible monolithic
`40%. One portion of the control circuitry is the sense amp which senses the
`monocrystalline semiconductor substrate is removed.
`state, potential or charge of a memory cell in the memory array circuitry during a
`read operation. The sense amp circuitry is a significant portion of the control
`14. The apparatus of claim 13, wherein the first substrate having
`circuitry and it is a constant challenge to the IC memory designer to improve
`polycrystalline active circuitry formed thereon.
`sense amp sensitivity in order to sense ever smaller memory cells while
`15. The apparatus of claim 13, wherein the first substrate having active
`preventing the area used by the sense amp from becoming too large.
`circuitry formed thereon.
`If this design constraint or trade-off between control and memory circuits did not
`16. The apparatus of claim 13, wherein at least one of the first and
`exist, the control circuitry could be made to perform numerous additional
`second substrates having passive circuitry formed thereon.
`functions, such as sensing multiple storage states per memory cell, faster
`memory access through larger more sensitive sense amps, caching, refresh,
`17. The apparatus of claim 13, wherein at least one of the first substrate
`address translation, etc. But this trade-off is the physical and economic reality for
`and the second substrate is a thinned substantially flexible substrate.
`memory ICs as they are presently made by all manufacturers.
`18. The apparatus of claim 13, further comprising a low stress dielectric
`The capacity of DRAM circuits increase by a factor of four from one generation
`layer overlying at least one of the first substrate and the second
`to the next; e.g. 1 Mbit, 4 Mbit, 16 Mbit and 64 Mbit DRAMs. This four times
`substrate.
`increase in circuit memory capacity per generation has resulted in larger and
`larger DRAM circuit areas. Upon introduction of a new DRAM generation the
`19. The apparatus of claim 18, wherein the low stress dielectric layer is
`circuit yields are too low and, therefore, not cost effective for high volume
`at least one of a silicon dioxide dielectric, an oxide of silicon dielectric,
`manufacture. It is normally several years between the date prototype samples of
`
`
`and caused to have a stress of about 5×108 dynes cm2 or less.
`a new DRAM generation are shown and the date such circuits are in volume
`20. The apparatus of claim 19, wherein the stress of the low stress
`production.
`dielectric is tensile.
`Assembling die in a stacked or three dimensional (3D) manner is disclosed in
`U.S. Pat. No. 5,354,695 of the present inventor, incorporated herein by
`21. The apparatus of claim 13, wherein at least one substrate of the first
`reference. Furthermore, assembling die in a 3D manner has been attempted with
`and second substrates has memory circuitry formed thereon and at
`regard to memory. Texas Instruments of Dallas Tex., Irvine Sensors of Costa
`least one of the first and second substrates has logic circuitry formed
`Mesa Calif. and Cubic Memory Corporation of Scotts Valley Calif., have all
`thereon, wherein the at least one substrate that has logic circuitry
`attempted to produce stacked or 3D DRAM products. In all three cases,
`formed thereon performs programmable gate line address assignment
`conventional DRAM circuits in die form were stacked and the interconnect
`with respect to the at least one substrate that has memory circuitry
`between each DRAM in the stack was formed along the outside surface of the
`formed thereon.
`circuit stack. These products have been available for the past several years and
`22. The apparatus of claim 13, wherein information processing is
`have proved to be too expensive for commercial applications, but have found
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`performed on data routed between the first and second substrates.
`some use in space and military applications due to their small physical size or
`footprint.
`23. The apparatus of claim 13, wherein at least one substrate of the first
`The DRAM circuit type is referred to and often used as an example in this
`and second substrates has logic circuitry formed thereon for performing
`specification, however, this invention is clearly not limited to the DRAM type of
`at least one function from the group consisting of: virtual memory
`circuit Undoubtedly memory cell types such as EEPROMs (Electrically Erasable
`management, ECC, indirect addressing, content addressing, data
`Programmable Read Only Memories), flash EPROM, Ferroelectric, or
`compression, data decompression, graphics acceleration, audio
`combinations (intra or inter) of such memory cells can also be used with the
`encoding, audio decoding, video encoding, video decoding, voice
`present Three Dimensional Structure (3DS) methods to form 3DS memory
`recognition, handwriting recognition, power management and database
`devices.
`processing.
`The present invention furthers, among others, the following objectives:
`24. A stacked integrated circuit comprising:
`1. Several-fold lower fabrication cost per megabyte of memory than circuits
`a plurality of integrated circuit substrates having formed on corresponding
`conventionally made solely with monolithic circuit integration methods.
`surfaces thereof complementary patterns of a material bondable using
`thermal diffusion bonding, wherein at least one of the plurality of substrates
`2. Several-fold higher performance than conventionally made memory circuits.
`is a substantially flexible monolithic integrated circuit substrate, and wherein
`a major portion of the at least one substantially flexible monolithic integrated
`3. Many-fold higher memory density per IC than conventionally made memory
`circuit substrate is removed; and
`circuits.
`a thermal diffusion bonded region between the complementary patterns.
`4. Greater designer control of circuit area size, and therefore, cost.
`25. The apparatus of claim 24, wherein at least one integrated circuit
`5. Circuit dynamic and static self-test of memory cells by an internal controller.
`substrate of the plurality of integrated circuit substrates has memory
`6. Dynamic error recovery and reconfiguration.
`circuitry formed thereon, the memory circuitry having a plurality of
`memory locations including at least one memory location used for
`7. Multi-level storage per memory cell.
`sparing, wherein data from the at least one memory location on the at
`least one integrated circuit substrate that has memory circuitry formed
`8. Virtual address translation, address windowing, various address functions
`thereon is used instead of data from a defective memory location on the
`such as indirect addressing or content addressing, analog circuit functions and
`at least one integrated circuit substrate that has memory circuitry
`various graphics acceleration and microprocessor functions.
`formed thereon.
`SUMMARY OF THE INVENTION
`26. The apparatus of claim 24, wherein at least one integrated circuit
`The present 3DS memory technology is a stacked or 3D circuit assembly
`substrate of the plurality of integrated circuit substrates has memory
`technology. Features include:
`circuitry formed thereon and at least one integrated circuit substrate of
`the plurality of integrated circuit substrates has logic circuitry formed
`1. Physical separation of the memory circuits and the control logic circuit onto
`thereon, wherein the at least one integrated circuit substrate that has
`different layers;
`logic circuitry formed thereon performs programmable gate line address
`assignment with respect to the at least one integrated circuit substrate
`2. The use of one control logic circuit for several memory circuits;
`that has memory circuitry formed thereon.
`3. Thinning of the memory circuit to less than about 50 μm in thickness forming a
`27. The apparatus of claim 24, wherein information processing is
`substantially flexible substrate with planar processed bond surfaces and bonding
`performed on data routed between circuitry of at least two of the
`the circuit to the circuit stack while still in wafer substrate form; and
`plurality of integrated circuit substrates.
`4. The use of fine-grain high density inter layer vertical bus connections.
`28. The apparatus of claim 24, wherein at least one integrated circuit
`The 3DS memory manufacturing method enables several performance and
`substrate of the plurality of integrated circuit substrates has
`physical size efficiencies, and is implemented with established semiconductor
`reconfiguration circuitry.
`processing techniques. Using the DRAM circuit as an example, a 64 Mbit DRAM
`29. The apparatus of claim 24, wherein at least one integrated circuit
`made with a 0.25 μm process could have a die size of 84 mm2, a memory area
`substrate of the plurality of integrated circuit substrates has logic
`to die size ratio of 40% and a access time of about 50 ns for 8 Mbytes of
`circuitry formed thereon for performing at least one function from the
`storage; a 3DS DRAM IC made with the same 0.25 μm process would have a
`group consisting of: virtual memory management, ECC, indirect
`die size of 18.6 mm2, use 17 DRAM array circuit layers, a memory area to die
`addressing, content addressing, data compression, data
`size ratio of 94.4% and an expected access time of less than 10 ns for 64
`decompression, graphics acceleration, audio encoding, audio decoding,
`Mbytes of storage. The 3DS DRAM IC manufacturing method represents a
`video encoding, video decoding, voice recognition, handwriting
`scalable, many-fold reduction in the cost per megabyte versus that of
`recognition, power management and database processing.
`conventional DRAM IC manufacturing methods. In other words, the 3DS
`memory manufacturing method represents, at the infrastructure level, a
`30. The apparatus of claim 24, further comprising:
`fundamental cost savings that is independent of the process fabrication
`a memory array having a plurality of memory storage cells, a
`technology used.
`plurality of data lines, and a plurality of gate lines, each memory
`BRIEF DESCRIPTION OF THE DRAWING
`storage cell stores a data value and has circuitry for coupling that
`data value to one of the plurality of data lines in response to
`The present invention may be further understood from the following description in
`receiving a gate control signal from one of the plurality of gate
`conjunction with the appended drawing. In the drawing:
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`FIG. 1 a is a pictorial view of a 3DS DRAM IC manufactured with Method A or
`lines;
`Method B and demonstrating the same physical appearance of I/O bond pads as
`circuitry that generates the gate control signal in response to
`a conventional IC die;
`receiving an address, including means for mapping addresses to
`FIG. 1 b is a cross-sectional view of a 3DS memory IC showing the metal
`gate lines; and
`bonding interconnect between several thinned circuit layers;
`a controller that determines if one of the plurality of memory cells is
`FIG. 1 c is a pictorial view of a 3DS DRAM IC stack bonded and interconnected
`defective and alters the mapping to eliminate references to the one
`face-down onto a larger conventional IC or another 3DS IC;
`of the plurality of memory cells that is defective.
`FIG. 2 a is a diagram showing the physical layout of a 3DS DRAM array circuit
`31. The apparatus of claim 24, further comprising:
`block with one data-line set of bus lines, i.e one port;
`at least one controller substrate having logic circuitry formed
`FIG. 2 b is a diagram showing the physical layout of a 3DS DRAM array circuit
`thereon;
`block with two sets of data-line bus lines, i.e. two ports;
`at least one memory substrate having memory circuitry formed
`FIG. 2 c is a diagram showing the physical layout of a portion of an exemplary
`thereon;
`memory controller circuit;
`a plurality of data lines and a plurality of gate lines on each memory
`FIG. 3 is a diagram showing the physical layout of a 3DS DRAM array circuit
`substrate;
`showing partitions for sixty-four (64) 3DS DRAM array blocks;
`an array of memory cells on each memory substrate, each memory
`FIG. 4 is a cross-sectional view of a generic 3DS vertical interconnection or
`cell stores a data value and has circuitry that couples the data
`feed-through in a thinned substrate;
`value to one of the plurality of data lines in response to selecting of
`one of the plurality of gate lines;
`FIG. 5 is a diagram showing the layout of a 3DS memory multiplexer for down-
`selecting gate-line read or write selection.
`a gate line selection circuit that enables a gate line for a memory
`operation, wherein the gate line selection circuit has programmable
`DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
`gates to receive address assignments for at least one of the
`plurality of gate lines and wherein the address assignments for
`Referring to FIG. 1 a and FIG. 1 b, the 3DS (Three Dimensional Structure)
`determining which of the plurality of gate lines is selected for each
`memory device 100 is a stack of integrated circuit layers with fine-grain vertical
`programmed address assignment; and
`interconnect between all circuit layers. The term fine-grain inter-layer vertical
`interconnect is used to mean electrical conductors that pass through a circuit
`controller substrate logic that determines if one memory cell of the
`layer with or without an intervening device element and have a pitch of nominally
`array of memory cells is defective and alters the address
`less than 100 μm and more typically less than 10 μm, but not limited to a pitch of
`assignments of the plurality of gate lines to remove references to
`less than 2 μm, as best seen in FIG. 2 a and FIG. 2 b. The fine-grain inter-layer
`the gate line that causes the defective memory cell to couple a
`vertical interconnect also functions to bond together the various circuit layers. As
`data value to one of the plurality of data lines.
`shown in FIG. 1 b, although the bond and interconnect layers 105 a, 105 b, etc.,
`are preferably metal, other material may also be used as described more fully
`32. The apparatus of claim 31, wherein said controller substrate logic:
`hereinafter.
`tests the array of memory cells periodically to determine if one of
`The pattern 107 a, 107 b, etc. in the bond and interconnect layers 105 a, 105 b,
`said memory cells is defective; and
`etc. defines the vertical interconnect contacts between the integrated circuit
`removes references in the address assignments to gate lines that
`layers and serves to electrically isolate these contacts from each other and the
`cause detected defective memory cells to couple data values to
`remaining bond material; this pattern takes the form of either voids or dielectric
`the plurality of data lines.
`filled spaces in the bond layers.
`33. The apparatus of claim 31, further comprising programmable logic to
`The 3DS memory stack is typically organized as a controller circuit 101 and
`prevent the use of data values from the plurality of data lines when gate
`some number of memory array circuit layers 103, typically between nine (9) and
`lines cause detected defective memory cells to couple data values to
`thirty-two (32), but there is no particular limit to the number of layers. The
`the plurality of data lines.
`controller circuit is of nominal circuit thickness (typically 0.5 mm or greater), but
`each memory array circuit layer is a thinned and substantially flexible circuit with
`34. The apparatus of claim 31, wherein the array of memory cells are
`net low stress, less than 50 μm and typically less than 10 μm in thickness.
`arranged within physical space in a physical order and are arranged
`Conventional I/O bond pads are formed on a final memory array circuit layer for
`within an address space in a logical order, wherein the physical order of
`use with conventional packaging methods. Other metal patterns may be used
`at least one memory cell is different than the logical order of the at least
`such as insertion interconnection (disclosed in U.S. Pat. Nos. 5,323,035 and
`one memory cell.
`5,453,404 of the present inventor), DCA (Direct Chip Attach) or FCA (Flip-Chip
`35. The apparatus of claim 31, wherein:
`Attach) methods.
`the logic circuitry of the at least one controller substrate is tested
`Further, the fine grain inter-layer vertical interconnect can be used for direct
`by an external means; and
`singulated die bonding between a 3DS memory die and a conventional die
`(wherein the conventional die could be the controller circuit as shown in FIG. 1 c)
`the array of memory cells of the at least one memory substrate are
`or a 3DS memory die and another 3DS memory die; it should be assumed that
`tested by the logic circuitry of the at least one controller substrate,
`the areas (sizes) of the respective dice to be bonded together can vary and need
`wherein the testing achieves a functional testing of a substantial
`not be the same. Referring more particularly to FIG. 1 c, a 3DS DRAM IC stack
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`100 is bonded and interconnected face-down onto a larger conventional IC or
`portion of the array of memory cells.
`another 3DS IC 107. Optionally the 3DS stack 100 can be composed of only
`36. The apparatus of claim 31, wherein the logic circuitry of the at least
`DRAM array circuits with the DRAM controller circuitry as part of the larger die.
`one controller substrate performs functional testing of a substantial
`If the DRAM controller circuitry is part of the larger die, then fine-grain vertical
`portion of the array of memory cells.
`bus interconnect would be required (at the face 109 of the 3DS DRAM IC stack
`100) to connect the 3DS DRAM array circuit to the DRAM controller, otherwise
`37. The apparatus of claim 31, wherein the controller substrate logic is
`larger grain conventional interconnection could be incorporated (patterned) into
`further configured to:
`the planarized bond layer.
`prevent the use of at least one defective gate line; and
`As shown in FIG. 3, each memory array circuit layer includes a memory array
`replace references to memory cells addressed using the defective
`
`circuit 300 composed of memory array blocks 301 (nominally less than 5 mm2 in
`gate line with references to spare memory cells addressed using a
`area) and each block is composed of memory cells (in much the same manner
`spare gate line.
`as the cell array of a DRAM or EEPROM circuit), busing electrodes, and—at the
`option of the designer—enabling gates for selection of specific rows or columns
`38. The apparatus of claim 31, wherein the controller substrate logic is
`of the memory array. The controller circuit is composed of sense amps, address,
`further configured to prevent the use of at least one defective gate line.
`control and drive logic that would normally be found at the periphery of a typical
`memory circuit of monolithic design such as in a conventional DRAM.
`39. The apparatus of claim 31, wherein the logic circuitry of the at least
`one controller substrate performs all functional testing of the array of
`Fine-grain busing vertically connects the controller independently to each
`memory cells of the at least one memory substrate.
`memory array layer such that the controller can provide drive (power) or enable
`40. The apparatus of claim 24, wherein at least one of the plurality of
`signals to any one layer without affecting the state of any of the other layers.
`integrated circuit substrates is a thinned substantially flexible substrate.
`This allows the controller to test, read or write independently each of the memory
`circuit layers.
`41. The apparatus of claim 24, wherein at least one of the plurality of
`FIG. 2 a and FIG. 2 b show examples of layouts of possible blocks of a memory
`integrated circuit substrates is formed with a low stress dielectric.
`array such as the block 301 of FIG. 3. Although only a portion of the block is
`42. The apparatus of claim 41, wherein the low stress dielectric is at
`shown, in the illustrated embodiment, the blocks exhibit bilateral symmetry such
`least one of a silicon dioxide dielectric, an oxide of silicon dielectric, and
`that the layout of the complete block may be ascertained from the illustrated
`
`
`caused to have a stress of about 5×108 dynes/cm2 or less.
`portion. Abbreviations “T”, “L”, and “TL” are used following various reference
`numerals to indicate “Top”, “Left” and Top-Left,” respectively, implying
`43. The apparatus of claim 42, wherein the stress of the low stress
`corresponding elements not shown in the figure.
`dielectric is tensile.
`Referring to FIG. 2 a, a core portion 200 of the block is composed of a “sea” of
`44. An integrated circuit structure comprising:
`memory cells. Logically, the aggregation of memory cells may be subdivided into
`“macrocells” 201 each containing some number of memory cells, e.g. an 8×8
`a first substrate having a first surface; and
`array of 64 memory cells. At the periphery of the core is formed fine-grain vertical
`a second substrate bonded to the first surface of the first substrate to form
`interconnect comprising inter-layer bond and bus contact metallizations 400,
`conductive paths between the first substrate and the second substrate
`described in greater detail hereinafter with reference to FIG. 4. The fine-grain
`wherein the second substrate is a substantially flexible monolithic
`vertical interconnect includes I/O power and ground bus lines 203TL, memory
`monocrystalline semiconductor substrate having active circuitry formed
`circuit layer selects 205T, memory macro cell column selects 207T, data lines
`thereon, wherein no other substrates are bonded to the first surface, wherein
`209L, and gate-line multiplexer (“mux”) selects 209TL. Gate-line multiplexers
`at least one substrate of the first and second substrates has memory
`211T are, in the illustrated embodiment, 4:1 multiplexers used to select one of
`circuitry formed thereon, the memory circuitry having a plurality of memory
`four columns within an eight-wide memory macro cell column. Corresponding
`locations including at least one memory location used for sparing, wherein
`bottom-side 4:1 multiplexers combine with the topside multiplexers 211T to form
`data from the at least one memory location on the at least one substrate that
`equivalent 8:1 multiplexers for selecting a single gate-line from an eight-gate-line-
`has memory circuitry formed thereon is used instead of data from a
`wide memory macro cell column.
`defective memory location on the at least one substrate that has memory
`One implementation of a 4:1 gate-line bus muliplexer 500 is shown in FIG. 5.
`circuitry formed thereon.
`Gate-line enables 209TL′ (formed in a Metal-1 layer, for example) control
`45. The apparatus of claim 44, further comprising at least one dielectric
`transistors 501 a through 501 d, respectively. Coupled to the transistors are
`layer wherein the dielectric layer comprises at least one of a silicon
`respective gate lines 503 a through 503 d. Also partly visible are gate-lines 505 a
`dioxide dielectric, an oxide of silicon dielectric, and a dielectric with a
`through 505 d which are coupled to a corresponding 4:1 multiplexer (not shown).
`
`
`tensile stress of 5×108 dynes/cm2 or less.
`When one of the gate-line enables is active, the corresponding gate-line is
`coupled to an output line 507 of the multiplexer (formed in a Metal-2 layer, for
`46. An integrated circuit structur