Case 1:14-cv-01430-LPS Document 308-13 Filed 06/22/20 Page 1 of 7 PageID #: 20927
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`Exhibit 13
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`Case 1:14-cv-01430-LPS-CJB Document 109-2 Filed 04/20/16 Page 183 of 240 PageID #:
`Moore's Lag Shifts Paradigm of Semi Industry | EE Times
`11/20/2014
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`Blog
`Moore's Lag Shifts Paradigm of
`Semi Industry
`Moore's Law lagging may be a good thing
`Zvi Or-Bach, MonolithIC 3D Inc.
`9/3/2014 04:30 PM EDT
` 15 comments post a comment
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`krisi thank you Colin, interesting
`info...2 years to volume production
`sounds very aggressive
`
`11/20/2014
`2:14:11 PM
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`According to Zvi Or-Bach, president and CEO of MonolithIC
`3D Inc., 28nm will be the last process node following Moore's
`Law for most designs.
`
`In an earlier column, 28nm – The Last Node of Moore's Law, we
`pointed out that the change has already happened. It is no longer
`a matter of forecast or prediction. In this blog, we will start by
`reviewing some of what has transpired since that column was
`published. Then we will focus on the ensuing paradigm shift in the
`semiconductor industry.
`
`The following chart was presented in the IEEE IITC workshop by
`GlobalFoundries. It illustrates the cost impact of the double
`patterning required for scaling below 28/22 nm.
`
`Click here for a larger image.
`
`In his coverage of Semicon West, Rick Merritt wrote: "Moore's
`Law has definitely slowed." He quoted Gartner semiconductor
`analyst Bob Johnson as saying, "No matter what Intel says,
`Moore's Law is slowing down. Only a few high-volume, high-
`performance apps can justify 20 nm and beyond."
`
`Soon thereafter, in a Semiconductor Manufacturing & Design blog
`post about ConFab 2014, Peter Singer quoted Dr. Gary Patton,
`vice president of semiconductor research and development center
`at IBM, as saying: "The challenge we're facing now is two-fold.
`Number one, we're struggling to get that 0.7X linear scaling. It
`might be about 0.8X. And we're adding a lot more complexity,
`especially when you adding double and triple patterning."
`
`More recently, in early August, we finaly got more information
`http://www.eetimes.com/author.asp?section_id=36&doc_id=1323755
`
`1/6
`
`

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`More recently, in early August, we finaly got more information
`from Intel about its upcoming 14nm technology node. In our blog
`Intel vs. Intel, we articulated that Intel's numbers indicate that
`Moore's Law stopped at the 28/22nm nodes, both in terms of the
`required bringup time and the cost of the new technology nodes.
`
`It is hard to accept that a trend that has held strong for 50 years,
`and that kept going many years after multiple predictions of its
`imminent demise, has really stopped. And it is even harder as we
`watch the huge effort of bringing up the 14nm and 10nm nodes.
`Yet it seems that everybody should agree that the semiconductor
`industry is now going through a paradigm shift and -- for most
`designs -- 28 nm is, at least for some time, the last node of
`Moore's Law.
`
`These well-known charts present the reason for that change.
`
`Click here for a larger image.
`
`These charts show that design costs increase by more than $100
`million from 32 nm to 16 nm. If we assume a die cost of $10 at 32
`nm, and if we assume that the traditional cost reduction per node
`still holds, then we would need a volume of more than 20 million
`units just to break even. If one also considers the risk associated
`with such a design, it would actually require more than 100 million
`units -- or at least $1 billion of market -- for such device to justify
`the investment. Clearly, very few designs have the market for 100
`million units or $1 billion.
`
`The following chart by IBS presents the past trend in design starts
`per node. As we see, most new designs are still created at the
`130nm node, while the node with the fastest rampup is at 65 nm.
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`Design starts per year; click here for a larger image.
`(Source: IBS Dec 2012)
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`A 2016 forecast from Anysilicon on semiconductor technology
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`Alvie on Gimme an MMU!
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`Case 1:14-cv-01430-LPS Document 308-13 Filed 06/22/20 Page 4 of 7 PageID #: 20930
`Case 1:14-cv-01430-LPS-CJB Document 109-2 Filed 04/20/16 Page 185 of 240 PageID #:
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`11/20/2014
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`Yet again, this indicates a very slow shift to more advanced
`nodes, and the expectation is that -- even in 2016 -- most new
`designs will still be implemented at the 130nm node. This is clearly
`a paradigm shift in the industry, which is responding accordingly.
`Just before Semicon West 2014, we saw the conclusions of the
`SEMI's World Fab Forecast. This forecast uses a bottom-up
`methodology, providing high-level summaries and graphs, along
`with in-depth analyses of capital expenditures, capacities,
`technology, and products by fab. The following chart illustrates
`this new paradigm.
`
`Click here for a larger image.
`
`The report states:
`
`The cost per wafer has become an increasing
`concern below the 32nm node. The expected cost
`reduction benefit of production at smaller nodes is
`diminishing and is not keeping pace with the scaling
`benefits in many cases. This has widespread and
`fundamental implications for an industry long
`following the cadences of Moore's Law…
`
`These may be contributing factors as to why some
`volume fabs are exhibiting a lag in beginning
`production of a new technology node. Now evident
`quantitatively for the first time, there is evidence of a
`clear slowdown in volume production scaling of
`leading technology node transitions. [Emphasis
`added]
`
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`Mark Bohr on continued decline of
`http://www.eetimes.com/author.asp?section_id=36&doc_id=1323755
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`Case 1:14-cv-01430-LPS Document 308-13 Filed 06/22/20 Page 5 of 7 PageID #: 20931
`Case 1:14-cv-01430-LPS-CJB Document 109-2 Filed 04/20/16 Page 186 of 240 PageID #:
`Moore's Lag Shifts Paradigm of Semi Industry | EE Times
`11/20/2014
` 3215
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`cost/transistor
`sranje 9/12/2014 6:56:50 PM
`“One of the fundamental benefits of Moore’s Law is smaller
`feature sizes, primarily to get lower cost per transistor so we
`can do more things” in a similarly sized chip, he said. Intel
`already announced it has started making in volume chips
`using a 14 nm process at a lower cost per transistor than its
`prior 22 nm generation. It also said it is in development of a 10
`nm process that it believes will deliver lower cost per
`transistor.
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`Other options
`DrFPGA 9/7/2014 10:19:44 AM
`When fpgas are used to dynamically adapt and accelerate
`algorithms their transistors can get used and reused for
`multiple functions. Maybe this is one option to improve cost
`performance...
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`Monolitihic 3D enabling ultra-large
`energy efficient systems
`Zeev00 9/5/2014 1:35:59 PM
`One point that was not, perhaps, stressed enough is the huge
`energy saving at the system level enabled by monolithic 3D.
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`We all understand the energy savings because of shortened
`interconnect in 3D layers. Yet it seems that for large system
`this saving is limited to about a factor of 2 at best. Actually, it is
`potentially much more. For large-scale processing such as
`HPC, most of the energy goes to shuttling data off-chip across
`multiple processors and multiple memory subsystems. One
`cannot assume multiple layer HPC processors, as the heat --
`even if sinked across layers -- needs to be dissipated. But one
`can imagine a 3D layer of processor and memory subsystems
`sandwich that is arrayed on a huge wafer-sized chips. There is
`almost no off-chip driving of data in such an array, the memory
`is very close to the processors, and the "only" problem is
`reliability (Amdahl growls here :-). Yet having a 3D
`redundancy layer that is able to correct for hundreds of faults
`in the processor logic, neatly works around the reliability
`issue. And power has a much larger area to be dissipated
`from.
`
`In other words, new 3D-enabled architectures could allow for
`almost inifinitely-sized chips, overcoming the biggest energy
`barrier in HPC and exascale computing.
`
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`Re: Moore's " lag"
`Or_Bach 9/5/2014 5:04:10 AM
`3D Guy, I am glad that you like the term - Moore's "lag" - but
`the credit should go to Max Maxfield (The EE Times editor).
`
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`As to the VC returning to the semiconductor space let me
`make the following points:
`
`A. For VC investments it takes years before real high volume is
`resulted, so even if you are correct about these technologies
`being niche there is no contradiction there
`
`B. The escalating chip designs cost associated with dimension
`scaling drove out the VCs from semi. Once the market will
`develop alternative technologies to add value cost of masks
`and all other NRE related cost will trend down and with lower
`investment requirements more VC would consider again these
`type of ventures
`
`C. If you believe that IOT and wearable are anything close to
`the many trillions of dollar that Cisco and other are forecasting
`than you have to agree that vibrant venture activity is a must
`which lead to the kind of environment that VCs are part of.
`
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`Re: Heterogeneous integration
`Or_Bach 9/5/2014 4:41:39 AM
`Packaging has an important role as off-chip interconnect is
`1,000x worse than on-chip interconnect. Any improvment
`would impact the end system power and performance BUT
`keeping the cost down has been the problem so far.
`
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`Heterogeneous integration
`escher 9/4/2014 10:16:05 PM
`Zvi, What is your take on advanced packaging technology and
`its ability to enable heterogeneous integration?
`http://www.eetimes.com/author.asp?section_id=36&doc_id=1323755
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`Case 1:14-cv-01430-LPS Document 308-13 Filed 06/22/20 Page 6 of 7 PageID #: 20932
`Case 1:14-cv-01430-LPS-CJB Document 109-2 Filed 04/20/16 Page 187 of 240 PageID #:
`Moore's Lag Shifts Paradigm of Semi Industry | EE Times
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` 3216
`its ability to enable heterogeneous integration?
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`Slowing Moore's Law has its
`advantages
`betajet 9/4/2014 6:01:39 PM
`At his EE Live! 2014 keynote, "Bunnie" Huang talked about
`how slowing Moore's Law helps small developers, especially
`Open Hardware teams. It used to be that by the time such a
`team succeeded in shipping a product, standard PCs would
`have leap-frogged them in performance. With Moore's Law
`slowing, small developers have a better chance to ship
`products while they are still relevant.
`
`Here's an EE Times article with more detail:
`www.eetimes.com/document.asp?doc_id=1321796
`
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`Re: Intel's 14nm progress
`bec0 9/4/2014 5:47:21 PM
`Gondalf: Monolithic 3D can provide more than just one node of
`scaling. Both university and industry studies show it...the challenge
`has been how to make it. The upcoming S3S conference has some
`papers suggesting simple ways to get monolithic 3D. There is a good
`bit of cost savings too; the footprint is 25% of the original and the
`total silicon area is 50% when folding a logic design into two layers.
`Why? Mostly repeaters/buffer savings and transistor sizes....average
`wire length in the chip goes down. This blog goes thru some of the
`details (www.monolithic3d.com/3d-ic-edge1). And both layers are
`mono-crystalline silicon...with layer transfer the cost of the top layer
`mono-Si is amortized over the 10-20 times you use the donor wafer.
`Bottom line...it looks just like a node of scaling. Plus, designers/EDA
`now have another degree of freedom to exploit for compact and
`efficient architectures. Also, why not mix layers? Two logic layers (for
`logic redundancy), then one or more memory layers (maybe NV),
`then two more logic. Cool on both sides if needed.
`
`Yes, 3DIC in general has to deal with improving the heat
`conduction. Heat removal is a matter of getting a high enough
`lateral and vertical conduction to a sufficient heat-sink to
`overcome the operational heat generation. This blog talks to
`this with reference to an IEDM2012 paper by Stanford
`(www.monolithic3d.com/blog/can-heat-be-removed-from-3d-
`ic-stacks) on how to do that. Lateral conduction for the
`monolithic 3DIC case is solved by rigorously using the
`Vss/Vdd network to move the heat laterally as if the 2nd layer
`'substrate' is bulk Si, and the vertical conduction is taken care
`of by the high density of available vertical 'heat pipes' of
`monolithic 3D...10e6-10e8/cm2. The IEDM work ran both
`layers (substrate and monolithic 2nd layer) really hard and hot,
`and reasonable cooling was accomplished with the interlayer
`vias and power grids. The larger issue was getting sufficient
`heat sink capability...had to go to liquid cooling to get all the
`watts out of the stack.
`
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`Moore's " lag"
`3D Guy 9/4/2014 5:12:48 PM
`Zvi, Well researched article, as always. I like the term "Moore's
`Lag". Very catchy. You mention "Moore's Lag" will cause:
`
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`(1) Innovation into new technology and VCs will come back to
`invest in the industry.
`
`(2) While (1) may happen, I think we should stay awake to the
`possibility that new technology like SOI and subthreshold and
`others will remain niche for many more years and even if
`used, will not provide the long-term benefits scaling used to.
`Net result: Semiconductor technology will get even more
`commoditized and differentiation will happen at higher levels
`(eg. at the system and application levels). The VCs will
`continue to stay away from new semiconductor stuff, both
`because of its commoditized nature and because of the huge
`amount of investment needed for adequately proving out any
`idea and making money off it.
`
`Let's have a bet. I'm betting on (2).
`
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`Re: Intel's 14nm progress
`Gondalf 9/4/2014 4:04:02 PM
`Ummmm 3D interconnection could give "one" node stop just to
`help some companies about costs. Still nobody can avoid the
`shrink, it could be delayed for a couple of years but it is
`USER RANK
`inevitabile. Moreover we don't know the exact impact on costs
`FREELANCER
`http://www.eetimes.com/author.asp?section_id=36&doc_id=1323755
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`Case 1:14-cv-01430-LPS Document 308-13 Filed 06/22/20 Page 7 of 7 PageID #: 20933
`Case 1:14-cv-01430-LPS-CJB Document 109-2 Filed 04/20/16 Page 188 of 240 PageID #:
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`FREELANCER inevitabile. Moreover we don't know the exact impact on costs
`of design and its times. Another variable is "heat" and its
`removal, not all devices can be successfully designed on 3D
`interconnection, high power cpus for example are not well
`suited at all for this approach, but i have the suspect that even
`high perf. SOCs may have serious problems to keep their
`speed performance in tiny devices with the Tskin trick.
`
`I would make a distinction, stating that not all companies will
`benefit of these new stop gap solutions.
`
`
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