Case 1:14-cv-01432-LPS Document 238-9 Filed 12/12/19 Page 1 of 4 PageID #: 16135
`
`Exhibit I
`
`

`

`
`Case 1:14-cv-01432-LPS Document 238-9 Filed 12/12/19 Page 2 of 4 PageID #: 16136
`.
`Document 238 9 Fried 127’127’19 Page 2 6f 4 Page+D#: 16136
`
`Keith Gurnett
`
`and Tom Adams
`
`Within the last few years, backside thinning
`of fully processed 1C wafers has become a
`widely used technique in the search for high
`speed in advanced package technologies.
`Figure 3. shows the trend in finished IC thick-
`ness used in advanced packaging based on
`
`thickness figures quoted by various sources
`over the last ten years. The market potential
`for ultra-thin wafers, with backside metal-
`
`lization, is estimated by market researchers
`to be above 40% of the wafer market by the
`year 2010.
`
`Ultra-thin semiconductor
`
`wafer applications and
`
`processes
`
`The ongoing development in functionality of
`integrated circuits is now targeted on the integra»
`tion of all of the electronic elements in the total
`
`systeiu.This research is working from a base of
`many differing, semiconductor processes, Each of
`these processes will have a different attibute in
`terms of functionality sucah as speed, power etc.
`
`Wafer thickness
`
`(for advanced packaging techniques)
`
`0 Quoted in 1995
`
`1‘3 Quoted in 2000
`
`<>Quoted in 2005
`
`Year
`
`
`~<>< 50 micron
`
`1995
`
`2000
`
`2005
`
`2010
`
`Figure '1. Trend in ultra thin wafers for advanced packaging.
`
`VOL 19 - NO 4 - MAY 2006
`
`n Ill-Vs REViEW
`
`/\
`\/
`
`Three factors have concentrated development on
`thinner wafers: the demand for a low package
`height for chip cards and RFIDs, the requirement
`for higher power, and the search for Systems in a
`Pack (SiP) using chip stack methods.The premise
`is that the heat flow through the chip is greatly
`enhanced and through holes in the wafer create
`direct interconnection to adjacent dieAll of this
`is advantageous to chip stack technology, high
`speed and increased power. It is unusual to have
`three improvements take effect Without some
`loss of functionality.
`
`GaAs is extremely useful in the field of high-
`speed circuits. but its performance in terms
`of light emission is inhibited by its poor
`dissipation of the heat that accompanies
`light emission. Ultravthin GaAs chips allow
`greater thermal dissipation and also assist in
`the vertical interconnection through the chip
`by the use of vizls. Many systems have. this
`basic makeup: (iaAs high—speed circuits in the
`front end of systems, complex logic control
`circuitry in the middle, and power capability
`at the back end.
`
`This feature looks at the various processes used
`and being developed in order to exploit the
`virtues of speed, power and integration into sys
`tems that are offered by thin wafer devices.
`Currently, device chip stacks lead the way, but
`wafer processing by wafer bonding as against chip
`processing will be vigorously explored in order to
`achieve cost effectiveness, Chip processing will
`
`ELM EX_00000096
`
`

`

` Processin
`Case 1:14-cv-01432-LPS Document 238-9 Filed 12/12/19 Page 3 of 4 PageID #: 16137
`
`Casel:lAch$432LPS Document2389 Filedl
`
`need to overcome serious obstacles to acceptable
`yield.
`
`Thinning by grinding
`Back grinding is the conventional method for
`reducing wafers from their original thickness to
`a diminished thickness suitable for final packag-
`ing of die after dicing. Grinding is fast and pro’
`duces low variation and good surface finishes.
`For new, emerging applications that use very thin
`and ultrawthin die, grinding remains the common
`thinning method, but some process modifica-
`tions and additional techniques are required.
`
`Precisely controlled grinding
`rate
`Modern grinders rotate the wafer on a vacuum
`chuck and feed the rotating grind wheel into the
`backside of the wafer at a precisely controlled
`rate.The delicate grinding wheels employ graded
`diamond abrasives embedded in specially engi—
`neered binders on the wheel edge.Thc current
`production limit for grinding reduces wafers
`from an average starting thickness of 750 pm to
`as thin as 150 tunYield loss considerations from
`grinding and downstream processes (debonding
`from carrier) have made it very difficult to thin
`below 150 pin in production. Research projects
`on the other hand are consistently working
`below the 150 um level and creeping towards
`the 50 um level.
`
`Ground surface finishing
`processes
`Three methods are currently employed to
`remove grinding damage and improve the final
`surface finish:
`
`-
`
`traditional loose abrasive polishing;
`
`- wet etching;
`
`- dry plasma etching.
`
`The first method typically integrates a polishing
`step into the grinder itself, a method that offers
`the advantage of integrating the damage removal
`into the grinder tool and builds upon traditional
`(2MP (chemicalimechanicalipolishing) technology.
`(IMP, however, has the disadvantage of low
`removal rates and perpetuates the surface profile
`
`The second method uses familiar wet-etching
`process ’8
`to remove surface damageiW/et chemi-
`cal etching is one of the most common thinning
`techniquesTo etch one side of the wafer, one
`
`
`
`This is an ANADIG/CS GaAs wafer that has been thinned (after die separation); The die on
`[his wafer have been parlla/ly removed from the wafer:
`
`/\
`\/
`
`approach is spin etching, in which a thin stream
`of an etching agent is moved periodically over
`the surface of the rotating waferThe front sur-
`face of the wafer is protected either by addition—
`:11 layers, or by applying special chucks that allow
`the processing of thin wafers without surface
`protection layers or tapes.
`
`The third method uses atmospheric dry plasma
`etching to remove surface damage/VHS method
`offers the advantage that the surface damage is
`removed, the edges are improved by rounding
`the sharp edge, and the surface roughness can be
`controlled where needed for adhesion.
`
`Wafer handling
`In order to handle delicate thin wafers the
`
`device wafer is bonded to a rigid carrier sub»
`strate prior to the back-thinning process.’l‘he
`originally thick device wafer is bonded with its
`active surface to a carrier wafer using an adhe—
`sive bonding l: yer. After backside processing,
`including the thinning process and eventually
`further process steps (lithography, etching. etc),
`the thin device wafer, supported by the rigid carv
`ricr substmte, has to be released from the carrier
`wafer, enabling dicing and packaging processes
`in the final stages.
`
`www.th ree-fives.com
`
`ELM EX_00000097
`
`

`

`
`Processing
`Case 1:14-cv-01432-LPS Document 238-9 Filed 12/12/19 Page 4 of 4 PageID #: 16138
`: 16138
`Document2389 Filed127’127’19 Page4of4Page+D#
`
`Partially Singulated 10
`
`“3"; EMKH‘MMMM 3i"
`
`Bonded to carrier for thinning
`
`Mt“
`
`To be thinned
`
`by grinding
`
`The bonding strength for a wax layer is large
`enough to Withstand even harsh mechanical
`processes such as grinding and polishing. For the
`release of the device wafer from the carrier sub-
`strate, two methods can be usedzThe wax can be
`dissolved in a solvent or it can he softened and
`
`released by heating,
`
`Temporary bonding and
`debonding with dry-film
`laminates
`The recently increasing popularity of dry-film
`adhesive tapes, especially for thermal-release
`bonding, can be attributed mainly to the ease of
`the application and the enhanced thermal
`I‘ClCZISC temperature.
`
`A novel thinning technique
`The mechanical properties of ultra-thin and com-
`pound semiconductor wafers, such as brittleness,
`generate difficulties in wafer handling through
`the multistep processes involving cleaning, coat-
`ing, lithography, etching or thinvfilm deposition
`Whenever standard silicon material thickness
`
`falls below 100 um the material properties
`become similar to those of brittle compound
`semiconductor materials such as GaAs,
`
`A new method of singulating by back
`etching/grinding is shown in Figure '2. Front side
`grooves are cut in the wafer streets before back
`grinding. Chip separation takes place during
`backside thinning when family the front side
`grooves are opened. If the last step is a backside
`spin—etching process, grooves are rounded by the
`ctchant and possible residual microcracks are
`removed. The etchant can also act as stress relief
`
`to the singulated chips.
`
`Conclusions
`All the necessary processes to create, ultra-thin
`devices are available and only need to be refined.
`The fragility of the wafer structure before singu
`lation demands special procedures in order to
`complete the pi'ocessitig.After the wafer has
`been singulated into chips, the problems of
`fragility diminish.'l‘he development of through-
`hole interconnect and chip stack, be it in chip or
`wafer form, brings the back end process into the
`fab. This implies greater process control from
`start to finish. Back-end processing has always
`been considered as outside the fab environment.
`
`Bringing it inside will only benefit the final
`device reliability
`
`/\
`\/
`
`Figure 2, Singu/ar/‘ng by back grinding,
`
`The adhesives used for temporary bonding allow
`the release of the device wafer by using different
`approaches: UV release adhesives debond after
`exposure to UV light, thermal release adhesives
`have to be heated above a release temperature
`and solvent release adhesives have to be dis-
`
`solved in a chemical solvent for debtmding of
`the device wafer from the carrier.
`
`The temporarily bonded stack, consisting of
`device wafer, intermediate layer and carrier
`wafer, is generally further processed using several
`different techniques (eg. lithography, etching,
`etc.) Several different aspects, therefore, must be
`taken into account before selection of the inter-
`
`mediate layer for the targeted application.
`Temperature capability, chemical resistance, ease
`of processing and thickness variations are just
`some of the parameters that need to be consid-
`ered when choosing the adhesive method to be
`used between carrier and wafer.
`
`Temporary bonding and
`debonding with waxes
`Reversible wafer bonding, using lows or high,
`temperature waxes (up to 170°C) requires a
`wax coating step in liquid phaseThc highest
`level of uniformity for the spin-coated wax is
`essential.
`
`Ill-Vs REViEW
`
`VOL 19 - NO 4 - MAY 2006
`
`ELM EX_00000098
`
`