Case 1:14-cv-01432-LPS Document 238-2 Filed 12/12/19 Page 1 of 14 PageID #: 16085
`
`Exhibit B
`
`

`

`Case 1:14-cv-01432-LPS Document 238-2 Filed 12/12/19 Page 2 of 14 PageID #: 16086
`Case 1: 14--cv- 01432- LPS Document 238-2 Filed 12/12/19 Page 2 of 14 PagelD #: 16086
`IEEE TRANSACTIONS ON COMPONENTS, PACKAGING, AND MANUFACTURING TECHNOLOGY“PART 8 VOL. 21, NO. FEBRUARY 1998
`
`A Review of 3-D Packaging Technology
`
`Said F. Al-sarawi, Member, IEEE, Derek Abbott, Member, IEEE, and Paul D. Franzen, Member, IEEE
`
`in three-
`Abstract— This paper reviews the state—of—the-art
`dimensional
`(3-D) packaging technology for very large scale
`integration (VLSI). A number of bare dice and multichip module
`(MCM) stacking technologies are emerging to meet the ever
`increasing demands for low power consumption, low weight and
`compact portable systems. Vertical interconnect techniques are
`reviewed in details. Technical issues such as silicon efficiency,
`complexity, thermal management, interconnection density, speed,
`power etc. are critical in the choice of 3-D stacking technology,
`depending on the target application, are briefly discussed.
`
`Index Terms—Bare dice stacking, MCM stacking, 3-D MCM
`technology, 3-D packaging, vertical interconnection.
`
`I.
`
`INTRODUCTION
`
`S the complexity of portable electronic systems increases,
`such as in the shift
`from the mobile phone toward
`the Interactive Mobile Multimedia Personal Communicator
`
`(IM3PC) paradigm [I], greater demands are being placed on
`the production of low power, low weight and compact packag-
`ing technologies for VLSI integrated circuits. Likewise many
`aerospace and military applications are following this trend.
`In order to meet this demand, many new three-dimensional
`(3—D) packaging technologies are now emerging where either
`bare dice or MCM s a1e stacked along the;-axis resultingin
`dramatic improvement in compactness. As this 2—plane tech—
`nology results in a much lower overall interconnection length,
`parasitic capacitance and thereby system power consumption
`can be reduced by as much as 30% [2].
`Section II will discuss the advantages of 3-D packaging
`technology and its effect on system performance. Section III
`will provide a brief discussion of the different vertical inter—
`connection methods used in 3-D packaging, while Section IV
`will address the limitations of the3 —D technology.
`
`II. ADVANTAGFS OF3 -D PACKAGING TECHNOIOGY
`
`The following subsections discuss briefly how 3-D pack-
`aging technology enhances system performance and provides
`performance factors that cannot be achieved using conven-
`tional packaging technologies.
`
`A. Size and Weight
`
`By replacing single chip packages with a 3—D device,
`substantial size and weight reductions are achieved. The mag-
`nitude of these reductions depends,
`in part, on the vertical
`interconnection density and accessibility, which will be dis—
`cussed in Section II-G, thermal characteristics, and robustness
`required. It has been reported that 40 to 50 times reduction
`in size and weight is achievable using 3-D technology com-
`pared to conventional packaging. As an example, volume and
`weight comparisons between TI’s 3-D bare dice packaging
`and discrete and planar packaging (MCM) are presented
`in Tables IiVll. It
`is evident from these tables that a five
`
`to six times reduction in volume is possible over MCM
`technology and a ten to 20 times reduction over discrete
`packaging technology. Moreover, a two to 13 times reduction
`in weightis also achievable compared to MCM technology and
`a three to 19 times reduction compared to discrete components.
`All of these reductions result from eliminating the overhead
`weight and size associated with conventional
`technologies.
`Furthermore,
`in the case of the Aladdin parallel processor
`[3], the reduction in size and volume against the Cray X—MP
`benchmark was by about 660 and 2700 times, respectively.
`
`B. Silicon Ejficiency
`
`One of the main issues in packaging technology is the chip
`footprint, which is the printed circuit board area occupied
`by the chip [5] as defined in Fig, I. In the MCM case, the
`footprint is reduced by 20—90% because of the use of bare
`dice. Three-dimensional packaging results in 21 even more
`efficient utilization of silicon real estate, which is referred
`to as “silicon efficiency.” We can define silicon efficiency as
`the ratio of the total substrate area in a stack to the footprint
`area. Consequently 3—D technology exceeds a 100% silicon
`efficiency compared to other two-dimensional (2-D) packaging
`technologies.
`
`C. Delay
`
`Manuscript received April 30, 1997; revised August 20, I997, This work
`was supported in part by the Defence Science and Technology Organization
`(DSTO), Australia.
`S. F. Al-Sarawi and D. Abbott are with the Centre for High Per-
`formance Integrated Technologies and Systcms
`(Cl—IiPch). Department
`of Electrical and Electronic Engineering, The University of Adelaide,
`Adelaide 5005. South Australia (eemail: alsarawi@eleceng.adelaideeduau;
`dabbottgggelecengadelaidecdn.au).
`P, D. Franzon is with the Department of Electrical and Computer
`Engineering, North Carolina State University, Raleigh, NC 27695 USA
`(e-mail: paulf@eos.ncsu.edu).
`Publisher Item Identifier S l070-9894I98)00595«7.
`
`to travel
`Delay refers to the time required for a signal
`between the functional circuit blocks in a system. In high speed
`systems, the total delay time is limited primarily by the time of
`flight, which is defined as the time taken for the signal to travel
`(fly) along the interconnect [6]. The time of flight, 15, is directly
`proportional to the interconnect length. So reducing the delay
`requires reducing the interconnect length which is the case
`when using 3—D packaging, as shown in Fig. 2. The resultant
`reduction in interconnect length, results in a reduction of the
`interconnect associated parasitic capacitance and inductance,
`hence reducing signal propagation delays. For example,
`the
`signal delay as a result of using MCM’s is reduced by about
`3000/0. Furthermore the delay would be less in case of3——D
`1998 IEEE
`107079894/9881000
`
`ELM EX_00000001
`
`

`

`Case 1:14-cv-01432-LPS Document 238-2 Filed 12/12/19 Page 3 of 14 PageID #: 16087
`Case 1:14-cv-01432-LPS Document 238-2 Filed 12/12/19 Page 3 of 14 PagelD #: 160873
`AL-SARAWI at 51].: REVIEW OF 3»D PACKAGING TECHNOLOGY
`
`
`
`
`
`
`
`
`
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`
`TABLE II
`A LIST OI“ MUST OI‘ THE COMPANIES AND lNSTlTUTIONS
`_
`_
`I
`v
`v
`“ ORKING I\ THE AREA OF 3 D PACKAGING {/8]
`
`._ W _
`V
`_,
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`Packaged D“? StaCk‘n“
`”Custom 105
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`Standard 1C5
`
`
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`
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`II‘VIIic Scnsi’us
`IIHIJll'X
`’I‘lIOIIINIInACINi
`Dunno-Pac-
`Smnsuni‘, Flrli’llollll‘h
`Matsiishim (KII‘II)
`Fujitsu
`Grumman
`
`'l'homson-CI“3
`Hughes
`Tums Instiuinimis
`Il‘rlll'l‘w‘
`
`Hitachi tic Intel
`Toms Instruments
`nlllilp,
`llll'.
`Illlflfllll
`
`
`\"fllI/l‘OlllC, Inc
`Motsiisliim
`NFC Corp.
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`
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`
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`
`TABLE [V
`TABLE I
`3-D MASS MEMORY VOLUME AND WEIGHT COMPARISONS BETWEEN
`AN EVALUATION OF COMPANIES WHICH PROVIDE
`
`OTHER TECHNOLOGIES AND TEXAS 3-D TECHNOLOGY IN CMJ/Gbit [4]
`PERIPHERY INTERCONNECTION BETWEE\ STACKED IC’s
`
`7
`Type Capacity Discrctc
`2D 3D,
`2D (:9
`tampon):
`Application
`Country intercimncctioii 'l‘gchniquc
`
`Weight,
`SRAM
`1 erit
`1678
`783
`133
`5.0
`Matsnshita
`Nleiiici
`s”
`W
`Jiiiani
`StackI-d TAB carrier (PCB)
`
`
`4 Mlyil
`872
`249
`41
`{i ]
`Si; kcd TAB cni‘riu (lcmlfriimc)
`Fujitsu
`vaiiiiiriits
`Japan
`
`DRAM
`Soldcr dipped stacks to Ornate Vertical
`leit
`141 7778787
`10
`DUNSK‘, Pin:
`Mommies
`USA
`
`1 Mliit
`3.0
`conductors on edge
`
`Micron
`6.2
`’ ”7 WE"
`Solder Iillod holes in cinp carriers and
`
`z
`’j’",
`,
`.
`7 ’Ii'i'linology
`siiiicuis
`
`connections
`1 Mbit
`7790
`\uluinc
`SRAM
`Hitachi
`Soldcr
`
`)-9
`Wihibit
`through ll()l('
`and sputtered
`l Mblt
`il'b
`'I'IIIII
`film "ILI'OnnOcts‘
`4‘ Mblt
`2"“)
`metal conductors
`H" Mb“
`2'9
`Dll'l-‘Cl
`laser Milt-I
`traces On epoxy (‘lllll‘
`fun:
`PC hoards soldcrcd On two sides Of 'I'SUI)
`
`pack‘
`as
`
`Arm if’I'AIl loads soldered to bumps on
`silicon SthSLlflLL‘
`A ilip»cliiii lmndcd tO faces of the Stack
`Folded Ilcx circuits
`Folded llvx (‘lrt‘ulis
`Folded Ik'x (‘iIItiiils
`Wirc bonded to on MCM siibstiatc
`Circa”
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`W bonded W 2‘ “lb“ ““0 ‘hml'gh an “3
`Wfiiiiifii
`7
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`
`
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`
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`
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`FIAIII’I',
`drip‘rll)
`
`[25};
`
`USA
`L'SA
`L'SA
`[ISA
`France
`LISA
`
`
`
`Memories
`
`Mrmorics
`
`Mcirioiins/ASICs
`h'liiiiiiiii‘s/AflCs
`Mciiimii‘s
`
`Mummies/Aflfis
`
`,
`
`Toxin:
`lnstin'ncnis
`ASICS
`Grumman
`Aerospncn
`Gcnm '41 Electric ASICs
`Haiiis
`ASICs
`MCC
`ASICS
`Matia Marconi
`NIi‘niorics
`
`ELEM
`JISICS
`
`_
`
`TABLE V
`AN EVALUATION or COMPANIES WllICll PROVIDE
`AREA INTERCONNECTION BETWEEN STACKED [C’s
`
`Company
`Application
`Country Interconnection chliniauc
`iitsu
`Li
`L
`dipan
`1}
`up iiiifN .Jdtl‘iil NIH» sithoiii
`TABLE III
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`TABLE VI
`Omnm
`Cubic Mam”
`AN EVALUATION OF COMPANIES WHICH PROVIDE
`PERIPHERY INTERCONNECTION BETWEEN STACKED IVICM’S
`Hon ’szll and Coors
`O
`
`
`
`Company
`7 Application Couintryl interconnection Tochniduc'
`7
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`A
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`USA
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`'
`m
`a /
`ASIC
`[Sit
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`lill‘lillLMEQi
`tr,
`side of stack
`
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`ellaiioii intc (-n'iociimi
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`B: I,
`“Gammon“ “9mm“
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`proximity (0 each other, as shown in Fig 2.
`
`
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`of
`
`lllulll’ USA
`ASIC /'
`IIW‘W" ”mt"
`ASIC / 'inOIliL'S
`USA
`
`D. Noise
`I
`-
`-
`-
`AN EVALUATION OF LOMPANIES WHICH PROVIDE
`TAP”; ‘11
`‘
`News In gcncral can be defined as unwanted disturbances
`
`AREA INIERCONNECHOX BHWEW S1ACKED MCM‘s
`superimposed upon a useful signal, Which tend to obscure
`
`its information content. In high performance systems, noise — ,7 1,,
`
`
`,
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`,
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`Company
`Application W Country Interconnection Technique
`
`Inaflagenlelit
`IS a Hlajor deSlgH lssue‘ NOISe Can hmlt
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`creasmg delays, and reducmg nOISe margins and can cause
`I'ccdthroughs
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`"'““‘ri“‘
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`-
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`Stacked silicun wafeis with Iillcd \, as
`reflection nmsc;
`1)
`/
`2) crosstalk noise;
`3) simultaneous switching noise;
`4) electromagnetic interference (EMT) [7].
`The magnitude of all of these noise sources depends on the
`rise time of the signals passing through the interconnect.
`The faster the rise time,
`the worse the noise. The role of
`
`
`
`Stacked silicon wafers with lillod VIZLS
`,
`1
`
`,
`
`3—D technology in reducing noise is in the reduction of
`interconnection length, and hence reduction of the associated
`parasitics which translate into performance improvements. On
`
`ELM EX_00000002
`
`
`
`
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`

`

`Case 1:14-cv-01432-LPS Document 238-2 Filed 12/12/19 Page 4 of 14 PageID #: 16088
`Case 1: 14--cv- 01432- LPS Document 238-2 Filed 12/12/19 Page 4 of 14 PagelD #: 16088
`FEBRUARY 1998
`IEEE TRANSACTIONS ON COMPONENTS, PACKAGING, AND MANUFACTURING TECHNOLOGY“PART 8 VOL. 21, NO.
`
`I‘iflfiprinl used
`by even, chm
`
`Substrate used by
`Substrate area used by the MCM
`Focipnm med by
`the 5!) device
`the 3!) device
`/
`
`
`\
`
`
`
`
`
`Fig. l. A graphical
`and 3-D technology,
`
`illustration of the silicon efficiency between MCM’s
`
`3D Structure
`
`30 Structure
`
`Hg. 2. A comparison between the wiring lengths in 2-D and 3«D structures
`[79].
`
`the other hand, the noise could be problematic in a system
`if the used 3-D technique does not address the noise. For
`example,
`if the interconnections have not got a uniform
`impedance along the line or its impedance does not match
`the source and destination impedance, there is the potential
`for reflection noise. Furthermore, if the interconnects are not
`spaced enough there is also a potential for crosstalk noise.
`Simultaneous is reduced because of the shortened intercon-
`
`nects and consequent reduction of the associated parasitics,
`so producing less simultaneous noise for the same number of
`interconnections.
`
`E. Power Consumption
`
`In an electronic system the energy dissipated, E, due to the
`interconnect parasitic capacitance. C, is given by, E = CV2,
`and therefore the power consumption is P : fCV2, where
`V is the voltage swing across the O and f is the number
`of transitions per second. As the parasitic capacitance is
`proportional
`to the interconnection length,
`the total power
`consumption is reduced because of the reduced parasitics. For
`example, let us say that 10% of the system power consumption
`is dissipated in the interconnects when mounted on a PWB.
`If the product was implemented using MCM technology, the
`power consumption will be reduced by a factor of five. Hence,
`the product would consume 8% less power than the PWB-base
`product [8]. Furthermore, when such a product is implemented
`using 3-D technology the saving will be much more because of
`the reduced interconnect length and the associated parasitics.
`
`F. Speed
`
`The power saving achieved using 3—D technology can allow
`the 3-D device to inn at a faster rate of transitions per second
`(frequency) with no increase in power consumption. In addi-
`tion, the reduction in parasitics (capacitances and inductances),
`size and noise of a 3-D device, allow for higher transitions per
`second which would increase the overall system performance.
`For example, the Aladdin parallel processor, achieved 35 000
`and 10 800 in MIPS and FLOPS per unit volume improvement
`
`
`
`(a)
`
`(b)
`
`Fig, 3. A comparison between 2-D and 3-D packaging interms of the
`accessability and useablity of interconnection.
`
`over the Cray X-MP as a result of integration using 3-D MCM
`technology [3].
`
`G. Interconnect Usability and Accessibility
`
`The use of a 3-D packaging configuration provides access to
`116 neighbors within an equal interconnect length to a centre
`element in the stack, in contrast to eight neighbors to the centre
`element in the case of 2~D packaging technology, while as-
`suming atypical die thickness of 0.6 mm {9], [10] as illustrated
`in Fig. 3. Hence, reduction of the interconnect length in the
`stack results in reduction of propagation delay between chips.
`Furthermore, the available vertical interconnection results in
`maximum utilization of the available interconnects in contrast
`
`to traditional packaging technologies where such utilization
`is limited by physical structures such as vias or holes or by
`previously routed interconnects (Fig. 4). The accessibility in
`case of 3-D packaging technology depends on the type of
`vertical interconnection employed as it is proportional to the
`available vertical
`interconnect density—which is defined as
`the number of signal layers per average wire pitch [1 l], [12].
`So, area interconnection provides the most accessibility and
`usability in contrast to peripheral interconnections, where the
`usability and accessibility are limited by the periphery length
`of the stacked element.
`
`H. Bandwidth
`
`is
`Interconnect bandwidth, especially memory bandwidth,
`often the performance limiter in many computing and commu-
`nications systems. Thus low latency (delay) and wide buses are
`very desirable. For example, in the well known Intel Pentium
`Pro, the CPU and Level 2 cache are packaged together in the
`same multi—cavity Pin Grid Array to obtain a large memory
`bandwidth. The exciting possibility is whether 3~D packaging
`technologies can be used to integrate a CPU and memory chips
`while avoiding the cost of the multicavity Pin Grid Array.
`III. VERTICAL INTERCONNECTIONS IN 3-D ELECTRONICS
`
`Vertical Interconnections [l3], [l4] refer to the intercon-
`nections needed to route power, ground, and signals to the
`layers within the 3-D Module. The following subsections will
`describe briefly the different types of vertical interconnections.
`
`A. Periphery Interconnection Between Stacked ICs
`
`interconnection tech—
`list
`The following subsections will
`niques used to interconnect stacked chips using the stack
`periphery.
`
`ELM EX_00000003
`
`

`

`Case 1:14-cv-01432-LPS Document 238-2 Filed 12/12/19 Page 5 of 14 PageID #: 16089
`Case 1: 14--cv-01432- LPS Document 238-2 Filed 12/12/19 Page 5 of 14 PagelD #:165089
`AL-SARAWI er a]: REVIEW OF 3D PACKAGING TECHNOLOGY
`
`3D Structure
`
`21) Structure
`
`oaonooooa
`
`
`
`
`Via Hole
`
`Wiring
`
`Fig. 4. A comparison between 3-D and 2-D structures in terms of the
`possible number of interconnections assuming one routing layer for the 2-D
`structure [79].
`
`
`
` TAB Leads
`Lead
`
`Fig. 5. Two variants of the stacked tape carrier vertical interconnect: (a)
`stacked TAB on PCB and (b) stacked TAB on leadframc.
`
`1) Stacked Tape Carrier: Stacked tape carrier is a method
`for interconnecting IC’s using TAB technology. This method
`could be divided further into stacked TAB on PCB and stacked
`
`TAB on leadfrarne as illustrated by the schematic diagram
`shownin Fig.51he IAB on PCB method is used by Intel
`Japan [15] and Matsushita Electric Industrial Company [l6],
`[17], [18]. In Matsushita’s case, they used this approach for
`designing high density memory cards. The second method is
`used by Fujitsu in designing DRAM chips [l9], [20].
`2) Solder Edge Conductors: Solder edge conductor bond-
`ing is a process where vertical interconnections between IC‘s
`are performed by soldering edge conductors. There are four
`variants of this method as follows.
`
`a) Solder dipped stacks to create vertical conductors on
`edge; In this approach,
`the leads of the stacked IC’s
`that are to be connected. are brought into contact using
`a static molten solder bath and simultaneously soldered.
`A schematic diagram on how such interconnections are
`performed is shown in Fig. 6(a). This method is used by
`
`Dense—Fae for designing high density memory modules
`[21], [22], [23].
`b) Solder-filled holes in chip carriers and spacers: In this
`approach the Vias are filled with a conductive material
`to interconnect the stacked IC using carriers and spacers
`as shown in Fig. 6(b), This method is used by Micron
`Technology in designing DRAM and SRAM chips [24].
`A similar technique was developed and patented by
`Hughes Electronics [25].
`c) Solder connections between plated through—hole: In this
`approach the IC leads are brought by TAB then in-
`terconnected using a small PCB called a PCB frame,
`which has Vias through it. The vertical interconnections
`are achieved using these Vias and by stacking these
`frames using a solder joint bonding technique as shown
`in Fig. 6(d). Hitachi has developed this method and used
`it in the design of high density DRAM’s [26].
`d) Edge array solder balls: In this approach, solder balls
`are placed along the edge of the chip and the chip is
`edge mounted on the substrate using solder reflow. For
`example, Hughes achieved this by dicing through the
`solder ball [27]. MCNC has achieved this by shaping
`the solder ball so that it “overhangs” the chip edge [28].
`MCNC is also capable of rerouting the pads to the edge
`of the chip as shown by the photograph of an early
`prototype in Fig. 7.
`3) Thin Film Conductors on Face-q/ia—Cube: A thin film
`is a layer of conductive material either sputtered or evaporated
`onto a substrate in a vacuum to form conductors. ‘Thin film
`conductors on face—of—a—cube’
`is a method where vertical
`
`interconnections are performed on the cube face. There are
`two variants of this method as follows.
`
`a) Thin film “Teconnects " and sputtered metal conductors:
`This method was jointly developed by Irvine Sensors and
`IBM. In this method, after the I/O signals are rerouted to
`one edge of the chip, a thin film metal layer is patterned
`on the surface of the stacked chips. Then, two processes,
`called lift-off photolithography and sputter-deposition,
`are performed on the face of the stack to form pads and
`buslines. creating what is called “T-connections” [29] as
`shown in Fig. 8.
`b) Direct laser write traces on epoxy cube face: In this
`method. the interconnect pattern on the sides of the cube
`is generated by laser trimming. This pattern is designed
`to intersect with the IC’s wires cross section on the face
`
`ofthe cube [30], [31] as shown in Fig. 9. This method is
`used by Thomson-CFS DOI for high density memories
`[30], mierocameras [32], [33]. medical applications and
`smart munitions [34], [31].
`4) An Interconnection Substrate Soldered to the Cube Face:
`In this method a separate substrate is soldered to the face of
`the cube as will be explained by the following variants of the
`method.
`
`a) Array of TAB leads soldered to bumps on silicon sub-
`strate: This method was developed and used by Texas
`Instruments in the design of very high density memo-
`ries [35], [36],
`[37]. The vertical interconnections are
`
`ELM EX_00000004
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`Case 1: 14--cv- 01432- LPS Document 238-2 Filed 12/12/19 Page 6 of 14 PagelD #: 16090
`IEEE TRANSACTIONS ON COMPONENTS, PACKAGING, AND MANUFACTURING TECHNOLOGY“PART 8 VOL. 21, NO FEBRUARY 1998
`
`Conductors
`
`Ceramic
`
`
`
`
`Solder Joint
`Ceramic
`V 1a
`/
`Interconnect
`Pad
`
`
`Adhesive
`Spacer
`
`
`
`(a)
`
`(M
`
`Pad
`
`Tape carrier lend
`lape Larrler
`Through imle
`Solder juml
`
`PCB Tram?
`
`PCB
`
`
`
`
`
`
`
`Fig. 6. Three variants of the solder edge conductors vertical interconnections: (a) solder edge contacts, (b) solder filled Via, and (c) stacked PCB leadirames.
`
`(C)
`
`
`Fig. 9. Direct laser writing process for vertical interconnections.
`
`Wire cross
`section
`
`Laser made kerf
`
`Conductor
`
`Fig. 7. A photograph of an edge array with solder balls fabricated at MCNC.
`
`Adhesive
`
`Lead
`Pmiv'd'iu"
`
`T—mnneet
`
`
`
`
`
`(Cross section)
`
`
`
`(Side View)
`
`Fig. 8. Thin film metal “T—connccts" for vertical interconnections.
`
`achieved by rerouting the memory chip I/Os for TAB
`bonding. Then, a group of four to 16 of these chips
`is laminated to form the 3-D stack. These stacks are
`
`placed on a silicon substrate and aligned such that the
`TAB leads 0“ the bottom 01° the stack contact the solder
`bumped pads on the substrate as shown in Fig. 10.
`b) A flip-Chip bonded to faces ofthe stack: In this method,
`before MCM’S are stacked their interconnection leads
`
`to the side to a metallic pad. Then an
`are brought
`IC is bonded to these metallic pads using [lip-chip
`technology as shown in Fig. 11. This approach was
`used by Grumman Aerospace corporation to develop
`surveillance technology for military applications [38],
`[39].
`C) PC boards soldered on two sides 9f TSOP packages. In
`this approach, two PCB’s arc soldered on two sides of
`stacked TSOP packages to perform the vertical intercon—
`nections. Then, the PCB leads are configured to form a
`dual
`in line package (DIP) as shown in Fig. 12. This
`
`ELM EX_00000005
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`Case 1:14-cv-01432-LPS Document 238-2 Filed 12/12/19 Page 7 of 14 PagelD #: 160917
`AL-SARAWl at 51].: REVIEW OF 3»D PACKAGING TECHNOLOGY
`
`3D Memory Modules
`
`,.
`
`‘
`
`,
`
`.
`
`TAB leads
`
`Substrate
`
`\
`
`Solder bumps
`
`
`
`
`
`Fig. l0. Texas Instruments array TAB leads soldered to bumps on a silicon
`substrate.
`
`Pad
`
`50‘6" bump
`
`Interconnect
`
`
`
`2 _—__.—
`
`vuucal
`lnlvnunnection
`
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`Device
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`E.
`
`
`Schematic diagram showing how IC’s are stacked and intercon—
`l3.
`Fig.
`nected using a flex type material.
`
`Substrate
`
`ICs
`
`.Wire bond
`Pad
`
`A
`
`A
`Fig. ll. Vertical interconncction method where a chip is flip bonded to the
`Slde of the stacked MCM’S.
`
`.
`
`“I 33"“?
`------.v;.;.;.;+;3;,.
`.m.
`44444444‘A33 ‘3‘
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`Fig, 14. Vertical interconnection approach using wire bonding techniques.
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`Film
`
`(b)
`
`'I‘Util’s
`
`(a)
`
`(a) Schematic diagram of a PCB solder to TSOP’S and (b) a cross
`Fig. 12.
`sectional View of the upper schematic
`
`(b)
`(a) Schematic diagram of two chips stacked and interconnected
`Fig. 15.
`using wire bonding and (b) a top View of the upper schematic diagram.
`
`method is used by Mitsubishi in designing high density
`memories [40].
`In the folded flex circuits, bare
`5) Folded Flex Circuits:
`dice are mounted and interconnected on a flex type material,
`then folded {0' form a 3-D stack [41] 35 shown in Fig. 13-
`This method 175
`reported by General ElectriC, Harris, and
`MicroModule Systems.
`’
`.
`6) Wire Bonded Stacked Chips: The “Wire bonded stacked
`chips” method uses a wire bonding technique for the vertical
`interconnections. There are two variants for this approach:
`3' Area Interconnection Between Stacked [CS
`a) Wire bonded to an MCM substrate directly:
`In this
`An area interconnection is a method where vertical inter-
`approach, stacked chips are wire bonded to a planar
`connections are not bonded to the periphery of the stacked
`MCM substrate using wire bonding technology as shown
`elements, as will be illustrated by the following variant of this
`in Fig. 14. This approach was used by Matra Marconi
`Space for a high density solid state recorder [42] and by method.
`
`”Chip in the design of high density memory modules
`[43]
`h) Wire bonded to a substrate through an 1C: In this ap—
`preach,
`there is a mother and a daughter chip. The
`mother chip will act as a substrate for the daughter
`chip, where interconnections from the daughter chip go
`to pads on the surface of the mother chip substrate as
`shown in Fig. 15. Voltonic USA has used this technology
`in some medical applications [44].
`
`ELM EX_00000006
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`

`Case 1:14-cv-01432-LPS Document 238-2 Filed 12/12/19 Page 8 of 14 PageID #: 16092
`Cgase 1: 14--cv-01432- LPS Document 238-2 Filed 12/12/19 Page 8 of 14 PagelD #: 16092
`FEBRUARY 1998
`IEEE TRANSACTIONS ON COMPONENTS, PACKAGING, AND MANUFACTURlNG TECHNOLOGY“PART 8 VOL. 21, NO
`
`‘ LSI Chm
`Glass
`
`Ferroelectric liquid crystal (FLC)
`
`
`
`
`Large concave
`solder joint
`
`Substrate
`
`Small convex
`solder joint
`
`Fig. lo.
`
`Schematic diagram oftwo chips stacked using flip-chip technology.
`
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`m rm prm" n 1;»
`
`1C or MCM
`
`
`
`
`
`l 7.
`Fi g.
`method.
`
`Schematic diagram of Hughes microspring vertical
`
`interconnect
`
`I) Flip—Chip Bonded Stacked Chips Without Spacers." In this
`approach the stacked IC’s are flipped and interconnected
`to either a substrate or another chip using the solder joint
`technology. This technique was used by many companies,
`some of these companies are IBM company in the design
`of ultra-high-density components [45], Fujitsu for stacking a
`GaAs chip on a CMOS chip technology [46] and Matsushita
`which developed a new “micro—bump bonding method” [47]
`and used by Semiconductor Research Center, Osaka, Japan,
`for thermal heads and an LED printer head [48].
`2) Flip Chip Bonded Stacked Chips Wth Space/s. This ap—
`proachis similar to the above approach except that spacers are
`used to control the distance between the stacked chips. This
`technique was developed and used by University of Colorado,
`Boulder, and University of Califomia, San Diego, to fix a glass
`plate containing a ferroeleetric liquid crystal on the top of the
`VLSI chip [49]. [50] as shown in Fig. 16.
`3) Microbridge Springs
`and Thermomigration Vias:
`Microbridge springs method involves the use of microsprings
`to achieve the vertical interconnections between stacked lC’s,
`as shown in Fig. 17. This method was developed and used
`by Hughes in the design of 3—D parallel computers for real
`time data and image processing and avionics for F-l4, F-lS,
`F/A-lS, AV-SB, and B-2 aircrafts [51]. The same technique
`can be used for MCM’s and is also relevant to the methods
`
`presented in Section III-D1.
`
`C. Periphery Interconnection Between Stacked MCMS
`This is a method where vertical interconnections between
`
`stacked MCM’s are realized on the stacks periphery. There
`are three main variants of this method as follows.
`
`Lid
`
`
`
`interconnection
`Fig, 18, A soldered leads on stacked MCM’s vertical
`method, which is a variant of the solder edge conductors method discussed
`in Section lll‘AZ.
`
`I) Solder Edge Conductors: This is similar to the solder
`edge conductor for lC’s, discussed in Section ill-AZ. How-
`ever, in this case the vertical interconnections are performed
`between MCM’s rather than lC’s. There are two variants of
`this method.
`
`a) Solder dipped stacks to create vertical conductors on
`edge: This technique is similar to the solder dipped
`stacks to create the ‘vertical conductors on edge’ tech-
`nique discussed in Section Ill-A2 with the exception that
`MCM’s are used to form the stack. This technique was
`used by Trymer in the development of a guidance system
`for hypervelocity projectiles {52], [53].
`b) Solder leads on stacked MCMs: After each MCM is
`packaged separately they are stacked with the leads
`formed to allow stacking as shown in Fig. 18,
`then
`soldered for permanent mounting. Matsushita Electronic
`Components has used this method in the design of
`high density SRAM’s and DRAM’s by using 2—8 layer
`stack. This method is referred to as ‘Staeked QFP—
`format MCMs’ because the leads on the bottom board
`
`are formed as a quad-flat pack package [54].
`2) Thin Film Conductors on Face-ofla-Cube:
`a) HDl-thin film intercmmeet laminated to side of stack:
`The vertical interconnects are realized along the sides
`of the stack using the same high density intercon-
`nect (HDI) process used in the substrate. The sides
`are laminated then patterned using a chemical process
`called “electroplated photoresist.” A schematic diagram
`of this method is shown in Fig. 19. This technique was
`developed and used by General Electric in the design
`of high density memories and other application specific
`integrated circuits (ASIC’s) [55], [56].
`b) Direct
`laser write traces on epoxy cube face: This
`method of interconnection is similar to the one discussed
`
`in Section Ill—A3 except that MCM’s are used in the
`stack instead of lC’s. Thomson-CPS is the company
`who developed this technology for both MCM and IC
`stacking and called it “MCM-V.”
`In this approach a
`3) Blind Castellation Interconnection:
`semicircular or crown—shaped metallised surface (Castellation)
`is used for making vertical
`interconnections between the
`stacked MCM’s as shown in Fig. 20. This method was used by
`
`ELM EX_00000007
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`

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`Case 1:14-cv-01432-LPS Document 238-2
`Filed 12/12/19 Page 9 of 14 PageID #: 160939
`AL-SARAWI at 51].: REVIEW OF 3»D PACKAGING TECHNOLOGY
`
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`Fig. 19,
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`Via
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`Fig. 20.
`method and (b) a schematic diagram of three MCM’s stacked using the blind
`castellation method.
`
`Harris and CTS Microelectronics in the design of high density
`memory modules [57], [58], [59].
`4) Wire Bonded Stacked MCMs: This approach is similar
`to the wire bonded stacked chips technique discussed in
`Section lIl«A6, except MCM-Ds are used in the stack. This
`approach was developed and used by CENG for designing a
`1 Gb mass memory module [60].
`elas-
`uses
`approach
`5) Elostomeric Connectors: This
`stacked
`tromeric
`connectors1
`to vertically interconnect
`MCM’s Such approach is currently employed by the Jet
`
`‘ An