Case 1:14-cv-01432-LPS Document 238-12 Filed 12/12/19 Page 1 of 85 PageID #: 16268
`
`Exhibit L
`
`

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`Case 1:14-cv-01432-LPS Document 238-12 Filed 12/12/19 Page 2 of 85 PageID #: 16269
`
`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`12/268,386
`
`11-10-2008
`
`Utility
`CHIU, TSZK
`2822
`8139
`
`E081110.3DS.US
`257/347
`Glenn J. Leedy,
`Parkland, FL (US)
`
`Application
`Number:
`Filing or 371 (c)
`Date:
`Application
`Type:
`Examiner Name:
`Group Art Unit:
`Confirmation
`Number:
`Attorney Docket
`Number:
`Class/ Subclass:
`First Named
`Inventor:
`First Named
`Applicant:
`
`Entity Status:
`
`Small
`
`AIA (First
`Inventor to File):
`
`No
`
`Correspondence
`Address Customer 30232
`Number:
`Status:
`
`Patented Case
`
`09-23-2015
`ELECTRONIC
`us 2009-0067210
`Al
`03-12-2009
`
`Status Date:
`
`Location:
`Location Date:
`Earliest
`Publication No:
`Earliest
`Publication Date:
`Patent Number:
`Issue Date of
`Patent:
`International
`Registration
`Number (Hague):
`International
`Registration
`Publication Date:
`
`Title of Invention:
`
`THREE DIMENSIONAL STRUCTURE MEMORY
`
`AMENDMENT
`
`Sir:
`
`Please amend the claims as follows:
`
`1
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`

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`Case 1:14-cv-01432-LPS Document 238-12 Filed 12/12/19 Page 3 of 85 PageID #: 16270
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`Amendments of the Claims
`This listing of claims will replace all prior versions and listings of claims in the
`application:
`
`Listing of Claims
`
`1-87. (canceled)
`88. (Currently amended) A stacked integrated circuit memory comprising:
`at least one logic integrated circuit, wherein the at least one logic integrated
`circuit is one of: a thin substantially flexible integrated circuit, and capable of forming a
`thin substantially flexible integrated circuit;
`at least one thin substantially flexible memory integrated circuit positioned in a
`stacked relation to said at least one logic integrated circuit; and
`interconnections electrically connecting the at least one logic integrated circuit
`and the at least one thin substantially flexible memory integrated circuit;
`wherein at least one of the at least one logic integrated circuit and the at least one
`thin substantially flexible memory integrated circuit comprises a monocrystalline
`semiconductor substrate of one piece,; and
`wherein the at least one of the at least one logic integrated circuit and the at least
`one thin substantially flexible memory integrated circuit has formed thereon a lov,r stress
`silieoR based dieleetrie layer haviRg a stress of less thaa 5 Jr 1 O& dyaes/em:± teRsile
`plurality of dielectric layers having a combined thickness and including one or more
`
`2
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`silicon-based dielectric layers that are flexible, the one or more dielectric layers that are
`flexible comprising a majority of the combined thickness.
`
`89. (Currently amended) The stacked integrated circuit memory of claim 88, wherein the
`interconnections electrically connecting the at least one logic integrated circuit and the at
`least one thin substantially flexible memory integrated circuit are vertical
`interconnections internal to the stacked integrated circuit memory; and wherein the one or
`more silicon-based dielectric layers that are flexible have a stress of less than 5 x 108
`dynes/cm2 tensile.
`
`90. (Currently amended) The stacked integrated circuit memory of claim 88 claim 89,
`wherein at least one of the logic integrated circuit and the at least one thin substantially
`flexible memory integrated circuit comprises one of a single crystal semiconductor
`material and polysilicon semiconductor material.
`
`91. ( Currently amended) The stacked integrated circuit memory of claim 8 8 claim 8 9,
`wherein at least one of the at least one logic integrated circuit and the at least one thin
`substantially flexible memory integrated circuit have a thickness of less than about 50
`microns.
`
`92. (Currently amended) The stacked integrated circuit memory of claim 88 claim 89,
`wherein at least one of the at least one logic integrated circuit and the at least one thin
`
`3
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`substantially flexible memory integrated circuit have a thickness of less than about 10
`microns.
`
`93. (Currently amended) The stacked integrated circuit memory of claim 88 claim 89,
`wherein the at least one thin substantially flexible memory integrated circuit has a
`different process technology from the at least one logic integrated circuit.
`
`94. (Previously presented) The stacked integrated circuit memory of claim 93, wherein
`the different process technology is one of DRAM, SRAM, FLASH, EEPROM, EPROM,
`Ferroelectric and Giant Magneto Resistance.
`
`95. (Currently amended) The stacked integrated circuit memory of claim 88 claim 89,
`wherein at least one of the at least one logic integrated circuit and the at least one thin
`substantially flexible memory integrated circuit comprise active circuit devices and
`passive circuit devices.
`
`96. (Currently amended) The stacked integrated circuit memory of claim 88 claim 89,
`wherein the at least one logic integrated circuit comprises at least two logic integrated
`circuits, wherein a plurality of data bytes are transferred between the logic integrated
`circuits with at least some of the interconnections.
`
`4
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`97. (Currently amended) The stacked integrated circuit memory of claim 88 claim 89,
`further comprising at least one of a microprocessor, a graphics processor, a power
`management control circuitry and a content-addressable memory circuitry.
`
`98. (Currently amended) The stacked integrated circuit memory of claim 88 claim 89,
`wherein the at least one logic integrated circuit performs at least one data function,
`wherein the data function is one of audio encoding, audio decoding, video encoding,
`video decoding, voice recognition, handwriting recognition, ECC, logical to real address
`translation, graphical processing and database management processing.
`
`99. (Currently amended) The stacked integrated circuit memory of claim 88 claim 89,
`wherein the at least one thin substantially flexible memory integrated circuit comprises:
`a plurality of data lines;
`a plurality of gate lines;
`an array of memory cells, each memory cell storing a data value and comprising
`circuitry for coupling that data value to a corresponding data line of said data lines in
`response to the selection of a corresponding gate line of said gate lines; and
`wherein the at least one logic integrated circuit comprises:
`gate line selection logic for selecting gate lines for memory operations, said gate
`line selection logic comprising programmable gates to receive programmed address
`assignments for said gate lines, each programmed address assignment for determining
`which of the gate lines is to be selected; and
`
`5
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`

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`test logic for at least one of determining whether there are any defective memory
`cells of said memory cells and reconfiguring the programmed address assignments to
`eliminate references to the corresponding gate lines for the defective memory cells and
`determining whether there are any defective gate lines of the gate lines and reconfiguring
`the programmed address assignments to eliminate references to the defective gate lines.
`
`100. (Previously presented) The stacked integrated circuit memory of claim 99, wherein
`the test logic tests periodically to determine at least one of whether there any defective
`memory cells of the memory cells and whether there are any defective gate lines of the
`gate lines.
`
`101. (Previously presented) The stacked integrated circuit memory of claim 99, wherein
`the at least one logic integrated circuit comprises programmable logic to prevent the use
`of data values from the corresponding data lines for said defective memory cells.
`
`102. (Previously presented) The stacked integrated circuit memory of claim 99, wherein
`said memory cells are arranged within physical space in a physical order and are arranged
`within an address space in a logical order, wherein said physical order of at least one
`memory cell is different than the logical order of the at least one memory cell.
`
`103. (Previously presented) The stacked integrated circuit memory of claim 100, wherein
`testing of the at least one logic integrated circuit together with the testing by the test logic
`
`6
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`achieves functional testing of the at least one logic integrated circuit and at least one of
`the memory cells and the gate lines.
`
`104. (Previously presented) The stacked integrated circuit memory of claim 100, wherein
`the testing by the test logic substantially reduces or eliminates the need for external
`testing of at least one of the memory cells and the gate lines.
`
`105. (Previously presented) The stacked integrated circuit memory of claim 99, wherein
`the reconfiguring programmed address assignments comprises at least one of replacing
`references to the corresponding gate lines for the defective memory cells with references
`to the corresponding gate lines for spare memory cells of the memory cells and replacing
`references to the defective gate lines with references to spare gate lines of the gate lines.
`
`106. (Previously presented) The stacked integrated circuit memory of claim 99, wherein
`the reconfiguring programmed address assignments comprises at least one of preventing
`the use of the corresponding gate lines for the defective memory cells without
`replacement and preventing the use of the defective gate lines without replacement,
`thereby reducing the amount of available memory storage of the stacked integrated circuit
`memory.
`
`107. (Currently amended) A stacked integrated circuit memory comprising:
`a logic layer, wherein the logic layer is one of: a thin substantially flexible layer,
`and capable of forming a thin substantially flexible layer;
`
`7
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`Case 1:14-cv-01432-LPS Document 238-12 Filed 12/12/19 Page 9 of 85 PageID #: 16276
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`at least one thin substantially flexible memory layer that is at least one of formed
`overlying the logic layer and bonded in a stacked relationship to the logic layer; and
`a plurality of connections internal to the stacked integrated circuit for transferring
`a plurality of data bytes between the logic layer and the at least one thin substantially
`flexible memory layer;
`wherein at least one of the logic layer and the at least one thin substantially
`flexible memory layer comprises a monocrystalline semiconductor substrate of one piece,
`and wherein the at least one of the logic layer and the at least one thin substantially
`flexible memory layer has formed thereon a lmv stress silicon based dielectric layer
`having a stress of less than 5 Jc 1 0& dynes/em;i. tensile plurality of dielectric layers having
`a combined thickness and including one or more silicon-based dielectric layers that are
`flexible, the one or more dielectric layers that are flexible comprising a majority of the
`combined thickness.
`
`108. (Currently amended) The stacked integrated circuit memory of claim 107, wherein
`the connections electrically connecting the logic layer and the at least one thin
`substantially flexible memory layer are vertical interconnections internal to the stacked
`integrated circuit, and wherein the one or more silicon-based dielectric layers that are
`flexible have a stress of less than 5 x 108 dynes/cm2 tensile.
`
`109. (Currently amended) The stacked integrated circuit memory of claim 107 claim 108,
`wherein at least one of the logic layer and the at least one thin substantially flexible
`
`8
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`

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`memory layer comprises one of a single crystal semiconductor material and polysilicon
`semiconductor material.
`
`110. (Currently amended) The stacked integrated circuit memory of claim 107 claim 108,
`wherein at least one of the logic layer and the at least one thin substantially flexible
`memory layer have a thickness of less than about 50 microns.
`
`111. (Currently amended) The stacked integrated circuit memory of claim 107 claim 108,
`wherein at least one of the logic layer and the at least one thin substantially flexible
`memory layer have a thickness of less than about 10 microns.
`
`112. (Currently amended) The stacked integrated circuit memory of claim 107 claim 108,
`wherein the at least one thin substantially flexible memory layer has a different process
`technology from the logic layer.
`
`113. (Previously presented) The stacked integrated circuit memory of claim 112, wherein
`the different process technology is one of DRAM, SRAM, FLASH, EEPROM, EPROM,
`Ferroelectric and Giant Magneto Resistance.
`
`114. (Currently amended) The stacked integrated circuit memory of elaim 107 claim 108,
`wherein the logic layer and the at least one thin substantially flexible memory layer
`comprise at least one of active circuit devices and passive circuit devices.
`
`9
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`Case 1:14-cv-01432-LPS Document 238-12 Filed 12/12/19 Page 11 of 85 PageID #: 16278
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`115. (Currently amended) The stacked integrated circuit memory of claim 107 claim 108,
`further comprising at least one of a microprocessor, a graphics processor, a power
`management control circuitry and a content-addressable memory circuitry.
`
`116. (Currently amended) The stacked integrated circuit memory of claim 107 claim 108,
`wherein the logic layer performs at least one data function, wherein the data function is
`one of audio encoding, audio decoding, video encoding, video decoding, voice
`recognition, handwriting recognition, ECC, logical to real address translation, graphical
`processing and database management processing.
`
`117. (Currently amended) The stacked integrated circuit memory of claim 107 claim 108,
`wherein the at least one thin substantially flexible memory layer:
`a plurality of data lines;
`a plurality of gate lines;
`an array of memory cells, each memory cell storing a data value and comprising
`circuitry for coupling that data value to a corresponding date line of said data lines in
`response to the selection of a corresponding gate line of said gate lines; and
`wherein the logic layer comprises:
`gate line selection logic for selecting gate lines for memory operations, said gate
`line selection logic comprising programmable gates to receive programmed address
`assignments for said gate lines, each programmed address assignment for determining
`which of said gate lines is to be selected; and
`
`10
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`

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`a test logic for at least one of determining whether there are any defective
`memory cells of said memory cells and reconfiguring the programmed address
`assignments to eliminate references to the corresponding gate lines for the defective
`memory cells and determining whether there are any defective gate lines of the gate lines
`and reconfiguring the programmed address assignments to eliminate references to the
`defective gate lines.
`
`118. (Previously presented) The stacked integrated circuit memory of claim 117, wherein
`the test logic tests periodically to determine at least one of whether there are any
`defective memory cells of said memory cells and whether there are any defective gate
`lines of the gate lines.
`
`119. (Previously presented) The stacked integrated circuit memory of claim 117, wherein
`the logic layer comprises programmable logic to prevent the use of data values from the
`corresponding data lines for the defective memory cells.
`
`120. (Previously presented) The stacked integrated circuit memory of claim 117, wherein
`said memory cells are arranged within physical space in a physical order and are arranged
`within an address space in a logical order, wherein said physical order of at least one
`memory cell is different than the logical order of the at least one memory cell.
`
`11
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`Case 1:14-cv-01432-LPS Document 238-12 Filed 12/12/19 Page 13 of 85 PageID #: 16280
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`121. (Previously presented) The stacked integrated circuit memory of claim 118, wherein
`testing of the logic layer together with the testing by the test logic achieves functional
`testing of the logic layer and at least one of the memory cells and the gate lines.
`
`122. (Previously presented) The stacked integrated circuit memory of claim 118, wherein
`the testing by the test logic substantially reduces or eliminates the need for external
`testing of at least one of the memory cells and the gate lines.
`
`123. (Previously presented) The stacked integrated circuit memory of claim 117, wherein
`the reconfiguring of the programmed address assignments comprises at least one of
`replacing references to the corresponding gate lines for the defective memory cells with
`references to the corresponding gate lines for spare memory cells of the memory cells and
`replacing references to the defective gate lines with references to spare gate lines of the
`gate lines.
`
`124. (Previously presented) The stacked integrated circuit memory of claim 117, wherein
`the reconfiguring of the programmed address assignments comprises at least one of
`preventing the use of the corresponding gate lines for the defective memory cells without
`replacement and preventing the use of the defective gate lines without replacement,
`thereby reducing the amount of available memory storage of the array of memory.
`
`125.- 181. (Canceled)
`
`12
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`Case 1:14-cv-01432-LPS Document 238-12 Filed 12/12/19 Page 14 of 85 PageID #: 16281
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`182. (Currently amended) The stacked integrated circuit memory of claim gg claim 89,
`wherein the vertical interconnections pass through holes in said monocrystalline
`semiconductor substrate, wherein each vertical interconnection comprises within the hole
`a conductive center portion and an insulating portion surrounding the center portion, the
`insulating portion comprising a dielectric having a stress ofless than 5 x 108 dynes/cm2
`tensile.
`
`183. (Currently amended) The stacked integrated circuit memory of claim 107 claim 108,
`wherein the connections pass through holes in said monocrystalline semiconductor
`substrate, wherein each connection comprises within the hole a conductive center portion
`and an insulating portion surrounding the center portion, the insulating portion
`comprising a dielectric having a stress ofless than 5 x 108 dynes/cm2 tensile.
`
`184. (Currently amended) The stacked integrated circuit memory of elaim gg claim 89,
`wherein the at least one thin substantially flexible memory integrated circuit comprises
`the monocrystalline semiconductor substrate, the monocrystalline semiconductor
`substrate is thinned and substantially flexible and has a first surface and a second surface,
`only one of said first and second surfaces having semiconductor devices formed thereon,
`and another one of said first and second surfaces is polished or smoothed after the surface
`is exposed from thinning of the monocrystalline semiconductor substrate.
`
`185. (Currently amended) The stacked integrated circuit memory of elaim 107 claim 108,
`wherein the at least one thin substantially flexible memory layer comprises the
`
`13
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`monocrystalline semiconductor substrate, the monocrystalline semiconductor substrate is
`thinned and substantially flexible and has a first surface and a second surface, only one of
`said first and second surfaces having semiconductor devices formed thereon, and another
`one of said first and second surfaces is polished or smoothed after the surface is exposed
`from thinning of the monocrystalline semiconductor substrate.
`
`186. (Currently amended) The stacked integrated circuit memory of claim gg claim 89,
`wherein at least two of the following: the interconnections electrically connecting the at
`least one logic integrated circuit and the at least one thin substantially flexible memory
`integrated circuit are vertical interconnections internal to the stacked integrated circuit; at
`least one of the at least one logic integrated circuit and the at least one thin substantially
`flexible memory integrated circuit comprise one of a single crystal semiconductor
`material and polysilicon semiconductor material.; at least one of the at least one logic
`integrated circuit and the at least one thin substantially flexible memory integrated circuit
`has a thickness of less than about 50 microns; at least one of the at least one logic
`integrated circuit and the at least one thin substantially flexible memory integrated circuit
`has a thickness of less than about 10 microns; the at least one thin substantially flexible
`memory integrated circuit has a different process technology from the at least one logic
`integrated circuit, wherein the different process technology is one of DRAM, SRAM,
`FLASH, EEPROM, EPROM, Ferroelectric and Giant Magneto Resistance; at least one of
`the at least one logic integrated circuit and the at least one thin substantially flexible
`memory integrated circuit comprise active circuit devices and passive circuit devices; the
`at least one thin substantially flexible memory integrated circuit comprises a
`
`14
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`monocrystalline semiconductor substrate having a first surface and a second surface, only
`one of said first and second surfaces having semiconductor devices formed thereon,
`wherein another one of said first and second surfaces is polished; at least one of the at
`least one logic integrated circuit and the thin substantially flexible memory integrated
`circuit is formed from a semiconductor wafer; at least one of the at least one logic
`integrated circuit and the at least one thin substantially flexible memory integrated circuit
`is thinned by at least one of abrasion, etching and parting, and subsequently polished to
`form a polished surface; a plurality of polysilicon layers are provided with at least one
`low stress silicon-based dielectric layer deposited on each of said polysilicon layers in a
`stacked relationship to at least one of the at least one logic integrated circuit and the at
`least one thin substantially flexible memory integrated circuit; a plurality of integrated
`circuits are provided in a stacked relationship each of said plurality of integrated circuits
`comprising a polysilicon substrate and at least one low stress silicon-based dielectric
`layer; a plurality of integrated circuits are provided in a stacked relationship each of said
`plurality of integrated circuits comprising a deposited polysilicon layer and at least one
`low stress silicon-based dielectric layer; the at least one logic integrated circuit performs
`testing of the at least one thin substantially flexible memory integrated circuit; at least
`one of the at least one logic integrated circuit and the at least one thin substantially
`flexible memory integrated circuit comprises reconfiguration circuitry; the at least one
`thin substantially flexible memory integrated circuit comprises a substantially flexible
`semiconductor substrate, at least one conductive interconnection passing vertically
`through the substantially flexible semiconductor substrate and being insulated from the
`substantially flexible semiconductor substrate by a low stress silicon-based dielectric
`
`15
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`material having a stress ofless than 5 x 108 dynes/cm2 tensile; at least a portion of the
`stacked integrated circuit memory is partitioned into a plurality of block stacks each with
`vertically interconnected circuit blocks, wherein a plurality of said block stacks are
`configured to independently perform memory operations; at least one of the at least one
`logic integrated circuit and the at least one thin substantially flexible mern01y integrated
`circuit comprises a first side and a second side opposite the first side, further comprising
`integrated circuitry formed on the first side and interconnections for at least a portion of
`the integrated circuitry formed 011 the second side.
`
`187. (Currently amended) The stacked integrated circuit memory of claim gg claim 89,
`wherein at least three of the following: the interconnections electrically connecting the at
`least one logic integrated circuit and the at least one thin substantially flexible memory
`integrated circuit are vertical interconnections internal to the stacked integrated circuit; at
`least one of the at least one logic integrated circuit and the at least one thin substantially
`flexible memory integrated circuit comprise one of a single crystal semiconductor
`material and polysilicon semiconductor material; at least one of the at least one logic
`integrated circuit and the at least one thin substantially flexible memory integrated circuit
`has a thickness of less than about 50 microns; at least one of the at least one logic
`integrated circuit and the at least one thin substantially flexible memory integrated circuit
`has a thickness of less than about 10 microns; the at least one thin substantially flexible
`memory integrated circuit has a different process technology from the at least one logic
`integrated circuit, wherein the different process technology is one of DRAM, SRAM,
`FLASH, EEPROM, EPROM, Ferroelectric and Giant Magneto Resistance; at least one of
`
`16
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`the at least one logic integrated circuit and the at least one thin substantially flexible
`memory integrated circuit comprise active circuit devices and passive circuit devices; the
`at least one thin substantially flexible memory integrated circuit comprises a
`monocrystalline semiconductor substrate having a first surface and a second surface, only
`one of said first and second surfaces having semiconductor devices formed thereon,
`wherein another one of said first and second surfaces is polished; at least one of the at
`least one logic integrated circuit and the thin substantially flexible memory integrated
`circuit is formed from a semiconductor wafer; at least one of the at least one logic
`integrated circuit and the at least one thin substantially flexible memory integrated circuit
`is thinned by at least one of abrasion, etching and parting, and subsequently polished to
`fixrn a polished surface; a plurality of polysilicon layers are provided with at least one
`low stress silicon-based dielectric layer deposited on each of said polysilicon layers in a
`stacked relationship to at least one of the at least one logic integrated circuit and the at
`least one thin substantially flexible memory integrated circuit; a plurality of integrated
`circuits are provided in a stacked relationship each of said plurality of integrated circuits
`comprising a polysilicon substrate and at least one low stress silicon-based dielectric
`layer; a plurality of integrated circuits are provided in a stacked relationship each of said
`plurality of integrated circuits comprising a deposited polysilicon layer and at least one
`low stress silicon-based dielectric layer; the at least one logic integrated circuit performs
`testing of the at least one thin substantially flexible memory integrated circuit; at least
`one of the at least one logic integrated circuit and the at least one thin substantially
`flexible memory integrated circuit comprises reconfiguration circuitry; the at least one
`thin substantially flexible memory integrated circuit comprises a substantially flexible
`
`17
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`semiconductor substrate, at least one conductive interconnection passing vertically
`through the substantially flexible semiconductor substrate and being insulated from the
`substantially flexible semiconductor substrate by a low stress silicon-based dielectric
`material having a stress ofless than 5 x 108 dynes/cm2 tensile; at least a portion of the
`stacked integrated circuit memory is partitioned into a plurality of block stacks each with
`vertically interconnected circuit blocks, wherein a plurality of said block stacks are
`configured to independently perform memory operations.
`
`188. (Currently amended) The stacked integrated circuit memory of claim gg claim 89,
`further comprising at least two of the following: at least two logic integrated circuits,
`wherein a plurality of data bytes are transferred between the logic integrated circuits; at
`least one of a microprocessor, a graphics processor, a power management control
`circuitry and a content-addressable memory circuitry; at least one data function, wherein
`the data function is one of audio encoding, audio decoding, video encoding, video
`decoding, voice recognition, handwriting recognition, ECC, logical to real address
`translation, graphical processing and database management processing; at least one
`vertical interconnect that passes through said monocrystalline semiconductor substrate,
`wherein the vertical interconnect comprises a conductive center portion and an insulating
`portion surrounding the center portion, the insulating portion comprising a dielectric
`having a stress ofless than 5 x 108 dynes/cm2 tensile.
`
`18
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`189. (Currently amended) The stacked integrated circuit memory of claim gg claim 89,
`further comprising at least three of the following: at least two logic integrated circuits,
`wherein a plurality of data bytes are transferred between the logic integrated circuits; at
`least one of a microprocessor, a graphics processor, a power management control
`circuitry and a content-addressable memory circuitry; at least one data function, wherein
`the data function is one of audio encoding, audio decoding, video encoding, video
`decoding, voice recognition, handwriting recognition, ECC, logical to real address
`translation, graphical processing and database management processing; at least one
`vertical interconnect that passes through said monocrystalline semiconductor substrate,
`wherein the vertical interconnect comprises a conductive center portion and an insulating
`portion surrounding the center portion, the insulating portion comprising a dielectric
`having a stress ofless than 5 x 108 dynes/cm2 tensile.
`
`190. (Currently amended) The stacked integrated circuit memory of elaim 107 claim 108,
`wherein at least two of the following: the interconnections electrically connecting the
`logic layer and the at least one thin substantially flexible memory layer are vertical
`interconnections internal to the stacked integrated circuit; the logic layer and the at least
`one thin substantially flexible memory layer comprise one of a single crystal
`semiconductor material and polysilicon semiconductor material; at least one of the logic
`layer and the at least one thin substantially flexible memory layer has a thickness of less
`than about 50 microns; at least one of the logic layer and the at least one thin
`substantially flexible memory layer has a thickness of less than about 10 microns; the at
`least one thin substantially flexible memory layer has a different process technology from
`
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`the logic layer, wherein the different process technology is one of DRAM, SRAM,
`FLASH, EEPROM, EPROM, Ferroelectric and Giant Magneto Resistance; the logic
`layer and the at least one thin substantially flexible memory layer comprise at least one of
`active circuit devices and passive circuit devices; the at least one thin substantially
`flexible memory layer comprises a monocrystalline semiconductor substrate having a
`first surface and a second surface, only one of said first and second surfaces having
`semiconductor devices formed thereon, wherein another one of said first and second
`surfaces is polished; at least one of the logic layer and the thin substantially flexible
`memory layer is formed from a semiconductor wafer; at least one of the logic layer and
`the at least one thin substantially flexible memory layer is thinned by at least one of
`abrasion, etching and parting, and subsequently polished to fonn a polished surface; a
`plur