Case 1:14-cv-01432-LPS Document 237 Filed 12/12/19 Page 1 of 288 PageID #: 15733
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`IN THE UNITED STATES DISTRICT COURT
`FOR THE DISTRICT OF DELAWARE
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`ELM 3DS INNOVATIONS, LLC,
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`PLAINTIFF,
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`MICRON TECHNOLOGY, INC.; MICRON
`SEMICONDUCTOR PRODUCTS, INC.; AND
`MICRON CONSUMER PRODUCTS
`GROUP, INC.,
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`V.
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`DEFENDANTS.
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`V.
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`ELM 3DS INNOVATIONS, LLC,
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`PLAINTIFF,
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`SAMSUNG ELECTRONICS CO., LTD.,
`SAMSUNG SEMICONDUCTOR, INC.,
`SAMSUNG ELECTRONICS AMERICA, INC.,
`AND SAMSUNG AUSTIN
`SEMICONDUCTOR, LLC,
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`DEFENDANTS.
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`V.
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`ELM 3DS INNOVATIONS, LLC,
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`PLAINTIFF,
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`SK HYNIX INC., SK HYNIX AMERICA INC.,
`HYNIX SEMICONDUCTOR
`MANUFACTURING AMERICA INC., AND
`SK HYNIX MEMORY SOLUTIONS INC.,
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`DEFENDANTS.
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`C.A. NO. 14-01431-LPS-CJB
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`JURY TRIAL DEMANDED
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`C.A. NO. 14-01430-LPS-CJB
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`JURY TRIAL DEMANDED
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`C.A. NO. 14-01432-LPS-CJB
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`JURY TRIAL DEMANDED
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`DECLARATION OF JOHN KAPPOS IN SUPPORT OF DEFENDANTS’ CLAIM
`CONSTRUCTION BRIEF
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`Case 1:14-cv-01432-LPS Document 237 Filed 12/12/19 Page 2 of 288 PageID #: 15734
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`I, John Kappos, hereby declare the following:
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`1.
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`I am a partner with the law firm of O’Melveny & Myers and am admitted to
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`practice pro hac vice before this Court. I submit this declaration in support of the Defendants’
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`Claim Construction Brief. The facts set forth in this declaration are known to me personally. If
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`called as a witness, I could and would testify competently concerning these matters.
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`2.
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`Attached hereto as Exhibit A is a true and correct copy of the Declaration of
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`Richard B. Fair Regarding Claim Construction, dated January 17, 2019.
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`3.
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`Attached hereto as Exhibit B is a true and correct copy of the Responsive
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`Declaration of Dr. Richard B. Fair Regarding Claim Construction, dated February 1, 2019.
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`4.
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`Attached hereto as Exhibit C is a true and correct copy of the Declaration of Dr.
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`Steven Murray Regarding Claim Construction, dated January 18, 2019.
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`5.
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`Attached hereto as Exhibit D is a true and correct copy of the Rebuttal
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`Declaration of Dr. Steven Murray Regarding Claim Construction, dated February 1, 2019.
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`6.
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`Attached hereto as Exhibit E is a true and correct copy of the Declaration of
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`Shefford Baker, dated January 25, 2019.
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`7.
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`Attached hereto as Exhibit F is a true and correct copy of the Final Written
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`Decision from inter partes review proceeding IPR2016-00389 (Paper No. 66). The parties
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`intended to include the Final Written Decision for IPR2016-00389 as an exhibit to their Joint
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`Claim Construction Chart but inadvertently omitted the correct document. See D.I. 166-1 at 10;
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`D.I. 166-2 at 5.
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`- 2 -
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`Case 1:14-cv-01432-LPS Document 237 Filed 12/12/19 Page 3 of 288 PageID #: 15735
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`I declare under penalty of perjury under the laws of the United States of America that the
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`foregoing is true and correct, and that this declaration is executed this 4th day of November
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`2019, at Newport Beach, California.
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` /s/ John Kappos
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` John Kappos
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`- 3 -
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`Case 1:14-cv-01432-LPS Document 237 Filed 12/12/19 Page 4 of 288 PageID #: 15736
`Case 1:14-cv-01432-LPS Document 237 Filed 12/12/19 Page 4 of 288 PageID #: 15736
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`EXHIBIT A
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`EXHIBIT A
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`Case 1:14-cv-01432-LPS Document 237 Filed 12/12/19 Page 5 of 288 PageID #: 15737
`Case 1:14-cv-01432-LPS Document 237 Filed 12/12/19 Page 5 of 288 PageID #: 15737
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`IN THE UNITED STATES DISTRICT COURT
`IN THE UNITED STATES DISTRICT COURT
`FOR THE DISTRICT OF DELAWARE
`FOR THE DISTRICT OF DELAWARE
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`C.A. NO. 14-01431-LPS-CJB
`C.A. NO. 14-01431-LPS-CJB
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`JURY TRIAL DEMANDED
`JURY TRIAL DEMANDED
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`C.A. NO. 14-01430-LPS-CJB
`C.A. NO. 14-01430-LPS-CJB
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`JURY TRIAL DEMANDED
`JURY TRIAL DEMANDED
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`C.A. NO. 14-01432-LPS-CJB
`C.A. NO. 14-01432-LPS-CJB
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`JURY TRIAL DEMANDED
`JURY TRIAL DEMANDED
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`ELM 3DS INNOVATIONS, LLC,
`ELM 3DS INNOVATIONS, LLC,
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`
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`PLAINTIFF,
`PLAINTIFF,
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`
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`MICRON TECHNOLOGY, INC.; MICRON
`MICRON TECHNOLOGY, INC.; MICRON
`SEMICONDUCTOR PRODUCTS, INC.; AND
`SEMICONDUCTOR PRODUCTS, INC.; AND
`MICRON CONSUMER PRODUCTS
`MICRON CONSUMER PRODUCTS
`GROUP, INC.,
`GROUP, INC.,
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`V.
`V.
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`DEFENDANTS.
`DEFENDANTS.
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`V.
`V.
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`ELM 3DS INNOVATIONS, LLC,
`ELM 3DS INNOVATIONS, LLC,
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`
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`PLAINTIFF,
`PLAINTIFF,
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`SAMSUNG ELECTRONICS CO., LTD.,
`SAMSUNG ELECTRONICS CO., LTD.,
`SAMSUNG SEMICONDUCTOR, INC.,
`SAMSUNG SEMICONDUCTOR, INC.,
`SAMSUNG ELECTRONICS AMERICA, INC.,
`SAMSUNG ELECTRONICS AMERICA, INC.,
`AND SAMSUNG AUSTIN
`AND SAMSUNG AUSTIN
`SEMICONDUCTOR, LLC,
`SEMICONDUCTOR, LLC,
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`
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`DEFENDANTS.
`DEFENDANTS.
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`V.
`V.
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`ELM 3DS INNOVATIONS, LLC,
`ELM 3DS INNOVATIONS, LLC,
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`PLAINTIFF,
`PLAINTIFF,
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`SK HYNIX INC., SK HYNIX AMERICA INC.,
`SK HYNIX INC., SK HYNIX AMERICA INC.,
`HYNIX SEMICONDUCTOR
`HYNIX SEMICONDUCTOR
`MANUFACTURING AMERICA INC., AND
`MANUFACTURING AMERICA INC., AND
`SK HYNIX MEMORY SOLUTIONS INC.,
`SK HYNIX MEMORY SOLUTIONS INC.,
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`
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`DEFENDANTS.
`DEFENDANTS.
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`vvvvvvvvvvvv
`vvvvvvvvvvvvv
`vvvvvvvvvvvv
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`DECLARATION OF DR. RICHARD B. FAIR
`DECLARATION OF DR. RICHARD B. FAIR
`REGARDING CLAIM CONSTRUCTION
`REGARDING CLAIM CONSTRUCTION
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`

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`Case 1:14-cv-01432-LPS Document 237 Filed 12/12/19 Page 6 of 288 PageID #: 15738
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`I, Dr. Richard B. Fair, declare as follows:
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`I.
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`INTRODUCTION
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`1.
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`I have been retained by Micron Technology, Inc.; Micron Semiconductor
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`Products, Inc.; and Micron Consumer Products Group, Inc. (collectively “Micron”); and
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`Samsung Electronics Co., Ltd., Samsung Semiconductor, Inc., Samsung Electronics America,
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`Inc., and Samsung Austin Semiconductor, LLC (collectively, “Samsung”) as an independent
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`expert in connection with the above-captioned lawsuit to provide my analyses and opinions in
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`certain technical aspects of this dispute. I understand that SK hynix Inc., SK hynix America Inc.,
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`Hynix Semiconductor Manufacturing America Inc., and SK hynix Memory Solutions, Inc.
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`(collectively, “SK hynix”) join all parts of this declaration except for Sections VI.D-VI.E.
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`2.
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`The purpose of this Declaration is to analyze and explain how a person of
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`ordinary skill in the art at the time of the alleged inventions would understand certain claim
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`terms in U.S. Patent Nos. 7,193,239 (the “’239 patent”), 7,504,732 (the “’732 patent”), 8,035,233
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`(the “’233 patent”), 8,410,617 (the “’617 patent”), 8,629,542 (the “’542 patent”), 8,653,672 (the
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`“’672 patent”), 8,791,581 (the “’581 patent”), 8,796,862 (the “’862 patent”), 8,824,159 (the
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`“’159 patent”), 8,841,778 (the “’778 patent”), 8,907,499 (the “’499 patent”), 8,928,119 (the
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`“’119 patent”), and 8,933,570 (the “’570 patent”) (collectively, the “Asserted Patents”), which I
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`understand are owned and asserted by Elm 3DS Innovations, LLC (“Elm”). My opinions and the
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`bases for my opinions are set forth below.
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`3.
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`I am being compensated at my ordinary and customary consulting rate of $600
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`per hour for my work. My compensation is in no way contingent on the nature of my findings,
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`the presentation of my findings in testimony, or the outcome of this or any other proceeding. I
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`have no other interest in this proceeding.
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`4.
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`I am competent to testify to the matters stated in this Declaration and have
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`1
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`Case 1:14-cv-01432-LPS Document 237 Filed 12/12/19 Page 7 of 288 PageID #: 15739
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`personal knowledge of the facts and statements herein. Each of the statements is true and
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`correct.
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`II.
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`BASIS FOR OPINION
`A.
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`Qualifications
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`5.
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`I have summarized in this section my educational background, career history,
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`publications, and other relevant qualifications. A more detailed account of my work experience,
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`qualifications, and publications is included in my curriculum vitae, attached as Exhibit A to this
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`declaration.
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`6.
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`I have been a professor in the Department of Electrical and Computer Engineering
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`at Duke University since 1981. My current tenured position is the Lord-Chandran Professor of
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`Engineering in the Pratt School of Engineering.
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`7.
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`I received my Bachelor of Science degree in Electrical Engineering from Duke
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`University in 1964. In 1966, I received a Master of Science degree in Electrical Engineering
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`from Penn State University. In 1969, I received a Ph.D. in Electrical Engineering from Duke
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`University.
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`8.
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`Since 1969, I have been involved in the research, teaching, development, design,
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`and manufacturing of semiconductor devices and processes. For example, I have experience
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`with thin film processes such as physical and chemical vapor deposition methods, modeling
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`semiconductor technology, designing integrated circuits and semiconductor chips, designing
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`high-density memory and analog circuit layouts, and fabricating and packaging integrated
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`circuits. In addition, I have experience in the design, layout, and simulation of analog and digital
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`integrated circuits.
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`9.
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`From 1969 to 1981, I worked at Bell Laboratories and I had direct experience
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`with the manufacturing, design, and testing of numerous semiconductor devices and integrated
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`2
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`Case 1:14-cv-01432-LPS Document 237 Filed 12/12/19 Page 8 of 288 PageID #: 15740
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`circuits, including metal-oxide-semiconductor (MOS) dynamic memory chips. I researched and
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`developed numerous semiconductor devices, including silicon and gallium arsenide transistors,
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`analog and digital integrated circuits, photovoltaic devices, and thin film transistors (“TFTs”)
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`fabricated in laser recrystallized polycrystalline silicon.
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`10.
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`During my time at Bell Laboratories, I worked on advanced silicon process
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`development in the areas of photolithography, thin film deposition, metallization, etching,
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`cleaning, plasma-assisted processing, LPCVD, ion implantation doping, and annealing/oxidation.
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`11.
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`In 1981, I became Professor of Electrical Engineering at Duke University. At the
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`same time, I also served in a joint role as Vice President of the Microelectronics Center of North
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`Carolina (“MCNC”) in Research Triangle Park, North Carolina. During 1990-1993, I led the
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`Center for Microelectronic Systems. The MCNC and the Center for Microelectronic Systems
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`were devoted to the development of advanced technologies for fabricating integrated circuits and
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`for improvements in semiconductor manufacturing processes in general. My areas of
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`responsibility as Vice President included analog and digital integrated circuit design, system
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`design, semiconductor fabrication technology, advanced multichip module packaging, and
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`studies in electronic materials, including amorphous semiconductors and multi-layered
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`aluminum and copper interconnects. In my division at MCNC, we designed, fabricated, and
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`tested the world’s first one-million-transistor processor chip in 1987. I also was responsible for
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`the MCNC analytical lab, which included electron microscopy, atomic composition analysis, and
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`sample preparation for reverse engineering studies.
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`12. While at MCNC, I helped set up a state-of-the-art CMOS processing facility and
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`directed research on semiconductor processing including photolithography, wafer cleaning,
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`annealing, ion implantation, plasma-enhanced CVD of thin dielectric films, metallization, and
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`3
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`Case 1:14-cv-01432-LPS Document 237 Filed 12/12/19 Page 9 of 288 PageID #: 15741
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`anisotropic etching processes. We conducted research on multi-level metal interconnects, barrier
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`metallurgy, organic and inorganic inter-metal dielectrics, anti-reflective coatings, via and trench
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`etching processes, 3-point wafer bending stress effects, and selective tungsten deposition for via
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`filling. We also had an active research program in characterizing point defects in ion implanted
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`amorphous and single crystal silicon, with the goal of understanding implantation defect
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`annealing effects on dopant impurity diffusion.
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`13.
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`In 1994, I returned to Duke University full-time. Since then I have continued to
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`teach courses on (1) the design and analysis of analog and digital integrated circuits, (2)
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`semiconductor devices, (3) the chemistry and physics of transistor and integrated circuit
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`fabrication, and (4) thin-film microfluidic devices, fluid dynamics, and applications. In addition,
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`I have an active funded research program that involves undergraduate and graduate students.
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`Areas of research have included silicon cantilever beam sensors, silicon wafer processing by
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`rapid thermal annealing, and microfluidic devices.
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`14.
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`I have published over 170 papers in refereed and peer-reviewed journals and
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`conference proceedings, contributed chapters to 12 books, edited nine books or conference
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`proceedings, given over 130 invited talks in the field of electrical engineering, and I am a named
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`inventor on 35 granted U.S. patents and 8 pending U.S. patent applications.
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`15.
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`I am also a Life Fellow of the Institute of Electrical and Electronic Engineers
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`(“IEEE”), a Fellow of the Electrochemical Society, past Editor-in-Chief of the Proceedings of
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`the IEEE, and past Associate Editor of the IEEE Transactions on Electron Devices. I have been
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`listed in Who’s Who in America, Who’s Who in Engineering, Who’s Who in the Semiconductor
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`Industry, Who’s Who in Frontiers of Science and Technology, Who’s Who in Technology
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`Today, and American Men and Women in Science. I am a recipient of the IEEE Third
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`4
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`Case 1:14-cv-01432-LPS Document 237 Filed 12/12/19 Page 10 of 288 PageID #: 15742
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`Millennium Medal, and I was awarded the Solid State Science and Technology Medal of the
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`Electrochemical Society in April 2003.
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`16.
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`Based on my over 49 years of experience in thin film and bulk semiconductor
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`device design, processing technology research and development, integrated circuit fabrication,
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`research in point defects in amorphous and single crystal silicon, and the acceptance of my
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`publications and professional recognition by societies in my field, I believe that I am considered
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`to be an expert in the art of semiconductor processing, semiconductor device design and
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`fabrication, and integrated circuit design and fabrication. I have been qualified numerous times
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`as an expert, and I have given expert opinion testimony relating to semiconductor processing,
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`including dielectric material properties, stress analysis, stacked 3D ICs, bonding of stacked
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`layers, and layer-to-layer interconnection. Additionally, I have extensive publications in the
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`field of semiconductor technology, and my accomplishments have been recognized by both
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`academic and professional societies.
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`B. Materials Considered
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`17.
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`As part of my preparation for writing this Declaration, I reviewed the Asserted
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`Patents, their prosecution histories, the parties’ proposed constructions, and the extrinsic
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`evidence cited in this declaration.
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`III. LEGAL STANDARDS FOR CLAIM CONSTRUCTION
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`18.
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`I understand that the words of a claim are generally given the ordinary and
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`customary meaning that the term would have to a person of ordinary skill in the art at the time of
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`the invention.
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`19.
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`I understand that to determine how a person of ordinary skill would understand a
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`claim term, courts may consider both “intrinsic” and “extrinsic” evidence. I understand that
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`courts look first to the intrinsic evidence of record, which includes the patent itself (including the
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`5
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`Case 1:14-cv-01432-LPS Document 237 Filed 12/12/19 Page 11 of 288 PageID #: 15743
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`claims and specification) and the prosecution history. I also understand that courts may consider
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`extrinsic evidence, such as expert and inventor testimony, dictionaries, and learned treatises.
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`20.
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`I understand that a person of ordinary skill in the art is deemed to read the claim
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`term not only in the context of the particular claim in which it appears, but also in the context of
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`the entire patent, including the specification and prosecution history. Thus, any explicit
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`definitions of terms or intentional disclaimers or disavowals of claim scope in the specification
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`or prosecution history must be considered in determining the meaning of a claim term.
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`21.
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`I understand that particular embodiments appearing in the written description do
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`not limit claim language that has broader effect, and that the scope of the claims is not
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`necessarily limited to inventions that look like the ones shown in the figures and described in the
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`specification. However, I also understand that the patentee is required to define precisely what
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`he claims his invention to be, and the claims must be construed in a manner consistent with the
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`specification.
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`22.
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`I am informed that a term must be interpreted with a full understanding of what
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`the inventors actually invented and intended to include within the scope of the claim as set forth
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`in the patent itself. Thus, claim terms should not be broadly construed to encompass subject
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`matter that is technically within the broadest reading of the term, but is not supported when the
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`claims are viewed in light of the invention described in the specification.
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`23.
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`I understand that the prosecution file history of the patent provides additional
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`evidence of how both the Patent Office and the inventors understood the terms of the patent,
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`particularly in light of what was known in the prior art. I understand that arguments and
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`amendments made during prosecution may further require a narrow interpretation of a claim
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`term, even if that term is used more broadly in the specification.
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`6
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`Case 1:14-cv-01432-LPS Document 237 Filed 12/12/19 Page 12 of 288 PageID #: 15744
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`24.
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`I understand that differences among claims can also be a useful guide in
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`understanding the meaning of particular claim terms. For example, I am familiar with the
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`doctrine of “claim differentiation” where the presence of dependent claims that add a particular
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`limitation to an independent claim gives rise to a presumption that the limitation in question is
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`not present in the independent claim. However, I understand that “claim differentiation” is not a
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`rigid rule and it cannot overcome a contrary construction dictated by the written description or
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`prosecution history.
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`25.
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`I understand that patent claims must particularly point out and distinctly claim the
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`subject matter which the inventors regard as the invention. I understand that if a claim term,
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`when interpreted in light of the specification and the prosecution history, fails to inform those
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`skilled in the art about the scope of the claimed invention with reasonable certainty, then the
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`claim term and all claims reciting such term are indefinite. For example, a relative term or term
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`of degree may be indefinite if the patent at issue fails to provide some standard for measuring the
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`degree intended.
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`IV.
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`THE ASSERTED PATENTS
`A.
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`The ’239 Patent1 Specification
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`26.
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`The ’239 patent is entitled “Three Dimensional Structure Integrated Circuit.”
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`’239 patent, Cover; 1:1-2. The ’239 patent is directed to stacked integrated circuit memory. Id.,
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`1:19-20. The ’239 patent describes fabrication methods for three-dimensional integrated circuits
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`
`
` 1
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` All of the Asserted Patents are related and claim priority to a common application. The
`specifications of the Asserted Patents are substantially similar. Thus, by identifying portions of
`the ’239 patent specification, this declaration also incorporates all corresponding portions of the
`patent specification in each of the remaining Asserted Patents.
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`7
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`Case 1:14-cv-01432-LPS Document 237 Filed 12/12/19 Page 13 of 288 PageID #: 15745
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`which include the steps of thinning substrates, bonding the substrates to form a vertical stack, and
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`forming vertical interconnections passing through the substrates. Id. at 7:36-11:25.
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`27.
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`The ’239 patent describes “[g]rind[ing] the backside or exposed surface of the
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`second circuit substrate to a thickness of less than 50 μm and then polish[ing] or smooth[ing] the
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`surface.” Id. at 9:25-27; see also id. at 11:1. The ’239 patent describes that, by thinning the
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`substrate to a thickness of less than 50 μm and then polishing or smoothing the surface, “[t]he
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`thinned substrate is now a substantially flexible substrate.” Id. at 9:25-28; see also 3:18-19
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`(“Thinning of the memory circuit to less than about 50 μm in thickness forming a substantially
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`flexible substrate with planar processed bond surfaces and bonding the circuit to the circuit stack
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`while still in wafer substrate form[.]”). Next, the backside of the substrate is processed to form
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`interconnections that pass through the substrate. Id. at 9:57-10:28. The resulting structure is
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`illustrated in Figure 4, reproduced below:
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`Id. at Fig. 4. As shown in Figure 4, a “feed-through 417” passes through a thinned “substrate
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`415.” Id. at 10:21-24. A “‘DRAM processed’ portion 420 of the wafer” over the thinned
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`substrate 415 “includes various dielectric and metal layers.” Id. at 10:13-15. The dielectric and
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`metal layers may include, for example, three metal layers. Id. at 10:16-20. Contacts 413 and
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`421 are formed at matching locations on the top-side (i.e., the transistor-forming side) and
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`bottom-side of the integrated circuit. Id. at 10:16-20, 10:26-27.
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`28.
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`The ’239 patent further explains that the substrates, such as that shown in Figure 4
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`above, are stacked and interconnected to form a three-dimensional integrated circuit. See id. at
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`10:21-30, Figs. 1a-1c. The specification discloses that the substrates are preferably bonded
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`together using thermal diffusion metal bonding. Id. at 7:62-64; see also id. at 6:52-60, 8:12-54,
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`9:63-10:5, 11:15-24. Thermal diffusion bonding refers to a process of using heat and pressure to
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`fuse together two metallic surfaces without using additional adhesive or bonding materials. See
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`id. at 8:12-54. The specification explains that the “preferred bonding material is pure aluminum
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`or an alloy of aluminum,” but that other conductive materials including “Sn [tin], Ti [titanium], In
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`[indium], Pb [lead], Zn [zinc], Ni [nickel], Cu [copper], Pt [platinum], Au [gold] or alloys of such
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`metals” and “highly conductive polysilicon” can also be used. Id. at 8:29-40. Although the
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`bonding surfaces may include some non-conductive areas composed of “silicon oxide,” there
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`must be some conductive surfaces being bonded in order to form “vertical interconnections” that
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`electrically connects the two circuits. Id. at 8:34-45. Indeed, the specification explains that native
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`surface oxides over the conductive pads must be removed prior to bonding in order to avoid
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`“increase[ing] the resistance in the vertical interconnections formed by the bond.” Id. at 8:41-54.
`
`29.
`
`The specification discloses other approaches to bond multiple substrates to form a
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`3D circuit, such as using “anisotropically conductive epoxy adhesive … to form interconnects
`
`between the two” stacked substrates. Id. at 6:52-60. An “anisotropically conductive epoxy
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`adhesive” is an adhesive material that conducts electricity in one direction (e.g., in a direction
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`9
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`perpendicular to the substrate surface) but not in another direction (e.g., in a direction parallel to
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`the substrate surface). When “anisotropically conductive epoxy adhesive” is used to bond
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`between two stacked layers, such as two of the circuits show in Figure 4 above, it would form
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`vertical interconnects between the two layers to electrically connect them. See id. The
`
`specification discloses using conventional input/output (“I/O”) bonding methods, such as wire
`
`bonding, to connect the stacked 3D integrated circuit to a package substrate or other structures
`
`(see, e.g., id. at 9:63-10:5, 10:47-50, 11:15-24), but the body of the specification does not disclose
`
`using any method other than using vertical, through-silicon interconnects to interconnect multiple
`
`layers within a stacked 3D integrated circuit.
`
`30.
`
`The specification and claims of the ’239 patent also recite the use of low tensile
`
`stress dielectrics. See, e.g., id. at 8:66-9:16, claim 2. The specification acknowledges that the use
`
`of such dielectrics was described years before the earliest alleged priority date of the ’239 patent
`
`by the named inventor in Leedy ’695: “The thinned (substantially flexible) substrate circuit layers
`
`are preferably made with dielectrics in low stress (less than 5×108 dynes/cm2) such as low stress
`
`silicon dioxide and silicon nitride dielectrics as opposed to the more commonly used higher stress
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`dielectrics of silicon oxide and silicon nitride used in conventional memory circuit fabrication.
`
`Such low stress dielectrics are discussed at length in U.S. Pat. No. 5,354,695 of the present
`
`inventor, incorporated herein by reference.” Id. at 8:66-9:7. The ’239 patent explains that “[t]he
`
`use of dielectrics with conventional stress levels could be used in the assembly of” the described
`
`3D ICs, but that “if more than a few layers comprise the stacked assembly, each layer in the
`
`assembly will have to be stress balanced so that the net stress of the deposited films of a layer is
`
`less than 5×108 dynes/cm2.” Id. at 9:7-9:12. Other than referencing the disclosure of Leedy ’695,
`
`the specification of the ’239 Patent does not contain any other disclosure regarding the structure
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`and properties of low tensile stress dielectrics.
`
`B.
`
`31.
`
`Asserted Claims
`
`I understand that Elm has asserted the following claims in this litigation, where
`
`brackets indicate a claim asserted only against Samsung Defendants and parentheses indicate
`
`claims asserted only against SK hynix Defendants and Micron Defendants:
`
`Asserted Patent
`U.S. Pat. No. 7,193,239
`U.S. Pat. No. 7,474,004
`U.S. Pat. No. 7,504,732
`U.S. Pat. No. 8,035,233
`U.S. Pat. No. 8,410,617
`U.S. Pat. No. 8,629,542
`U.S. Pat. No. 8,653,672
`U.S. Pat. No. 8,796,862
`U.S. Pat. No. 8,841,778
`U.S. Pat. No. 8,907,499
`U.S. Pat. No. 8,928,119
`U.S. Pat. No. 8,933,570
`U.S. Pat. No. 8,791,581
`
`32.
`
`Asserted Claims
`10, 11, 12, 18, 19, 20, 60, 61, 62, 63, 67, 70, 71, 72, 73, 77
`20, 21, 22, 23
`10, [11], 13, 14
`34
`51
`1, 2, 3, 30, 31, 33, 40, 41, 44
`17, 22, 95, 129, [130], 131, 132, 145, 146, 152
`34, 36, 135, 136, 137, 138, 147
`32, 44, 46, 54
`12, 13, 24, [36], [37], 38, (49), 53, 83, 86, 87, 132
`18, (33)
`58, 60, [61], 67
`(1), 12, 36, 54, 78, 116, 136
`
`Claims 12, 10, 11, and 60 of the ’239 patent, excerpted below, recite many of the
`
`same components and other features described above in the specification.
`
`1. Circuitry comprising: a plurality of monolithic substrates having integrated circuits
`
`formed thereon and stacked in layers such that each layer comprises only one of the
`
`substrates, wherein at least one of the plurality of substrates is a substantially flexible
`
`
`
` 2
`
` Claim 1 is not asserted in this case but is excerpted here because other claims asserted in this
`case (e.g., claims 10, 11) depend from claim 1.
`
`11
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`substrate, and wherein a major portion of the monolithic substrate is removed; and
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`between adjacent substrates, a bonding layer bonding together the adjacent substrates, the
`
`bonding layer being formed by bonding first and second substantially planar surfaces
`
`having a bond-forming material throughout a majority of the surface area thereof.
`
`10. The apparatus of claim 1, wherein the circuitry is formed with a low stress dielectric.
`
`11. The apparatus of claim 10, wherein the low stress dielectric is at least one of a silicon
`
`dioxide dielectric, an oxide of silicon dielectric, and caused to have stress of about
`
`5x108 dynes/cm2 or less.
`
` 60. An integrated circuit structure comprising: a plurality of semiconductor dice, each
`
`die having an integrated circuit formed thereon, said dice being stacked in layers, wherein
`
`at least one of the plurality of dice is substantially flexible, and wherein at least one of the
`
`plurality of dice has at least one of polycrystalline active circuitry formed thereon,
`
`reconfiguration circuitry formed thereon, and passive circuitry formed thereon; and
`
`between adjacent dice, a bonding layer bonding together the adjacent dice, the bonding
`
`layer bonding first and second substantially planar adjacent surfaces of the adjacent dice,
`
`with at least one or more portions of the bonding layer being located other than at the
`
`edges of the adjacent dice.
`
`33.
`
`Claims 12 and 13 of the ’499 patent, excerpted below, also recite the components
`
`and other features described above in the specification.
`
`12. A thin and substantially flexible circuit comprising: a thin monocrystalline
`
`semiconductor layer of one piece; a silicon-based dielectric layer formed on the thin
`
`semiconductor layer and having a stress of less than 5x108 dynes/cm2
`
` tensile; and
`
`circuitry supported by the thin semiconductor layer and the dielectric layer defining an
`
`12
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`integrated circuit die having an area, wherein the thin semiconductor layer extends
`
`throughout a substantial portion of the area of the integrated circuit die.
`
`13. The thin and substantially flexible circuit of claim 12, comprising: a vertical
`
`interconnect conductor extending vertically through the thin semiconductor layer and
`
`coupled to said circuitry; and a vertical silicon-based dielectric insulator extending
`
`vertically through the thin semiconductor layer and around the interconnect conductor
`
`and having a stress of less than 5x108 dynes/cm2 tensile.
`
`C.
`
`Relevant Prosecution History
`
`‘499 patent
`
`34.
`
`Application No. 13/734,874 (which later issued as the asserted ’499 patent) was
`
`filed on January 4, 2013, as a continuation of application No. 12/788,618 (which later issued as
`
`the asserted ’672 Patent). On May 29, 2013, the Examiner issued a Non-Final Rejection in
`
`which he rejected all pending claims (i.e., claims 1-5, 7-17, and 19-32). Claims 7, 12, 19, and 24
`
`were objected to for reciting “substantially flexible,” which, according to the Examiner, rendered
`
`“the claims unclarity, since the resulting claims do not clearly set for the metes and bounds of the
`
`patent protection desired.” Office Action (May 29, 2013) at 3. The Examiner rejected Claims 1-
`
`5, 7-17, and 19-32 on the ground of non-statutory obviousness-type double patenting over claims
`
`1-62 of U.S. Patent No. 8,410,617. Claims 1, 26, and 30 were also rejected as being anticipated
`
`by U.S. Patent No. 4,104,418 (Park). Claim 14 was found to be obvious in light of Park. The
`
`Examiner explained that Park discloses a flexible substrate with a low-stress dielectric layer. Id.
`
`at 7.
`
`35.
`
`In response, the Applicant distinguished Park on two grounds. First, the
`
`Applicant argued that Park discloses depositing a dielectric layer on a dielectric substrate for flat
`
`panel displays, and that Park thus failed to disclose a semiconductor substrate. Second, the
`
`13
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`Applicant argued that Park discloses forming a low compressive stress dielectric layer, whereas
`
`the claims were amended to require a low tensile stress dielectric layer. Applicant’s Amendment
`
`and Response (June 20, 2013).
`
`36.
`
`To overcome the objection that “substantially flexible” is indefinite, the Applicant
`
`stated:
`
`Id. at 9.3
`
`
`
`37.
`
`Based on the Applicant’s response, the Examiner withdrew his rejections for
`
`indefiniteness of the term “substantially flexible” and in view of Park, while maintaining the
`
`double-patenting rejection. Office Action (July 8, 2013). The Examiner rejected Claims 1 and
`
`26 as being anticipated by U.S. Patent No. 4,637,029 (Haya