ELM 3DS INNOVATIONS, LLC,
` PLAINTIFF,
`
` V.
`
`MICRON TECHNOLOGY, INC.; MICRON
`SEMICONDUCTOR PRODUCTS, INC.; AND
`MICRON CONSUMER PRODUCTS
`GROUP, INC.,
` DEFENDANTS.
`
`
`
`ELM 3DS INNOVATIONS, LLC,
` PLAINTIFF,
`
` V.
`
`SAMSUNG ELECTRONICS CO., LTD.,
`SAMSUNG SEMICONDUCTOR, INC.,
`SAMSUNG ELECTRONICS AMERICA, INC.,
`AND SAMSUNG AUSTIN
`SEMICONDUCTOR, LLC,
` DEFENDANTS.
`
`
`
`ELM 3DS INNOVATIONS, LLC,
` PLAINTIFF,
`
` V.
`
`SK HYNIX INC., SK HYNIX AMERICA INC.,
`HYNIX SEMICONDUCTOR
`MANUFACTURING AMERICA INC., AND
`SK HYNIX MEMORY SOLUTIONS INC.,
` DEFENDANTS.
`
`
`
`
`
`
`C.A. No. 14-01431-LPS-CJB
`
`JURY TRIAL DEMANDED
`
`
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`
`
`C.A. No. 14-01430-LPS-CJB
`
`JURY TRIAL DEMANDED
`
`
`
`
`
`C.A. No. 14-01432-LPS-CJB
`
`JURY TRIAL DEMANDED
`
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`Case 1:14-cv-01432-LPS Document 233 Filed 11/04/19 Page 1 of 10 PageID #: 15621
`
`IN THE UNITED STATES DISTRICT COURT
`FOR THE DISTRICT OF DELAWARE
`
`
`
`DEFENDANTS’ OBJECTIONS AND RESPONSES
`TO PLAINTIFF’S TECHNOLOGY TUTORIAL
`
`
`
`

`

`Case 1:14-cv-01432-LPS Document 233 Filed 11/04/19 Page 2 of 10 PageID #: 15622
`
`I.
`
`INTRODUCTION
`
`Pursuant to Paragraph 10 of the Amended Scheduling Order (D.I. 176 in 14-01430-LPS,
`
`D.I. 152 in 14-01431-LPS, D.I. 179 in 14-01432-LPS), Defendants submit these objections and
`
`responses to the technology tutorial (D.I. 200 in 14-01430-LPS, D.I. 172 in 14-01431-LPS, and
`
`D.I. 201 in 14-01432-LPS) submitted by Plaintiff Elm 3DS Innovations, LLC (“Elm”). Elm’s
`
`tutorial violates the Court’s Order that the “tutorial should focus on the technology in issue and
`
`should not be used for argument,” not only by arguing the meaning and scope of disputed claim
`
`language, but doing so in a misleading manner. Defendants respectfully request that the Court
`
`disregard certain passages of Elm’s tutorial as set forth below.
`
`II.
`
`OBJECTIONS TO ELM’S TUTORIAL
`
`Elm improperly uses its tutorial to argue an overly broad interpretation for the disputed
`
`claim term “vertical interconnect” and its variants which appear as follows in the Joint Claim
`
`Construction Chart (JCCC) (D.I. 194 in 14-01430-LPS, D.I. 166 in 14-01431-LPS, and D.I. 193
`
`in 14-01432-LPS):
`
`JCCC Term 6. “vertically interconnected circuit block stacks” / “vertically
`interconnected circuit blocks”;
`JCCC Term 7. “a plurality of vertical interconnect segments interconnecting the first
`and second integrated circuit layers, wherein each vertical interconnect segment
`forms an interconnection only between a pair of adjacent integrated circuits”;
`JCCC Term 8. “said plurality of first interconnection and said plurality of second
`interconnections are substantially aligned with each other, and said plurality of
`first interconnections and said plurality of second interconnections are electrically
`coupled together to form a plurality of vertical interconnections, including
`redundant vertical interconnections.”
`
`In its tutorial, Elm repeatedly uses the disputed claim term “vertical interconnect” and its
`
`variants in a manner inconsistent with the use of that term in the asserted patents. See, e.g., U.S.
`
`Patent No. 7,193,239 (D.I. 1-1) (“’239 Patent”) at 4:13-19 (“The term fine-grain inter-layer
`
`vertical interconnect is used to mean electrical interconnect conductors that pass through a
`
`
`
`

`

`Case 1:14-cv-01432-LPS Document 233 Filed 11/04/19 Page 3 of 10 PageID #: 15623
`
`circuit layer with or without an intervening device element and have a pitch of nominally less
`
`than 100 µm and more typically less than 10 µm, but not limited to a pitch of less than 2
`
`µm ….”) (emphasis added).1
`
`First, as shown below in tutorial slides 47 and 48, Elm depicts prior art 3D structure
`
`interconnects, which do not pass through a circuit layer, as “vertical interconnects.” See also
`
`Elm’s Tutorial at 8:48-9:02. Elm’s characterization thus contradicts the definition of “vertical
`
`interconnects” in the asserted patents. See ’239 Patent at 4:13-19. Thus, Elm’s tutorial slides
`
`47-48 and accompanying narration should be disregarded by the Court.
`
`Elm’s Tutorial at Slide 47.
`
`Elm’s Tutorial at Slide 48.
`
`
`Second, in tutorial slides 51-53 and accompanying narration (see Elm’s Tutorial at 9:54-
`
`10:37) provided below, Elm again uses the claim term “vertical interconnect” in an
`
`argumentative and misleading manner to convey a meaning that is inconsistent with that term’s
`
`use in the asserted patents. For example, in the narration accompanying slide 51, Plaintiff argues
`
`for a general interpretation of the disputed claim term untethered to the asserted patents:
`
`When stacking chips, designers have dozens of vertical connection methods at
`their disposal. These vertical connection methods generally fit into two
`categories.
`
`
`1 “Fine-grain” refers to the conductors’ pitch, namely “nominally less than 100 µm and more
`typically less than 10 µm, but not limited to a pitch of less than 2 µm.” ’239 Patent at 4:13-19.
`
`
`
`2
`
`
`
`

`

`Case 1:14-cv-01432-LPS Document 233 Filed 11/04/19 Page 4 of 10 PageID #: 15624
`
`Elm’s Tutorial at 9:54-10:04 (narration accompanying slide 51) (emphasis added).
`
`In tutorial slide 52 and accompanying narration, Elm states that “vertical connections”
`
`encompass a first category of prior art interconnections which it refers to as “periphery
`
`interconnections.” But, here again, Elm misleadingly depicts the supposed “vertical
`
`interconnections” as electrical conductors that do not pass through a circuit layer, thus
`
`contradicting the asserted patents’ definition of “vertical interconnect.” See ’239 Patent at 4:13-
`
`19. The asserted patents never refer to these prior art interconnects as “vertical interconnects.”
`
`In fact, the asserted patents distinguish these same prior art interconnects—“interconnect[s] …
`
`formed along the outside surface of the circuit stack”—from the claimed “vertical
`
`interconnects.” See, e.g.,’239 Patent at 2:34-48 (explaining that these prior art interconnects are
`
`“too expensive” in contrast to the “vertical interconnects” in the claimed invention); 3:10-40;
`
`1:66-67; 6:7-9; 6:15-22.
`
`“Periphery interconnections, such as
`soldered vertical PC boards, metal films
`patterned and deposited on the face of a chip
`stack, and wire bonded stacked chips.”
`
`Elm’s Tutorial at Slide 52.
`
`Narration at 10:04-10:14 (narration
`accompanying Elm’s Tutorial at Slide 52).
`
`
`In tutorial slide 53 and accompanying narration, Elm asserts that the disputed term’s
`
`meaning encompasses a second category of prior art interconnections which it refers to as “area
`
`interconnections.” In addition to being argumentative, Elm’s characterization is misleading
`
`because Elm identifies connections which are merely between two layers but do not pass through
`
`
`
`3
`
`
`
`

`

`Case 1:14-cv-01432-LPS Document 233 Filed 11/04/19 Page 5 of 10 PageID #: 15625
`
`a layer, as “vertical interconnects,” thus contradicting that term’s definition in the asserted
`
`patents. See ’239 Patent at 4:13-19.
`
`“The second category of vertical
`interconnects are known as area
`interconnections. Two examples of area
`interconnections are shown here. The
`illustration on the left depicts solder ball
`arrays while the illustration on the right
`depicts stacked silicon wafers with filled
`vias. As area interconnections are not
`restricted to the edges of a substrate, more
`connections can be made.”
`
`Narration at 10:14-10:37 (narration
`accompanying Elm’s Tutorial at Slide 53)
`(emphasis added).
`
`Elm’s Tutorial at Slide 53.
`
`
`Thus, Elm’s tutorial slides 51-53 and their accompanying narration should be disregarded
`
`by the Court as being argumentative and misleading.
`
`Elm also improperly uses its tutorial in a subtle yet unmistakable attempt to fill gaps in
`
`the disclosure of the asserted patents and rehabilitate the indefinite “stress” terms. These terms
`
`appear in the JCCC as:
`
`JCCC Term 4. “have stress of about 5×108 dynes/cm2 or less” and variants
`JCCC Term 5. “low stress dielectric” and variants
`
`
`As Defendants explain in their claim construction briefing, the “stress” terms are
`
`indefinite because, among other things, there are many types of stresses in the context of
`
`semiconductor devices and a person of ordinary skill in the art (POSA) would not know with
`
`reasonable certainty, from the intrinsic evidence or otherwise, which type of stress is claimed.
`
`Defendants’ Opening Br. at 11-12. Elm’s tutorial (and specifically tutorial slide 57 and
`
`accompanying narration) improperly and misleadingly implies that the patents express concern
`
`about “curvature caused by the stress of the dielectric” and propose addressing that specific
`
`
`
`4
`
`
`
`

`

`Case 1:14-cv-01432-LPS Document 233 Filed 11/04/19 Page 6 of 10 PageID #: 15626
`
`concern by utilizing a “flexible die with a low stress dielectric.” Elm’s Tutorial at 11:02-11:24
`
`(narration accompanying slides 56-58).
`
`“But thinning the die can lead to increased
`curvature caused by the stress of the
`dielectric, and the reliability of the substrate
`itself may suffer. The patents address that
`problem by combining a thinned, flexible
`die with a low stress dielectric.”
`
`Elm’s Tutorial at Slide 57.
`
`Narration at 11:02-11:24 (narration
`accompanying Elm’s Tutorial at Slide 56-
`58).
`
`
`Contrary to what is implied by Elm’s assertion in its tutorial, the asserted patents do not
`
`highlight substrate curvature as a concern or associate such curvature with dielectric stress.
`
`Defendants’ Responsive Br. at 3-4. It is apparent that Elm is improperly attempting to
`
`rehabilitate the indefinite “stress” terms, and its tutorial slide 57 and narration from 11:02-11:24
`
`should thus be disregarded by the Court.
`
`III. CONCLUSION
`
`For the foregoing reasons, Defendants object to Plaintiff Elm’s technology tutorial and
`
`respectfully request that Elm’s tutorial slides 47-48, 51-53, and 57 and their accompanying
`
`narration be disregarded by the Court.
`
`
`
`
`
`
`
`
`
`
`
`
`
`5
`
`
`
`

`

`Case 1:14-cv-01432-LPS Document 233 Filed 11/04/19 Page 7 of 10 PageID #: 15627
`
`Dated: November 4, 2019
`
`OF COUNSEL:
`
`John Kappos
`Hana Oh Chen
`O’MELVENY & MYERS LLP
`610 Newport Center Drive
`Newport Beach, California 92660-3823
`(949) 823-6900
`jkappos@omm.com
`hchen@omm.com
`
`Brian Cook
`Xin-Yi Zhou
`O’MELVENY & MYERS LLP
`400 South Hope Street
`Los Angeles, California 90071-2899
`(213) 430-6000
`bcook@omm.com
`vzhou@omm.com
`
`OF COUNSEL:
`
`Allan M. Soobert
`Naveen Modi
`Phillip W. Citroen
`PAUL HASTINGS LLP
`875 15th Street, N.W.
`Washington, D.C. 20005
`(202) 551-1700
`(202) 551-1705 (fax)
`allansoobert@paulhastings.com
`naveenmodi@paulhastings.com
`phillipcitroen@paulhastings.com
`ServicePHSamsung-
`ELM3DS@paulhastings.com
`
`
`
`
`RICHARDS, LAYTON & FINGER, P.A.
`
`/s/ Tyler E. Cragg
`Frederick L. Cottrell , III (No. 2555)
`Travis S. Hunter (No. 5350)
`Tyler E. Cragg (No. 6398)
`One Rodney Square
`920 North King Street
`Wilmington, DE 19801
`(302) 651-7836
`cottrell@rlf.com
`hunter@rlf.com
`cragg@rlf.com
`
`Attorneys for Defendants Micron Technology,
`Inc., Micron Semiconductor Products, Inc. and
`Micron Consumer Products Group, Inc.
`
`YOUNG CONAWAY STARGATT &
`TAYLOR, LLP
`
`/s/ Adam W. Poff
`Adam W. Poff (No. 3990)
`Pilar G. Kraman (No. 5199)
`Rodney Square
`1000 North King Street
`Wilmington, DE 19801
`(302) 571-6600
`apoff@ycst.com
`pkraman@ycst.com
`
`Attorneys for Defendants Samsung Electronics
`Co., Ltd., Samsung Semiconductor, Inc.,
`Samsung Electronics America, Inc., and
`Samsung Austin Semiconductor, LLC
`
`
`
`6
`
`
`
`

`

`Case 1:14-cv-01432-LPS Document 233 Filed 11/04/19 Page 8 of 10 PageID #: 15628
`
`OF COUNSEL:
`
`L. Howard Chen
`Harold H. Davis
`Nicholas A. Brown
`GREENBERG TRAURIG, LLP
`Four Embarcadero Center, Suite 3000
`San Francisco, CA 94111
`(415) 655-1300
`chenh@gtlaw.com
`davish@gtlaw.com
`
`Vishesh Narayen
`GREENBERG TRAURIG, LLP
`101 E. Kennedy Blvd, Suite 1900
`Tampa, FL 33602
`(813) 318.5700
`narayenv@gtlaw.com
`
`
`GREENBERG TRAURIG, LLP
`
`/s/ Benjamin J. Schladweiler
`Benjamin J. Schladweiler (#4601)
`The Nemours Building
`1007 North Orange Street, Suite 1200
`Wilmington, DE 19801
`(302) 661-7352
`schladweilerb@gtlaw.com
`
`Attorneys for Defendants SK Hynix Inc., SK
`Hynix America Inc.,hynix Semiconductor
`Manufacturing America Inc., and SK Hynix
`Memory Solutions Inc.
`
`
`
`
`
`
`
`
`
`7
`
`
`
`

`

`Case 1:14-cv-01432-LPS Document 233 Filed 11/04/19 Page 9 of 10 PageID #: 15629
`
`
`CERTIFICATE OF SERVICE
`
`
`I, Adam W. Poff, hereby certify that on November 4, 2019, I caused to be
`
`electronically filed a true and correct copy of the foregoing document with the Clerk of the Court
`
`using CM/ECF, which will send notification that such filing is available for viewing and
`
`downloading to the following counsel of record:
`
`Joseph J. Farnan, Jr. Esquire
`Brian E. Farnan, Esquire
`Michael J. Farnan, Esquire
`Farnan, LLP
`919 North Market Street, 12th Floor
`Wilmington, DE 19801
`farnan@farnanlaw.com
`bfarnan@farnanlaw.com
`mfarnan@farnanlaw.com
`
`Attorneys for Plaintiff
`
`I further certify that on November 4, 2019, I caused a true and correct copy of the
`
`foregoing document to be served by e-mail on the above-listed counsel of record, and on the
`
`following:
`
`Adam K. Mortara, Esquire
`Matthew R. Ford, Esquire
`Bartlit Beck Herman Palenchar & Scott LLP
`54 West Hubbard Street, Suite 300
`Chicago, IL 60654
`adam.mortara@bartlit-beck.com
`matthew.ford@bartlit-beck.com
`
`
`
`
`24311221.1
`
`
`
`

`

`Case 1:14-cv-01432-LPS Document 233 Filed 11/04/19 Page 10 of 10 PageID #: 15630
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`
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`John M. Hughes, Esquire
`Katherine L.I. Hacker, Esquire
`Nosson D. Knobloch, Esquire
`Bartlit Beck Herman Palenchar & Scott LLP
`1801 Wewatta, Suite 1200
`Denver, CO 80202
`john.hughes@bartlit-beck.com
`kat.hacker@bartlit-beck.com
`nosson.knobloch@bartlit-beck.com
`
`Attorneys for Plaintiff
`
`
`
` YOUNG CONAWAY STARGATT
` & TAYLOR, LLP
`
`
`
`
`
`
`
`
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`
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`
`
`
`
`
`
`
`/s/ Adam W. Poff
`Adam W. Poff (No. 3990)
`Pilar G. Kraman (No. 5199)
`Rodney Square
`1000 North King Street
`Wilmington, Delaware 19801
`(302) 571-6600
`apoff@ycst.com
`pkraman@ycst.com
`
`Attorneys for Defendants Samsung Electronics Co.,
`Ltd., Samsung Semiconductor,
`Inc., Samsung
`Electronics America, Inc., and Samsung Austin
`Semiconductor, LLC
`On Behalf of All Defendants
`
`24311221.1
`
`2
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`