Case 5:18-cv-07581-LHK Document 31-12 Filed 03/04/19 Page 1 of 36
`Case 5:18-cv-07581-LHK Document 31-12 Filed 03/04/19 Page 1 of 36
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`EXHIBIT 12
`EXHIBIT 12
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`EXHIBIT 12
`EXHIBIT 12
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`Case 5:18-cv-07581-LHK Document 31-12 Filed 03/04/19 Page 1 of 36
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`EXHIBIT 12
`EXHIBIT 12
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`EXHIBIT 12
`EXHIBIT 12
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`
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`Case 5:18-cv-07581-LHK Document 31-12 Filed 03/04/19 Page 2 of 36
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`Silicon-Correlated Voltus Power Signoff
`of Embedded FPGA IPs on Advanced
`FinFET Nodes
`
`Dipal Patel, Principal Hardware/CAD Design Engineer
`Nitish Natu, Sr Hardware Design Engineer
`
`
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`Case 5:18-cv-07581-LHK Document 31-12 Filed 03/04/19 Page 3 of 36
`
`Agenda
`
`• What is Embedded FPGA IP ?
`
`• Overview of Flex Logix eFPGA flow
`
`• How to intergrade eFPGA in your Design ?
`
`• Why Power Signoff is important to for eFPGA ?
`
`• Voltus Signoff flow
`• Dynamic Power calculation and SI co-relation
`IR drop
`•
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`4/6/2018
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`©2016 Flex Logix Technologies, Inc.
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`Case 5:18-cv-07581-LHK Document 31-12 Filed 03/04/19 Page 4 of 36
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`What is Embedded FPGA IP ?
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`4/6/2018
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`©2016 Flex Logix Technologies, Inc.
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`Case 5:18-cv-07581-LHK Document 31-12 Filed 03/04/19 Page 5 of 36
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`Make ICs Flexible
`
`• Reconfigure RTL in your SoC/MCU anytime
`▪ Keep up with changing algorithms, industry standards, and
`customer requests
`▪ One chip can serve multiple applications
`▪ Longer chip life, higher ROI
`• EFLX® Embedded FPGA IP cores and software
`▪ Any size and process
`▪ Software to program it
`
`EFLX
`Embedded
`FPGA
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`4/6/2018
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`©2016 Flex Logix Technologies, Inc.
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`Case 5:18-cv-07581-LHK Document 31-12 Filed 03/04/19 Page 6 of 36
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`Everything You Need in an eFPGA
`✓High density similar to full custom FPGA
`✓High performance similar to full custom FPGA
`✓Silicon Proven in TSMC 16, 28, 40; port in 6 mo.s
`✓Any size array in days using proven building blocks
`✓Options for DSP and RAM
`✓Compatible with your metal stack & voltage
`✓Software programming tools with GUI
`✓Timing files extracted from GDS & for all corners
`✓DFT fault coverage >98%
`✓Special 100x speed test mode
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`4/6/2018
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`©2016 Flex Logix Technologies, Inc.
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`5
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`Case 5:18-cv-07581-LHK Document 31-12 Filed 03/04/19 Page 7 of 36
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`3 Programmable Building Blocks in a
`Programmable Interconnect Network
`
`LOGIC
`
`I/O
`
`DSP
`
`DSP MAC
`- Pre adder
`- 22x22 multiplier
`- Multiplier can be
`configured as two
`11x11 for AI/ML
`- accumulator
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`4/6/2018
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`©2016 Flex Logix Technologies, Inc.
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`6
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`To Interconnect Network
`
`Reconfigurable
`Building Block
`
`3
`
`3
`
`3
`
`3
`
`Output Selection
`
`FFFF
`
`FFFF
`
`FFFF
`
`FFFF
`
`2
`
`2
`
`2
`
`2
`
`Cout
`
`Data Mutiplexer
`Carry Arithmetic
`
`Cin
`
`CE/Reset
`
`6-in 2-out
`Look-up-table
`LUT
`
`6-in 2-out
`Look-up-table
`LUT
`
`6-in 2-out
`Look-up-table
`LUT
`
`6-in 2-out
`Look-up-table
`LUT
`
`Aux. Input
`
`2
`
`2
`
`2
`
`2
`
`2
`
`6
`
`6
`
`6
`
`6
`
`4
`
`From Interconnect Network
`
`∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙
`∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙
`∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙
`∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙
`
`RBB L
`
`RBB M
`
`RBB L
`
`∙ ∙
`∙ ∙
`
`RBB L
`
`DSP
`
`RBB M
`
`DSP
`
`RBB L
`
`∙ ∙
`∙ ∙
`
`∙ ∙
`∙ ∙
`
`∙ ∙
`∙ ∙
`
`∙ ∙
`∙ ∙
`
`∙ ∙
`∙ ∙
`
`∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙
`∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙
`∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙
`∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙
`
`
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`Case 5:18-cv-07581-LHK Document 31-12 Filed 03/04/19 Page 8 of 36
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`An FPGA is 20% logic, 80% interconnect
`
`O(N 2) worst-case
`complexity
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`4/6/2018
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`©2016 Flex Logix Technologies, Inc.
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`7
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`CLB
`LUT LUT
`
`LUT LUT
`
`CLB
`LUT LUT
`
`LUT LUT
`
`
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`Case 5:18-cv-07581-LHK Document 31-12 Filed 03/04/19 Page 9 of 36
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`XFLX™ Patented (3) Interconnect =
`Density & Fewer Metal Layers
`
`O(N∙logN) Boundary-less Radix Interconnect Network
`
`O(N2)
`
`O(N∙logN)
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`4/6/2018
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`©2016 Flex Logix Technologies, Inc.
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`8
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`CE
`
`1 C
`
`E
`
`2 C
`
`E
`
`3 C
`
`E
`
`4 C
`
`E
`
`5 C
`
`6 C
`
`E
`
`E
`
`7 C
`
`E
`8
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`Case 5:18-cv-07581-LHK Document 31-12 Filed 03/04/19 Page 10 of 36
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`XFLX Enables Denser FPGA + Fewer Metal Layers
`
`LUT Logic
`(21%)
`
`Traditional Mesh Interconnect
`(79%)
`
`LUT Logic
`(37%)
`
`XFLX Interconnect
`(63%)
`
`45% smaller
`under same assumption
`
`▪ XFLX needs just 5/6/7-metal
`layers for 40/28/16nm nodes
`▪ So XFLX is compatible with
`most metal stacks
`
`Mesh XFLX
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`4/6/2018
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`©2016 Flex Logix Technologies, Inc.
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`Case 5:18-cv-07581-LHK Document 31-12 Filed 03/04/19 Page 11 of 36
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`EFLX4K eFPGA with ArrayLinx™
`
`EFLX 4K is a
`complete eFPGA
`
`EFLX 4K
`Logic
`4K LUT4
`>1000 I/O
`
`EFLX 4K
`DSP
`3K LUT4
`40 MACs 22x22
`>1000 I/O
`
`ArrayLinx, a top level
`patented interconnect,
`enables EFLX4Ks
`to tile to make
`larger eFPGA arrays in
`days with no GDS change
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`4/6/2018
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`©2016 Flex Logix Technologies, Inc.
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`Case 5:18-cv-07581-LHK Document 31-12 Filed 03/04/19 Page 12 of 36
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`Overview of Flex Logix eFPGA flow
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`4/6/2018
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`©2016 Flex Logix Technologies, Inc.
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`Case 5:18-cv-07581-LHK Document 31-12 Filed 03/04/19 Page 13 of 36
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`How to Map your RTL to EFLX array?
`
`• Determine resources needed floorplan specification
`• Analyze worst-case timing, run placement & routing
`• Generate the bit file for EFLX
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`4/6/2018
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`©2016 Flex Logix Technologies, Inc.
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`12
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`ARM/MIPS...
`
`Your SoC
`
`EFLX
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`
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`Case 5:18-cv-07581-LHK Document 31-12 Filed 03/04/19 Page 14 of 36
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`EFLX IP – Resource / Floorplan Specification
`
`Customer synthesizes RTL to estimate resources and specify floorplan
`
`Flex Logix provides EFLX IP (GDS) for the customer floorplan
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`4/6/2018
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`©2016 Flex Logix Technologies, Inc.
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`13
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`Customer
`
`Flex Logix
`
`EFLX Synthesis
`
`Customer
`Design
`
`Synopsys
`Synplify
`
`EFLX FPGA
`Mapping
`
`Resource +
`Timing +
`Power
`Estimation
`
`EFLX
`Floorplan
`
`
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`Case 5:18-cv-07581-LHK Document 31-12 Filed 03/04/19 Page 15 of 36
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`How to integrate EFLX Cores in your SoC?
`
`▪ eFPGA is Digital IP, It can be used in wide range of applications
`• Low power or high performance
`• Networking: programmable parsers, network protocols, security protocols and storage
`protocols
`• Data Center Acceleration
`• Wireless Base Station DFE (digital front end)
`• MCU: reconfigurable I/O; I/O processing to offload the MPU; reconfigurable accelerators
`• SoC: I/O Mux; reconfigurable I/O; reconfigurable accelerators
`• SSD: programmable timing and ECC
`• Aerospace/Defense: integrated FPGA is smaller, lighter, lower power and can be
`implemented in rad-hard processes and/or trusted fabs
`
`▪ It is critical to connect eFPGA IP with sufficient power at SOC for targeted
`application
`• We make sure we have robust power grid up-to EFLX IP top layer for worst case testcases
`
`▪ It can share power grid with other SOC component or it could have separate
`power supply
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`4/6/2018
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`©2016 Flex Logix Technologies, Inc.
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`14
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`Case 5:18-cv-07581-LHK Document 31-12 Filed 03/04/19 Page 16 of 36
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`How to integrate EFLX Cores in your SoC?
`
`Step1
`
`Step2
`
`Step3
`
`Step4
`
`Step5
`
`Plan your SOC size, RTL, placement and usage of EFLX cores
`
`EFLX Synthesis – determine # of EFLX cores needed
`
`Floorplan your SOC – with LEF for EFLX cores
`
`SOC chip finishing – integrate GDS of EFLX cores
`
`SOC Simulation – sign-off with EFLX timing and EM/IR models
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`4/6/2018
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`©2016 Flex Logix Technologies, Inc.
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`15
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`Plan your SOC
`
`EFLX Synthesis
`Synopsys
`Synplify
`
`EFLX FPGA
`Mapping
`
`# EFLX Cores
`+ reports (PPA)
`
`Floorplan SOC
`Use
`EFLX LEF
`SOC
`PnR
`
`Integrate EFLX
`
`EFLX GDS
`
`SOC chip
`finishing
`
`SOC Chip
`Simulation
`
`
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`Case 5:18-cv-07581-LHK Document 31-12 Filed 03/04/19 Page 17 of 36
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`Power View Delivery
`
`▪ EFLX IP power connectivity recommendation to customer
`
`▪ We provide power estimation model for early rail analysis
`
`▪ DEF/Lib/PGV/Verilog to run flat power / IR at SOC level
`
`▪ We are evaluating cadence IP-PGV view as standard Power
`Grid delivery
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`4/6/2018
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`©2016 Flex Logix Technologies, Inc.
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`16
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`Case 5:18-cv-07581-LHK Document 31-12 Filed 03/04/19 Page 18 of 36
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`Voltus Signoff Flow
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`4/6/2018
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`©2016 Flex Logix Technologies, Inc.
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`17
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`Case 5:18-cv-07581-LHK Document 31-12 Filed 03/04/19 Page 19 of 36
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`Power estimation is critical for eFPGA IP
`
`SDC requires for
`correct twf
`generation
`
`Dynamic vector
`based analysis
`
`- Make sure activity
`annotation is
`correctly
`- Use this activity to
`analyze design
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`4/6/2018
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`©2016 Flex Logix Technologies, Inc.
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`18
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`Read Design
`( Verilog / LEF/ DEF / SDC )
`
`CCSP
`Libery power mode
`
`SPEF
`Interconnect Parasitics
`
`VCD
`Activity File
`
`Voltus
`
`set_power_analysis_mode
`
`Activity Annotation
`
`Power Report
`
`
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`Case 5:18-cv-07581-LHK Document 31-12 Filed 03/04/19 Page 20 of 36
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`Power Consumption
`
`▪ Use CCSP library models for accuracy
`
`▪ VCD (Value Change Dump ) based dynamic power calculation
`
`▪ Generate gate level VCD for different design style
`• Cons : High Runtime
`– EFLX Complier generated bitstream simulation
`• Pros : High Accuracy
`
`4/6/2018
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`©2016 Flex Logix Technologies, Inc.
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`19
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`Case 5:18-cv-07581-LHK Document 31-12 Filed 03/04/19 Page 21 of 36
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`VCD Generation
`
`EFLX Complier PnR Flow
`
`• Run RTL to bitstream flow
`
`• Simulate bitstream with
`gate level EFLX Array
`netlist
`
`• Dump VCD for design
`active duration
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`4/6/2018
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`©2016 Flex Logix Technologies, Inc.
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`20
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`Case 5:18-cv-07581-LHK Document 31-12 Filed 03/04/19 Page 22 of 36
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`EFLX Array power consumption
`
`• We calculate power Tile
`by Tile
`
`• Total power consumption
`is just addition of
`individual tiles
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`4/6/2018
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`©2016 Flex Logix Technologies, Inc.
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`21
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`Case 5:18-cv-07581-LHK Document 31-12 Filed 03/04/19 Page 23 of 36
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`Power estimation is critical for eFPGA IP
`
`•
`
`How do we estimate power
`for customer design- RTL ?
`
`1
`
`▪
`
`▪
`
`Power reports from
`experimental designs help us to
`find relation between utilization
`and Power.
`
`eFPGA complier reports
`utilization and frequency of
`operation for given RTL
`
`▪ Estimate power based eFPGA
`complier utilization report
`
`2
`
`report_power -outfile power.rpt
`-sort total -cell * -no_wrap
`
`Use activity annotation to
`analyze design
`
`4/6/2018
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`©2016 Flex Logix Technologies, Inc.
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`22
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`Case 5:18-cv-07581-LHK Document 31-12 Filed 03/04/19 Page 24 of 36
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`eFPGA Automated Validation Platform
`
`T16FF+ EFLX-150 Chip
`
`Validation Setup
`
`T16FFC EFLX4K Chip
`
`Software Platform:
`controls validation setup
`to characterize EFLX-150 IP
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`4/6/2018
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`©2016 Flex Logix Technologies, Inc.
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`23
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`Start
`
`Load Pattern;
`Set Temp./Voltage/Freq.
`
`Measure on-chip PVT
`(by PVT monitor)
`
`Adjust Temperature
`
`Temp. Converged?
`
`Yes
`
`Measure Performance/Power
`(for each Volt/Freq.)
`
`Temp. Sweep Done?
`
`Yes
`
`Pattern Sweep Done?
`
`No
`
`Yes
`
`Finish
`
`No
`
`No
`
`
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`Case 5:18-cv-07581-LHK Document 31-12 Filed 03/04/19 Page 25 of 36
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`EFLX-150 16FF+ Validation Chip
`
`•
`
`Validation Chip contains:
`2 EFLX-150 FPGA cores
`•
`16FF+
`•
`5 metal routing layers
`•
`dense M4/M5 power
`•
`gird
`• mesh clock
`5 dual ported 1028x72
`SRAM
`• Used to test data
`between EFLX –SRAM
`• Used as patter
`generator/checker
`2 PVT monitors to measure
`on-die
`Process/voltage/tempera
`•
`ture
`1 on-chip PLL – 1+GHz
`
`•
`
`•
`
`3x2
`EFLX-100
`
`PLL
`
`SRAM
`
`SRAM
`
`SRAM
`
`2x2
`EFLX-100
`
`PVT
`Monitor
`
`SRAM
`
`SRAM
`
`PVT
`Monitor
`
`3x2 Array, 2x2 Array
`
`Dual port SRAM, PVT Monitor, On-chip PLL
`
`4/6/2018
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`©2016 Flex Logix Technologies, Inc.
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`Case 5:18-cv-07581-LHK Document 31-12 Filed 03/04/19 Page 26 of 36
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`EFLX-150 16FF+ Power Analysis 1x1
`
`• Power analysis: Using dynamic vector-based simulations
`• Must have high LUT utilization, high freq. & high activity factor (AF)
`• Leakage quantified @ FFG(NP), 125°C, VDD+10%
`
`Dynamic Vector -based
`Voltus Simulation Results
`LUT Utilization 96%
`
`Total Dynamic Power (mW)
`sum (A+B+C)
`
`Internal (mW)
`(A)
`
`Leakage (mW)
`(B)
`
`Switching (mW)
`(C)
`
`TT
`0.8V
`85°C
`
`38.1
`
`FFGNP
`0.88V
`0°C
`
`40.91
`
`12.11
`
`11.06
`
`1.35
`
`24.63
`
`0.17
`
`29.6
`
`FFGNP
`0.88V
`125°C
`
`83.22
`
`40.16
`
`12.66
`
`30.39
`
`From Voltus simulations of EFLX-150 in TSMC 16FF+,
`with 96% LUT utilization at 800MHz
`
`4/6/2018
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`©2016 Flex Logix Technologies, Inc.
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`Case 5:18-cv-07581-LHK Document 31-12 Filed 03/04/19 Page 27 of 36
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`EFLX-150 16FF+ Power Co-relation for 2x2
`
`Single Stage Control
`Dynamic Current (mA) vs. Freq(GHz)
`
`280
`260
`240
`220
`200
`180
`160
`140
`120
`100
`80
`60
`40
`
`220
`200
`180
`160
`140
`120
`100
`80
`60
`40
`20
`0
`
`0.5
`
`1
`
`1.5
`
`Silicon (Dyn) current @85C (mA)
`
`Simulated (Dyn) current @85C (mA)
`
`Single Stage Control
`Dynamic Current (mA) vs. Freq(GHz)
`
`0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
`
`1
`
`1.1 1.2 1.3 1.4 1.5
`
`dyn current @85C (mA)
`
`dyn current @ 125C (mA)
`
`GHz
`
`GHz
`
`TEST DESIGN_1 : Single Stage Control Logic : 2x2 85C -
`Silicon
`Leakage
`Current
`7.12
`6.33
`5.48
`
`Dynamic
`Current
`79.61
`157.14
`231.62
`
`Total Current
`86.73
`163.47
`237.10
`
`Freq (GHz)
`0.5
`1
`1.5
`
`TEST DESIGN_1 : Single Stage Control Logic: 2x2 85C -
`Voltus
`Leakage
`Current
`5.86
`5.86
`5.86
`
`Dynamic
`Current
`89.64
`179.27
`264.08
`
`Total Current
`95.50
`185.12
`269.94
`
`Freq (GHz)
`0.5
`1
`1.5
`
`• Silicon shows good co-relation with
`Voltus power number
`• Dynamic current (measured ) scales
`linearly with frequency
`• Chart shows dynamic current at 85
`degC and 125 degC
`
`4/6/2018
`
`©2016 Flex Logix Technologies, Inc.
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`26
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`Case 5:18-cv-07581-LHK Document 31-12 Filed 03/04/19 Page 28 of 36
`
`EFLX200K Validation Chip TSMC16FFC
`
`• Validation report available
`• 7x7 Array
`– 14 EFLX4K DSP cores
`– 35 EFLX4K Logic cores
`– 114,240 6-LUTs (~183K LUT4s)
`– 560 22x22 MACs
`• Multiple SRAM blocks, PLL
`& PVT monitors for testing
`>1GHz to validate all specs
`over temperature and
`voltage
`
`4/6/2018
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`©2016 Flex Logix Technologies, Inc.
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`27
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`
`
`45
`
`25
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`5
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`Case 5:18-cv-07581-LHK Document 31-12 Filed 03/04/19 Page 29 of 36
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`EFLX4K 16FFC Power Co-relation for 1x1
`
`TEST_DESIGN_1
`Dynamic Current (mA) per 100 MHz vs.
`Temperature
`
`90.8%
`Utilization
`884 MHz
`
`TEST_DESGIN_1 1x1 85C - Silicon
`Single Stage Control Logic
`Dynamic
`Current
`127.5
`159.75
`200
`
`Leakage Current
`5.10
`39.80
`132.65
`
`Total Current
`132.60
`199.55
`332.65
`
`25 degC
`85 degC
`125 degC
`
`25 degC
`
`85 degC
`
`125degC
`
`Silicon (Dyn) current
`
`Simulated (Dyn) current
`
`TEST_DESIGN_1 1x1 85C - Voltus to 0.8V
`Dynamic
`Current
`131.25
`152.50
`
`Leakage Current
`3.60
`32.30
`
`Temerature
`25 degC
`85 degC
`
`Total Current
`134.85
`184.80
`
`79.2.%
`Utilization
`694Mhz
`
`25 degC
`85 degC
`
`TEST_DESIGN_2 1x1 85C - Silicon
`Network Package Processor
`Dynamic
`Current
`17.2
`30
`
`Leakage Current
`5.10
`39.80
`
`Total Current
`22.30
`69.80
`
`TEST_DESIGN_2 1x1 85C - Voltus to 0.8V
`Dynamic
`Current
`19.25
`22.00
`
`Leakage Current
`3.60
`32.30
`
`Temperature
`25 degC
`85 degC
`
`4/6/2018
`
`©2016 Flex Logix Technologies, Inc.
`
`Total Current
`22.85
`54.30
`
`28
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`Case 5:18-cv-07581-LHK Document 31-12 Filed 03/04/19 Page 30 of 36
`
`Tile (EFLX-150 / EFLX-4K) IR Flow
`
`Total instances in design:
`EFLX-150: 49063
`EFLX4K :
`1239118
`
`4/6/2018
`
`©2016 Flex Logix Technologies, Inc.
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`29
`
`Read EFLX Tile Design
`( Verilog / LEF/ DEF )
`
`Power Grid Views
`
`set virtual sources
`
`set_power_data
`(read ptiavg)
`
`Voltus
`
`set_rail_analysis_mode
`
`Analyze_rail reports
`
`Power Plots
`
`IR plots
`
`Resistance Plots
`
`Jrms plots
`
`
`
`Case 5:18-cv-07581-LHK Document 31-12 Filed 03/04/19 Page 31 of 36
`
`Array IR Flow
`
`set_power_data -
`format current {
`file.ptiavg } -instance
`CORE/TILE_N
`
`4/6/2018
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`©2016 Flex Logix Technologies, Inc.
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`30
`
`Read Array Design
`(read_def or specify_def)
`
`Power Grid Views
`
`Voltus
`
`set_power_pads
`
`set_rail_analysis_mode
`
`Tile1 Power
`
`Tile2 Power
`
`Tile3 Power
`
`. . . . .
`
`. . .
`
`Tile4 Power
`
`TileN Power
`
`Analyze_rail reports
`
`Power Plots
`
`IR plots
`
`Resistance Plots
`
`Jrms plots
`
`
`
`Case 5:18-cv-07581-LHK Document 31-12 Filed 03/04/19 Page 32 of 36
`
`16FF+ Validation Chip IR Drop
`
`Validation Chip IR results
`
`2
`
`0
`
`2
`
`0
`
`3
`
`1
`
`3
`
`1
`
`3
`
`0
`
`4
`
`1
`
`5
`
`2
`
`3
`
`0
`
`4
`
`1
`
`5
`
`2
`
`•
`
`•
`
`IR on VDD (EFLX) ~54.2mV ( 6.1%)
`FFGNP, 0.88V, 125C
`•
`• Most of the IR drop on VDD (EFLX)
`from power pad to EFLX core -due to
`limited power pads on 3 sides of
`Validation Chip
`
`IR on VSS (EFLX) ~ 9mV (1.02%)
`FFGNP, 0.88V, 125C
`•
`• Minimial IR drop on VSS (EFLX) –due
`to solid VSS power pads on all 4
`sides of EFLX FPGA
`
`4/6/2018
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`©2016 Flex Logix Technologies, Inc.
`
`31
`
`
`
`Case 5:18-cv-07581-LHK Document 31-12 Filed 03/04/19 Page 33 of 36
`
`16FFC Validation Chip IR Drop
`
`42
`
`43
`
`44
`
`45
`
`46
`
`47
`
`48
`
`TEST_DESIGN_1:
`
`Network package
`processor on Tile
`48 run at
`500Mhz/tt/0p8v/
`85C
`
`35
`
`36
`
`37
`
`38
`
`39
`
`40
`
`41
`
`28
`
`29
`
`30
`
`31
`
`32
`
`33
`
`34
`
`21
`
`22
`
`23
`
`24
`
`25
`
`26
`
`27
`
`14
`
`15
`
`16
`
`17
`
`18
`
`19
`
`20
`
`7
`
`0
`
`8
`
`1
`
`9
`
`2
`
`10
`
`11
`
`12
`
`13
`
`3
`
`4
`
`5
`
`6
`
`4/6/2018
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`©2016 Flex Logix Technologies, Inc.
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`32
`
`
`
`Case 5:18-cv-07581-LHK Document 31-12 Filed 03/04/19 Page 34 of 36
`
`16FFC Validation Chip IR Drop
`
`TEST_DESIGN_2:
`
`Single Stage
`Control logic on
`Tile 48 run at
`800Mhz/tt/0p8v/8
`5C
`
`42
`
`43
`
`44
`
`45
`
`46
`
`47
`
`48
`
`35
`
`36
`
`37
`
`38
`
`39
`
`40
`
`41
`
`28
`
`29
`
`30
`
`31
`
`32
`
`33
`
`34
`
`21
`
`22
`
`23
`
`24
`
`25
`
`26
`
`27
`
`14
`
`15
`
`16
`
`17
`
`18
`
`19
`
`20
`
`7
`
`0
`
`8
`
`1
`
`9
`
`2
`
`10
`
`11
`
`12
`
`13
`
`3
`
`4
`
`5
`
`6
`
`4/6/2018
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`©2016 Flex Logix Technologies, Inc.
`
`33
`
`
`
`Case 5:18-cv-07581-LHK Document 31-12 Filed 03/04/19 Page 35 of 36
`
`Summary for Voltus co-relation
`
`• Voltus simulation shows good correlation with measured
`silicon (<10%) across Voltage and Temperature
`
`• FlexLogix has silicon proven eFPGA EFLX-150 and EFLX4K
`in 16FFP/16FFC
`
`• EFLX-IP is fully functional / power correlated across a
`multiple RTL applications across Arrays
`
`4/6/2018
`
`©2016 Flex Logix Technologies, Inc.
`
`34
`
`
`
`Case 5:18-cv-07581-LHK Document 31-12 Filed 03/04/19 Page 36 of 36
`
`Cadence Support Acknowledgement
`
`We would like to thank Jin Wang from Cadence for his
`support
`
`4/6/2018
`
`©2016 Flex Logix Technologies, Inc.
`
`35
`
`
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