Case 5:18-cv-07581-LHK Document 31-10 Filed 03/04/19 Page 1 of 8
`Case 5:18-cv-07581-LHK Document 31-10 Filed 03/04/19 Page 1 of 8
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`EXHIBIT 10
`EXHIBIT 10
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`EXHIBIT 10
`EXHIBIT 10
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`Case 5:18-cv-07581-LHK Document 31-10 Filed 03/04/19 Page 2 of 8
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`eFPGA IP Density, Portability & Scalability
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`There are multiple eFPGA suppliers in the market today: Achronix, Adicsys, Efinix, Flex Logix™,
`Menta, QuickLogic.
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`There are 3 different business models and engineering approaches to eFPGA which you should
`understand to assess how it will impact your success in using their eFPGA IP and their viability
`as a supplier long term.
`
`
`
`
`Type of eFPGA
`company
`
`Design
`Approach
`
`Interconnect
`
`LUT Size
`Design
`
`Different sizes
`
`Validation Chip
`
`Implications Relative Density
`(1x is highest)
`Metal Stack
`
`Different Sizes
`
`GDS Delivery in
`your process,
`metal stack, size
`Risk
`
`FPGA Chip
`Companies
`Offering eFPGA
`Mesh
`
`4-input-LUT
`Full-custom
`Hard IP
`
`Modular custom
`construction
`None made
`public
`
`1x
`
`GDS changes:
`must re-route, if
`possible, for
`each metal stack
`GDS changes;
`smallest size
`unknown; up to
`1M LUTs
`Longest if any
`modifications
`required
`Significant GDS
`changes for
`every metal
`stack/process
`variation/array
`size
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`Soft-IP
`Companies
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`Flex Logix
`
`Mesh
`
`Variable?
`RTL IP or
`Standard Cell
`Hard IP
`Software
`generator?
`None made
`public
`
`0.3-0.5x
`
`?
`
`GDS changes;
`<10K LUTs
`
`Fast
`
`Not every array
`size is validated
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`Mixed Radix
`Hierarchical-Mesh
`6-input-LUT
`Standard Cell
`Hard IP
`
`Tiling with no GDS
`change
`Proves each eFPGA
`IP core in silicon and
`validates over
`temperature/voltage
`1x
`
`Compatible with
`almost all metal
`stacks with no GDS
`change
`No GDS change; 100
`to 200K LUTs with
`roadmap to 800K
`LUTs
`Fast
`
`GDS is proven in
`silicon and works
`across almost all
`metal stacks,
`process variations
`and array sizes
`
`Copyright 2017, Flex Logix Technologies, Inc. Flex Logix and EFLX are trademarks of Flex Logix.
`Achronix, Adicsys, Menta, QuickLogic, Efinix are trademarks of their respective owners.
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`

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`Case 5:18-cv-07581-LHK Document 31-10 Filed 03/04/19 Page 3 of 8
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`FPGA Chip Companies Providing eFPGA IP
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`FPGA chip companies generally build a new generation of FPGAs every ~3 years when there is a
`major advance in process technology.
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`They pick one foundry, one node, one variation of that node and do full-custom circuit design
`with typically the maximum or near-maximum number of metal layers in order to get the
`highest density FPGA they can. It takes them most of the 3 years to do the complex
`engineering required.
`
`Since FPGA customers want a range of sizes and some variation in the ratio of options like
`DSP/RAM, the FPGA chip companies will construct their FPGAs from some modular pieces: a
`block of LUTs, a DSP block, and typically a block-RAM (dual port). The 3-10 different sizes of
`the FPGA are put together from the blocks with circuit designers tuning the mesh interconnects
`and I/O’s for the array size.
`
`Their business model is to optimize to make the best FPGAs. What happens when they provide
`embedded FPGA IP?
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`1st There are typically dozens of metal stacks that a foundry supports. The bottom 4-7 layers,
`depending on the process, are generally common because of foundation IP like standard cells
`and memories. Above that, some customers want fewer layers for lower cost for simpler
`circuits; others want maximum layers for large, complex circuits. There are many variations of
`thicknesses/widths by layer to optimize for each customers design. FPGA companies usually
`design their chip with maximum or near-maximum metal layers which significantly limits the
`supported metal stacks to one or two. If a customer wants a different metal stack, they have to
`re-route. If the customer wants the same number of metal layers but with variations in
`thickness for some of the layers, timing will have to be redone and likely re-routing of the
`whole design along with circuit changes to offset timing/DRC issues with thicker/thinner metal.
`If the customer wants fewer metal layers, it may be impossible: presumably the FPGA chip uses
`the number of layers it does because it was not possible to route with fewer layers. The time to
`do all this work is likely 4-6 months with significant engineering expense.
`
`2nd Foundries continually improve each of their process nodes for yields, fewer metal layers and
`shrinks with a new variation every year or so. Since FPGA chip companies do full-custom
`design, they will need to re-simulate and likely re-design multiple portions of their chip to
`support the incremental changes to the process. (Whereas standard cells are generally useable
`across 2 or 3 incremental variations because they use less aggressive logic design rules AND the
`
`Copyright 2017, Flex Logix Technologies, Inc. Flex Logix and EFLX are trademarks of Flex Logix.
`Achronix, Adicsys, Menta, QuickLogic, Efinix are trademarks of their respective owners.
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`Case 5:18-cv-07581-LHK Document 31-10 Filed 03/04/19 Page 4 of 8
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`foundries try to keep the standard cells the same for their customers to migrate easily to the
`newer process variation).
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`3rd Supporting a range of array sizes and options (DSP, RAM) requires custom engineering: the
`blocks may be modular, but the connections between them and most importantly the
`interconnect will need to be redone especially since the amount of interconnects grows with N2
`for mesh interconnect designs. And the I/O ring is custom for each different array size.
`
`4th Since the GDS changes for every metal stack and array size and process variation, it is
`uneconomical to do a validation chip for every GDS change.
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`
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`Figure 1: Traditional 2D-Mesh Interconnect diagram illustrates the non-uniformity of a mesh network across the
`FPGA. Any change to the area or configuration will require re-implementing the interconnect, effectively creating a
`new embedded FPGA implementation.
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`The FPGA chip companies have been in business >10 years but offer eFPGA on only a few
`nodes.
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`The engineering investment to support different array sizes and options and metal stacks within
`an existing node/variation are significant; the engineering investment to port a full-custom
`design to a new node are much greater (that’s why FPGA companies usually only do a
`generation every few years).
`
`
`Copyright 2017, Flex Logix Technologies, Inc. Flex Logix and EFLX are trademarks of Flex Logix.
`Achronix, Adicsys, Menta, QuickLogic, Efinix are trademarks of their respective owners.
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`Case 5:18-cv-07581-LHK Document 31-10 Filed 03/04/19 Page 5 of 8
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`This is probably why the big FPGA chip companies don’t bother with eFPGA: it is a costly
`distraction to their primary business with, for them, a low return on investment.
`
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`Pure eFPGA IP Companies: Soft IP
`
`eFPGA soft IP companies offer a software tool that will generate RTL for an array based on
`inputs such as array size, I/O count, etc. The customer can then use EDA tools with a standard
`cell library to implement the eFPGA in any process – but the density is very low: FPGAs are very
`regular and benefit from structured placement. This approach has some use in test chips or
`very low volume products such as aerospace/defense.
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`One of these companies now offers hard IP on a couple of foundries/nodes. For that company,
`their maximum array size is <<10K and there are only a handful of sizes/option combinations to
`choose from. Density for the smallest arrays is ~0.5x of a full-custom FPGA; and for the largest
`arrays ~1/3 of a full-custom FPGA. Presumably what is happening is the N2 complexity growth
`in interconnect for larger arrays. Their largest array is 2x the LUTs and Flip-Flops of their mid-
`size array, but is ~3x the silicon area! This trend in interconnect complexity growth is probably
`why there are no large arrays offered. The number of metal layers required or the range of
`metal stacks they are compatible with is not public.
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`Each array size is a different design so a validation chip for one does not prove the others.
`Doing a validation chip for each array size is uneconomical.
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`Pure eFPGA Hard IP: Flex Logix
`
`Flex Logix is the youngest of the companies providing eFPGA but offers eFPGA on more process
`nodes/variations (7 foundry and 1 captive) and over a wider range of sizes than any competitor.
`
`We started the company based on Cheng Wang’s revolutionary interconnect which he
`developed working with others at UCLA while doing 5 different FPGA test chips of increasing
`complexity over multiple process nodes prior to starting Flex Logix.
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`In traditional FPGAs, the FPGA fabric is 70-80% interconnect and only 20-30% of the area is
`logic/LUTs.
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`Cheng’s test chips were limited in size by budget suppliers: To get more logic on the chip he
`came up with a new interconnect that was much denser than the traditional mesh. And its’
`complexity grows more slowly than mesh for larger array sizes.
`
`
`Copyright 2017, Flex Logix Technologies, Inc. Flex Logix and EFLX are trademarks of Flex Logix.
`Achronix, Adicsys, Menta, QuickLogic, Efinix are trademarks of their respective owners.
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`Case 5:18-cv-07581-LHK Document 31-10 Filed 03/04/19 Page 6 of 8
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`Figure 2: Illustration of Flex Logix interconnect resulting in a much more efficient interconnect compared to a
`traditional interconnect.
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`Cheng’s interconnect as developed at UCLA was the subject of a paper that won the
`Outstanding Paper Award at ISSCC in 2014 and of a patent recently issued to UCLA, of which
`Flex Logix is the exclusive licensee. Since starting Flex Logix, Cheng has made numerous
`improvements to the interconnect, some of which resulted in two recently issued patents.
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`The end result is that Flex Logix can use standard cells for rapid implementation and portability
`across incremental process variations, while achieving density essentially the same as eFPGA
`from full-custom FPGA chips: the increased density of the interconnect offsets the lesser
`density of the standard cells. The effective density of EFLX eFPGA is further increased by the
`higher utilization we achieve compared to traditional FPGA interconnect.
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`In 40nm our IP is compatible with two variations; in 28nm our IP is compatible with two
`variations; and in 16nm our IP is compatible with 3 variations.
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`Further, Flex Logix’ interconnect does not need maximum metal layers: in 40nm, 28nm and
`16nm our eFPGA IP is compatible with almost all metal stacks.
`
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`
`
`Copyright 2017, Flex Logix Technologies, Inc. Flex Logix and EFLX are trademarks of Flex Logix.
`Achronix, Adicsys, Menta, QuickLogic, Efinix are trademarks of their respective owners.
`
`

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`Case 5:18-cv-07581-LHK Document 31-10 Filed 03/04/19 Page 7 of 8
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`Array Size Scalability
`When we started Flex Logix, we realized in early talks with potential customers that customers
`wanted both silicon proven and a wide range of array sizes. We realized that designing say 10
`different array sizes would mean needing to have 10 different validation chips: this wasn’t
`feasible and not validating in silicon would mean unacceptable risk for the customer.
`
`So Cheng came up with an innovative solution: make an eFPGA IP core which is a complete
`FPGA on its own which can be tiled, without GDS changes, to make a very wide range of array
`sizes.
`
`For example, the EFLX®4K IP core is a
`complete embedded FPGA of 4K
`LUT4s with >600 inputs and >600
`outputs. But the EFLX4K also has a
`top-layer interconnect, not shown in
`the block diagram to the right, which
`automatically extends between cores
`when abutted enabling ~50 array
`sizes up to 200K LUTs. Any array
`configuration needed for a chip can
`be generated within a few days: most
`of the time is generating the .LIB files
`across numerous process corners,
`since timing is done at the array
`level.
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`Figure 3: Diagram of an EFLX Array. By arraying a validated embedded FPGA core, arrays of different sizes are
`validated by design thus eliminating risks associated with new embedded FPGA implementations on a given process.
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`Copyright 2017, Flex Logix Technologies, Inc. Flex Logix and EFLX are trademarks of Flex Logix.
`Achronix, Adicsys, Menta, QuickLogic, Efinix are trademarks of their respective owners.
`
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`Case 5:18-cv-07581-LHK Document 31-10 Filed 03/04/19 Page 8 of 8
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`We have an EFLX150 core for smaller array requirements; and someday we can implement an
`EFLX16K core when customers need up to 800K (or larger) LUT4 arrays.
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`Plus we have two versions of each IP core: all Logic and Logic with ~20% of the area replaced by
`Multiplier-Accumulators: the two versions are exactly the same dimensions so they can be
`intermixed to give customers the ratio of DSP-to-Logic they need.
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`Siicon Proven IP for Your Node/Variation, Your Metal Stack and Your Array Size
`When Flex Logix ports an EFLX IP core to a new process, it builds a validation chip with at least a
`2x2 array (this verifies that the top level interconnect extension works on all 4 sides) on a die
`with PLLs, PVTs and attached SRAM so testing can be done at high speeds (>1GHz on 16nm), at
`exact voltages and extreme temperatures to validate silicon function and performance. We
`have built 4 validation chips so far in 40nm, 28nm and 16nm (two: one for the EFLX150 and one
`for EFLX4K).
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`Since an EFLX array is built by abutting EFLX cores with no GDS
`changes, the EFLX Array you get is known good for your size and
`your node/variation.
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`We have demonstrated this by fabricating a 7x7 array of EFLX4K
`cores (EFLX200K = 200K LUT4s) in 16nm which is in validation
`now. It is fully functional, was demonstrated at ARM TechCon
`running our Flex Micro architecture. Now performance
`measurements are being done over temperature and voltage.
`
`
`Conclusion
`Flex Logix gives you the highest density, most flexibility on process variations/metal stacks, and
`widest range of array sizes while ensuring the GDS you use has been proven in silicon.
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`We are happy to go into more detail on any of the above analysis.
`
`
`Copyright 2017, Flex Logix Technologies, Inc. Flex Logix and EFLX are trademarks of Flex Logix.
`Achronix, Adicsys, Menta, QuickLogic, Efinix are trademarks of their respective owners.
`
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