Case 5:18-cv-07581-LHK Document 31-1 Filed 03/04/19 Page 1 of 13
`Case 5:18-cv-07581-LHK Document 31-1 Filed 03/04/19 Page 1 of 13
`
`
`
`EXHIBIT 1
`EXHIBIT 1
`
`

`

`Case 5:18-cv-07581-LHK Document 31-1 Filed 03/04/19 Page 2 of 13
`
`Proprietary
`Regular-Geometry Micro-Cells and Design Tools for Butterfly FPGA
`Proposal Number: D102-0003-0305, Topic Number: SB102-003 (DARPA)
`
`
`
`1. Identification and Significance of the Problem or Opportunity
`
`1.1 Objective: In this project, we plan to prepare a Phase I feasibility study of integrated circuit micro-
`cells based on regular geometry for use in our proprietary hierarchical FPGA interconnect
`architecture. The objective of the overall 3-phase FPGA project is to substantially reduce energy and
`cost of low-volume digital signal processing by using hierarchically routed interconnect, regular-
`geometry micro-cells, and associated tool-flow for routing and hardware mapping. Figure 1
`illustrates our overall vision for the project. While the FPGA architecture and associated tool-flow for
`design and algorithm mapping reduces cost in design time and chip metrics (the focus of Phases II
`and III), enforcing regular layout geometries at the cell level provides additional reduction in the
`manufacturing cost, particularly in advanced technology nodes such as 32nm and below. This
`proposal will thus evaluate the design of regular layout cells for FPGA design and compare their
`circuit and cost metrics to standard-cell based CMOS design. Our team is formed from an industrial
`innovator (Dr. Venkat Konda) who has strong patent portfolio in routing networks (Phase II work), and
`academic leaders in the areas of regular geometry circuit design (Prof. Puneet Gupta), and energy-
`efficient architecture design and associated tool-flows (Prof. Dejan Markovic). Our objective is to
`develop low-cost digital signal processing hardware and tool-flows for emerging markets such
`as wireless and sensor applications where cost and power consumption are key concerns.
`
`Figure 1: Regular-fabric micro-cells and blocks (output of Phase I) will be used to route Konda’s
`hierarchical interconnect architecture (output of Phase II) and further integrated on a demo FPGA
`chip with supporting mapping tool-flow (output of Phase III) to demonstrate significant improvements
`in chip size, performance, power, and also manufacturing cost.
`
`
`
`
`
`1
`
`Phase I: Regular geometry
`micro-cells and macro-blocks
`
`Phase II: Routing tools
`
`LUTs
`
`1 k
`
`100 k
`
`2D
`Mesh
`
`1 M
`
`10 B
`
`Konda
`
`Saving
`
`9,97 k
`
`100x
`
`1.66 M 6,200x
`
`Project Impact
`
`Phase III: FPGA chip demo
`(Tech: 32nm LEAP)
`
`+ mapping
`tool-flow
`
`LUT0
`
`LUT1
`
`LUT2
`
`LUT3
`
`S(0,0)
`
`S(0,1)
`
`S(0,2)
`
`S(0,3)
`
`S(1,0)
`
`S(1,1)
`
`S(1,2)
`
`S(1,3)
`
`Virtex-5
`
`SBIR Goal
`
`Radio DSP
`
`FFT module
`
`Mirco & small UAVs
`
`Satellite DSP
`
`MIMO DSP
`
`10
`100
`1000
`Performance (GOPS)
`
`100W
`
`10W
`
`1W
`
`Power
`
`100mW
`
`

`

`Case 5:18-cv-07581-LHK Document 31-1 Filed 03/04/19 Page 3 of 13
`
`Proprietary
`Regular-Geometry Micro-Cells and Design Tools for Butterfly FPGA
`Proposal Number: D102-0003-0305, Topic Number: SB102-003 (DARPA)
`
`
`
`
`1.2 Problem Addressed: With increasing cost of semiconductor design and manufacturing, enforcing
`regularity at all layers from device technology to hardware architecture is essential for future low-
`power and low-cost digital signal processing hardware. At the architecture level, FPGA-like regularity
`is becoming an attractive solution particularly for low-volume applications, but the adoption of FPGAs
`will be greatly challenged with their excess power, area, and performance due to the massive FPGA
`interconnect. The complexity of the FPGA interconnect is a quadratic function, O(N2), of the number
`of processing elements, N. To mitigate the interconnect challenge, we will make use of hierarchically
`routed and proprietary Konda interconnect architecture which has greatly reduced complexity,
`O(N∙log2N), which results in improved area, power, and performance of FPGA chips. Additionally, we
`must face unique challenges of scaled technology and enforce regularity in the layout cells (micro-
`cells). With the slow development of Extreme Ultra Violet (EUV) lithography, double patterning
`technology (DPT) appears as the most viable lithography solution for 32nm and later technology
`nodes [1]. DPT allows for more compact and better-yielding layout using mask decomposition to
`effectively increase pitch size. To find best DPT decompositions as applicable to FPGA micro-cells
`and building blocks, we propose to investigate micro-cell routing algorithms and characterize the cells
`in energy-area-performance space as compared to their standard-cell based CMOS counterparts.
`
`1.3 Proposed Solution: Our approach will consist of:
`(a) Research the state-of-the-art regular layout geometries and routing algorithms for micro-cells,
`(b) Innovate and provide unique solutions to overcome challenges at the cell layout, circuit, and
`architecture levels,
`(c) Develop modeling and simulation framework that will guide the final selection of regular-geometry
`micro-cells to be used in FPGA macro-blocks such as lookup tables (LUTs), DSP slices, block
`RAM (BRAM) modules, switch matrix (SM) elements that include switch boxes (SBs) and
`configuration memory, and
`(d) Perform energy, area, performance, yield, and variability evaluation of the propose micro-cell
`and macro-block structures for use in hierarchical FPGA interconnect architecture.
`
`
`As a quantitative measure of our Phase I study, we plan to provide an extensive list of circuit metrics
`as listed in Table 1. The metrics include area, energy, performance, variability, and yield estimates for
`standard-cell and proposed regular-geometry cells (both at the micro and macro levels). The outcome
`of Phase I will be to populate Table 1 with quantitative measures of functional-block metrics, and to
`provide associated solutions for layout cells. The layout cells from Phase I will be subsequently used
`in hierarchical FPGA interconnect architecture (Phase II), FPGA chip and hardware mapping tool-flow
`(Phase III) to provide over 10x improvement in power compared to the state-of-the-art FPGAs.
`
`
`Table I: Feasibility study of quantitative figures of merit of layout cells for FPGA application.
`
`Metric /
`Functional Block
`
`Energy (fJ)
`
`
`
`Delay (ps)
`
`Std-
`cell
`
`Regular
`geometry
`
`Std-
`cell
`
`Regular
`geometry
`
`NAND gate
`
`Flip-flop
`
`AOI gate
`Full adder
`
`4-input LUT
`
`DSP slice
`Switch box
`
`Switch matrix
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Variability ()
`Std-
`Regular
`cell
`geometry
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Yield (%)
`
`Std-
`cell
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Regular
`geometry
`
`
`
`
`
`
`
`
`
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`
`
`
`
`2
`
`
`
`
`
`

`

`Case 5:18-cv-07581-LHK Document 31-1 Filed 03/04/19 Page 4 of 13
`
`Proprietary
`Regular-Geometry Micro-Cells and Design Tools for Butterfly FPGA
`Proposal Number: D102-0003-0305, Topic Number: SB102-003 (DARPA)
`
`
`1.4 Proposal Strength: The main strength of the proposed work is the multi-disciplinary approach that
`spans technology, circuits, architectures, and algorithms for exploiting regularity multiple hierarchical
`layers in the design of digital signal processing hardware. The combined effort in the aforementioned
`areas will lead to the development of low-cost FPGA platform based on regular-geometry layout cells,
`hierarchically routed interconnect architecture, and tool-flow for area-efficient hardware mapping of
`digital signal processing algorithms. Our strength in all aspects from layout to algorithms will allow for
`(a) layout cell development, (b) accurate development of device and circuit specifications, (c) allow for
`extensive analysis to predict yield, power consumption, chip area, and performance, (d) provide full
`hardware/software demonstration at the end of the 3-phase program. Furthermore, our team has
`extensive experience in energy-efficient integrated circuits and architectures, CAD algorithms and
`layout cells, as well as network architectures and supporting routing algorithms.
`
`1.5 Market Opportunity: We see a great market potential in broad area of digital signal processing
`hardware where the cost and power consumption are key challenges. Our final goal is to develop a
`simple and low-cost FPGA hardware/software technology based on regular layout cells, regular
`hierarchical interconnect architecture, and tools for block routing and hardware mapping. The
`potential markets include both commercial and defense segments. With greatly reduced power
`consumption and cost, the technology will particularly impact energy-starved applications such as
`embedded electronics and distributed sensors. The technology will also provide a solution to rapid
`prototyping and emulation for a variety of communications and imaging applications. To reduce
`design cost and ensure scalability, our approach will deliver hierarchical methodology from micro-
`cell layout to final chip architecture and supporting tool-flows.
`
`1.6 Company Profile: Konda Technologies, Inc. is a startup company based in San Jose, CA. The
`company was founded in 2007 to develop & commercialize interconnect IP applicable for various
`products including FPGA routing interconnect, System-on-Chip interconnects and warehouse-scale
`datacenter switch networks. Our main customer today is Tier Logic Inc, a 3D-FPGA startup. The
`company has been engaged with vendors such as Xilinx Corporation, Altera Corporation and Cisco
`Systems.
`
`2. Phase I Technical Objectives
`
`2.1 Objective 1: Development of reusable infrastructure of regularity evaluation at cell-level
`We will develop a tool infrastructure to allow for evaluation and exploration of regular layout styles.
`This would include fast estimation-based methods as well as layout generation and simulation based
`methods.
`
`
`2.2 Objective 2: Analysis of regularity tradeoffs at different layers and identification of layout
`styles suitable for the FPGA architecture
`Using the regularity evaluation framework developed above, we will identify the optimal choice of
`regular layout styles on front-end layers (poly, active, M1, M2, contact). This will be applied to varying
`levels of design complexity ranging from standard cells to entire FPGA functional macros.
`
`
`2.3 Objective 3: Develop a comprehensive plan for Phase II
`The outcome of Phase I will be a comprehensive study of micro-cells and macro-blocks that will be
`used in Phase II to implement hierarchical interconnect architecture. The objective is to significantly
`improve energy, area, and performance of the FPGA hardware. The output of Phase I will be guided
`by the metrics outlined in Table 1. Phase I solutions will be developed with tight interaction between
`architecture, circuit, and process parameters to ensure globally optimal solutions. We will propose an
`IP library and associated tools to reduce design cost and facilitate commercial adoption of our
`technology.
`
`
`
`
`
`
`
`3
`
`

`

`Case 5:18-cv-07581-LHK Document 31-1 Filed 03/04/19 Page 5 of 13
`
`Proprietary
`Regular-Geometry Micro-Cells and Design Tools for Butterfly FPGA
`Proposal Number: D102-0003-0305, Topic Number: SB102-003 (DARPA)
`
`
`3. Phase I Work Plan
`
`3.1 Introduction and Prior Art
`Generally, regularity makes patterning easier. Inserting dummy features to ensure uniform density or
`to “isolate” standard cells from surroundings has been commonly followed approach. For more
`regularity, set of layout constraints or restrictive design rules [2], can be enforced to guarantee a
`lithography-friendly regular layout. As an example, a unidirectional fixed-pitch poly layer is enforced in
`Intel’s 45nm process. Because of the success of such gridded design rules in enhancing printability
`and reducing variations [4], such rules might be adopted to pattern other patterning layers such as
`metal and contacts/vias. This principle of restricting the layout is pushed to the extreme in [5] where
`layout is constructed out of pre-characterized regular fabrics (as opposed to design rules). A regular
`layout approach can be excessively conservative especially
`for
`layouts where patterning
`imperfections would otherwise be tolerable [2]. Nevertheless, increasing degree of regularity is
`expected to make patterning even feasible in the near term.
`
`Another important point is that regularity need not imply 1D gratings. The basic “template” for
`regularity could be something else while still ensuring good, low-cost printability (e.g., see [6]). The
`template printability can be optimized, for example, using source-mask optimization (SMO) or using
`character projection in maskless E-beam direct-write. Part of our work will also investigate if regularity
`other than gratings can be useful.
`
`
`3.2 Our Approach
`Our approach within this proposal, and in line with the SBIR call, is to examine routing tools for
`regular-geometry layout cells. The goal in Phase I will be to develop routing tools and layout cells for
`FPGA building blocks. The layout cells will vary in granularity from simple logic gates to complex
`blocks such as look-up tables, logic slices, switch boxes, and memory components. The regular cells
`will be characterized for density (area), yield, energy, and performance and compared to regular
`standard-cell based approach. The regular cells will be used in Phase II for interconnect architecture
`routing. The cells and routing tools will be made available as IP to facilitate rapid commercialization.
`
`
`
`Figure 2: Regularity evaluation framework (left), DRE results on 45nm Nangate open-cell library
`(right).
`
`
`
`Regularity is a continuum of possibilities and it has significant impact on area, delay, power as well as
`expected manufacturing yield. It therefore is very important to co-optimize design rules, regular layout
`styles as well as cell architectures. We have developed a Design Rule Evaluator (DRE) framework
`(see Error! Reference source not found.) which predicts the impact of layout style and design rule
`changes on important circuit metrics for standard cells as well as small custom blocks. DRE can run
`through a 100+ cell 45nm cell library in a few minutes with less than 2% average estimation error (see
`Error! Reference source not found.) making it perfectly suited for design space exploration of layout
`
`4
`
`
`
`
`
`Estimate = actual
`
`0 1 2 3 4 5 6 7 8
`Actual area [mm2]
`
`012345678
`
`Estimated area [mm2]
`
`Netlist
`
`Layout
`style
`
`Set of
`DR
`
`DR to
`evaluate
`Estimates
`of process
`control
`
`Design
`Rule
`Evaluator
`(DRE)
`
`Area
`
`Variability
`
`Manufacturability
`
`

`

`Case 5:18-cv-07581-LHK Document 31-1 Filed 03/04/19 Page 6 of 13
`
`Proprietary
`Regular-Geometry Micro-Cells and Design Tools for Butterfly FPGA
`Proposal Number: D102-0003-0305, Topic Number: SB102-003 (DARPA)
`
`regularity, design rules and design styles. As an example preliminary study using DRE, consider
`increasing regularity on the polysilicon layer (see
`Figure 1). We compare the cases of unrestricted 2D layout to 1D layout with arbitrary pitches and
`restricted 1D fixed pitch (i.e., grating-like) layout styles for a 45nm sequential benchmark design.
`
`
`
`
`Figure 1: Comparing layout restrictions for a benchmark design on polysilicon layer in terms of area,
`catastrophic yield (POS or probability of survival) and current variability (change in W/L).
`
`
`
`
`
`
`
`We will extend DRE to full-chip (FPGA) evaluation including local, intermediate and global metal/via
`layers. This will allow us to arrive at a principled choice of regularity and a layout style to enforce it for
`the FPGA interconnect fabric. The first phase will use DRE coupled with some layout design and
`simulation to identify optimal choice of regularity for basic building blocks of the FPGA.
`
`
`3.3 Task 1: Identification of candidate layout styles for regularity evaluations
`For different candidate patterning technologies at 32nm, 22nm, 16nm nodes, we will identify what
`forms of regularity and on what layers will help the most. This set may be a large one, especially, for
`the 22nm and 16nm nodes where lithographic patterning choices are still unclear (double patterning,
`self-aligned double patterning, e-beam direct write, interference-assisted lithography, etc).
`
`
`3.4 Task 2: DRE-based exploration of regularity tradeoffs in FPGA building blocks
`We will extend DRE framework to allow us to evaluate delay-power-yield-area-variability tradeoffs for
`regularity on polysilicon, contact, M1, M2 layers. The result will be a principled narrowing down of
`layout style choices with clear understanding of the tradeoffs.
`
`
`3.5 Task 3: Generation of layout, simulation, and comparison
`Using the optimized design rules and regular layout stules derived above, we will draw layouts of
`FPGA micro-cells. These will then be analyzed for delay/power/variability/manufacturability using
`explicit lithography simulation using a projected 32nm lithography setup coupled with non-rectangular
`transistor models. This will allow us for a close-to-silicon comparison of different layout styles (e.g.,
`irregular, 2D standard cells vs. regular layouts).
`
`
`
`
`
`
`
`
`
`Figure 4: (left) Area-Energy-Delay space for comparing multiple circuit and micro-architectural
`options. (right) Energy-delay tradeoff in CMOS (solid line) indicating minimum-delay (MDP) and
`minimum-energy (MEP) points. Regular-geometry based designs marked in (X) are expected to
`provide better energy-delay tradeoff than standard-cell based CMOS.
`
`
`5
`
`Area
`[mm2]
`
`8.6k
`8.4k
`8.2k
`8k
`7.8k
`
`0.96
`
`0.955
`
`0.95
`
`POS
`
`2%
`
`1%
`
`0%
`
`D(W/L)
`
`2D-
`poly
`
`1D-
`poly
`
`Fixed
`pitch
`
`2D-
`poly
`
`1D-
`poly
`
`Fixed
`pitch
`
`2D-
`poly
`
`1D-
`poly
`
`Fixed
`pitch
`
`Energy
`
`m-arch
`
`circuits
`
`Area
`
`Delay
`
`

`

`Case 5:18-cv-07581-LHK Document 31-1 Filed 03/04/19 Page 7 of 13
`
`Proprietary
`Regular-Geometry Micro-Cells and Design Tools for Butterfly FPGA
`Proposal Number: D102-0003-0305, Topic Number: SB102-003 (DARPA)
`
`
`
`We will use our methodology for area-energy-delay optimization of CMOS circuits and architectures
`[7, 8]. The methodology is based on pareto curve analysis for various circuit and architecture
`realizations as indicated in Fig. 4(a). Each tradeoff curve is a result of optimization program that
`minimizes energy subject to a delay constraint for circuits. The optimal tradeoff for the circuit-level
`energy and delay is illustrated in solid line in Fig. 4(b) by tuning gate size, supply, and threshold
`voltage. The line is bounded by minimum-delay (MDP) and minimum-energy (MEP) points. All points
`above the line are suboptimal, all points below the line are infeasible.
`
`The goal of regular-geometry explorations is to achieve better energy-delay tradeoff than regular
`standard-cell based CMOS approach as indicated by the (X) markers in Fig. 4(b). Points below MEP
`are the most desirable and it is expected that the micro-cell development will go mainly in this
`direction. Points above MEP but still below E-D plot of CMOS are also very desirable. We will use
`compact circuit models to formulate optimization problems, perform simulations and to populate the
`metrics in Table 1. This includes various FPGA datapath and storage functions.
`
`
`3.6 Task 4: A comprehensive Phase II development plan
`Towards the end of Phase I, as outlined in Table 2, and based on the outcome of Phase I, we will
`create a comprehensive Phase II development plan. We aim to integrate hierarchical interconnect
`architecture in Phase II based on the micro-cells and macro-blocks from Phase I. Details of the
`proprietary hierarchical interconnect architecture will be available in our proposal at the conclusion of
`Phase I.
`
`
`3.7 Timeline
`
`Table II: Phase I project schedule
`
`Month
`Task 1
`Task 2
`Task 3
`Task 4
`
`1
`
`
`
`
`
`2
`
`
`
`
`
`3
`
`
`
`
`
`
`
`4
`
`
`
`
`
`5
`
`
`
`
`
`6
`
`
`
`
`
`
`3.8 Task Work Breakdown
`
`Table III: Estimated task hours for key Personnel
`
`Task/Person
`
`Task 1
`Task 2
`Task 3
`Task 4
`TOTAL
`
`V. Konda
`(PI, Konda Tech)
`100
`80
`60
`40
`280
`
`Scientist
`(Konda Tech)
`140
`100
`60
`40
`340
`
`
`
`D. Markovic
`(UCLA)
`20
`30
`50
`100
`200
`
`P. Gupta
`(UCLA)
`80
`70
`30
`20
`200
`
`
`4. Related Work
`
`We have worked extensively on design-patterning interactions. We have developed methods for
`evaluation of regular layout styles through layout generation and simulation (DAC 2004) as well as
`through estimation and modeling (ICCAD 2009). Prof. Gupta has worked extensively on electrical
`modeling (SPIE’06, SPIE JM3’10, VLSID’10, ASPDAC’08, etc) and mitigation (TCAD’07, SPIE
`JM3’09, etc) of lithographic imperfections. Prof. Markovic has a strong track record in energy-efficient
`ASICs for digital signal processing.
`
`
`
`
`
`6
`
`

`

`Case 5:18-cv-07581-LHK Document 31-1 Filed 03/04/19 Page 8 of 13
`
`Proprietary
`Regular-Geometry Micro-Cells and Design Tools for Butterfly FPGA
`Proposal Number: D102-0003-0305, Topic Number: SB102-003 (DARPA)
`
`Relevant Business Relationships: Since its founding in 2007, the company has attracted strong
`interest from a variety of companies. The company has been engaged with vendors such as Xilinx
`Corporation, Altera Corporation and Cisco Systems. Our main customer today is Tier Logic Inc, a 3D-
`FPGA startup.
`
`Related Work by Others: Regular layouts have been under investigation to various extents in
`academia and industry for past few years. Commercial foundries enforce regularity to varying
`degrees using design rules (e.g., unidirectional, gridded poly is likely to be widely required at 32nm
`node). The origins of the approach lie in early work done by IBM on restricted design rules to be used
`for Alternating PSM patterning. Most cell libraries at 32nm node will use regular layouts, at least for
`the polysilicon layer. More regularity on other layers (contact, M1) has also been investigated in
`somewhat limited fashion by companies (e.g., PDBrix from PDF solutions and AreaTrim by Tela
`Innovations) but extensive tradeoff analyses between extent of regularity, area and yield is still an
`open problem.
`
`
`
`
`
`
`5. Relationship with Future Research or Research and Development
`
`5.1 Phase I Results
`The goal of Phase I is to develop a tool infrastructure to allow for evaluation and exploration of regular
`layout styles. This would include fast estimation-based methods as well as layout generation and
`simulation based methods. Using the regularity evaluation framework developed above, we will
`identify the optimal choice of regular layout styles on front-end layers (poly, active, M1, M2, contact).
`Our approach in Phase I will also focus the demonstration of library IP and the use of software to
`reduce cost and facilitate rapid commercialization. We will also study preliminary routing strategies for
`regular interconnect architecture for Phase II.
`
`
`5.2 Relationship to Phase II and its Objectives
`The regularity layout cells will be extended to FPGA architecture. The FPGA devices have regularly
`placed LUTs (Look-up tables) in a 2D-plane on a silicon die. So far 2D-Mesh networks have been
`used in FPGA devices due to their regular structure, i.e., both interconnect distribution-wise as well as
`the horizontal and vertical routing tracks layout-wise. However the switch complexity of the 2D-Mesh
`based FPGA interconnect is a quadratic function, O(N2), of the number of processing elements, N.
`Even though Benes/Butterfly Fat Tree networks with switch complexity of O(N∙log2N), which results in
`improved area, power, and performance of FPGA chips, they are not implementable due to the lack
`of known regular VLSI layouts, till today. Konda Technologies inventions with regular VLSI layouts for
`Benes/BFT based hierarchical networks are seminal and subsumes all the other known network
`topologies such as Clos networks, hypercube networks, cube-connected cycles and pyramid
`networks, which makes these networks implementable in a FPGA devices with regular structures
`both interconnect distribution-wise and layout-wise which is the key to exploit improved area, power,
`and performance of FPGA devices. The regularity of Konda hierarchical layout is also the key for its
`commercializability in System-on-Chip interconnect devices, FPIC devices as well.
`
`6. Commercialization Strategy
`
`
`We believe that our fundamental intellectual property would help us to commercialize out IP by
`technology and tools licensing. We have already been successful with our current engagement with
`Tier Logic to incorporate our interconnect IP into Teir Logic’s 3D-FPGA devices.
`
`
`6.1 General Commercial and Technology Landscape
`In the regular layout cells space, there have several undertakings in both academia and industry.
`Commercial foundries also enforce regularity to varying degrees using design rules (for example,
`unidirectional, gridded poly is likely to be widely required at 32nm node). The origins of the approach
`lie in early work done by IBM on restricted design rules to be used for Alternating PSM patterning.
`
`
`
`7
`
`

`

`Case 5:18-cv-07581-LHK Document 31-1 Filed 03/04/19 Page 9 of 13
`
`Proprietary
`Regular-Geometry Micro-Cells and Design Tools for Butterfly FPGA
`Proposal Number: D102-0003-0305, Topic Number: SB102-003 (DARPA)
`
`
`
`Most cell libraries at 32nm node will use regular layouts, at least for the polysilicon layer. More
`regularity on other layers (contact, M1) has also been investigated in somewhat limited fashion by
`companies (e.g., PDBrix from PDF solutions and AreaTrim by Tela Innovations) but extensive
`tradeoff analyses between extent of regularity, area and yield is still an open problem. Our advantage
`is system-wide visibility and consideration of regularity that starts from micro-cell level and goes up to
`our proprietary interconnect architecture.
`
`
`6.2 Market Opportunity
`Our initial market focus will be in electronics for portable applications where energy consumption is
`limited and where cost is a key concern such that scalability can be achieved. The approach
`described in this proposal is to create library cells for programmable integrated circuits in advanced
`technology nodes such as 32nm and beyond. We expect this technology to complement existing
`patent portfolio at Konda Technologies, Inc. in the area of network routing algorithms for a variety of
`markets.
`
`Commercialization of the technology is foreseen to be developed with close consultation with large
`semiconductor companies such as Qualcomm, Broadcom, ST Microelectronics, Novelics, Xilinx, and
`Altera where strategic partnerships have already been established. In addition, we expect large
`interest from defense companies such as Boeing and Northrop Grumman. We will certainly take
`inputs from both the civil and DoD companies to best tailor the technology platform to each market
`segment.
`
`We foresee the opportunity to use the technology in application-specific integrated circuit (ASIC)
`markets as well as FPGA market. ASICs used in wireless devices are power-limited yet require large
`amounts of flexibility for multiple operation modes. FPGAs can provide the flexibility, but at a
`prohibitive cost in power and area. Our technology provides solution to both of these problems as we
`offer flexible yet low power FPGA technology. Our micro-cells and routing tools can be used as IP by
`communication and FPGA companies alike. In 2010, FPGA market is expected at $4B, with
`projections of steady growth up to $6B in 2015 [9]. The ASIC market, $18B in 2009, is projected to
`exceed $22B by 2010 [10].
`
`We plan to expand our patent portfolio and issue soft IP (micro-cells and routing algorithms) on a
`non-exclusive license basis to ASIC and FPGA companies such as Qualcomm, Broadcom, Samsung,
`Xilinx, Altera, and Cisco.
`
`
`7. Key Personnel
`
`7.1 Company Background
`Based on a breakthrough and patent-pending layout for Benes/Butterfly Fat Tree network using
`horizontal and vertical tracks and with commercial potential for wide target applications such as
`FPGA devices, FPIC devices, logic emulation systems, Konda Technologies was founded in 2007 to
`commercialize the
`intellectual property into these markets. Our initial focus has been to
`commercialize interconnect IP into FPGA devices.
`
`
`7.2 Dr. Venkat Konda, Principal Investigator & CEO, Konda Technologies, Inc.
`Venkat Konda is an inventor, experienced entrepreneur and the CEO of Konda Technologies which
`he founded in 2007 based on a breakthrough layout using only horizontal and vertical tracks for
`Benes/BFT hierarchical networks, seminal rearrangeably and strictly non-blocking multicast routing
`algorithms with an architecture optimum with switch cost, power and performance. Venkat is currently
`in the process of commercializing the IP in FPGA interconnects, System-on-Chip interconnects and
`warehouse-scale datacenter switches. Prior
`to
`it, Venkat
`invented seminal algorithms
`for
`rearrangeably and strictly non-blocking multicast routing algorithms for Clos Networks and founded a
`startup Teak Networks, to commercialize into packet switch fabrics which are also applicable to
`design cheaper optical cross connects. Venkat received PhD degree in Computer Science & Engg
`
`
`
`8
`
`

`

`Case 5:18-cv-07581-LHK Document 31-1 Filed 03/04/19 Page 10 of 13
`
`Proprietary
`Regular-Geometry Micro-Cells and Design Tools for Butterfly FPGA
`Proposal Number: D102-0003-0305, Topic Number: SB102-003 (DARPA)
`
`
`
`from University of Lousiville, KY in 1992, and M.S in Electrical Engineering from Indian Institute of
`Technology, Kharagpur in 1988. Key patents/applications include:
`
`
`
`[1] Venkat Konda, ”Fully connected generalized multi-stage networks", USPTO App# 12/530,207.
`[2] Venkat Konda, ”Fully connected generalized Butterfly Fat Tree networks", USPTO App# 12/601,273.
`[3] Venkat Konda, ”VLSI Layouts of Fully connected generalized networks", USPTO App# 12/601,275.
`[4] Venkat Konda, ”Rearrangeably nonblocking multicast multi-stage networks ", US Patent # 6,885,669.
`[5] Venkat Konda, ”Strictly nonblocking multicast multi-stage networks ", US Patent # 6,868,084.
`
`
`7.2 Prof. Dejan Markovic, UCLA, Electrical Engineering (Sub-contractor)
`Dejan Markovic is an Assistant Professor of Electrical Engineering at UCLA. He completed the Ph.D.
`degree in 2006 at the University of California, Berkeley. In recognition of the impact of his Ph.D. work,
`he was awarded 2007 David J. Sakrison Memorial Prize at UC Berkeley. His current research is
`focused on integrated circuits for emerging radio and healthcare systems, design with post-CMOS
`devices, optimization methods and CAD flows. He will be contributing to the design and circuit
`demonstration tasks in this project. His responsibilities will include layout cell characterization, design
`and optimization of FPGA building blocks. Some relevant publications include:
`
`
`
`[1] D. Marković, C. C. Wang, L. Alarcon, T.-T. Liu, and J. M. Rabaey, "Ultralow-Power Design in Near-
`Threshold Region," Proceedings of the IEEE, vol. 98, no. 2, pp. 237-252, Feb. 2010.
`[2] R. Nanda, C.-H. Yang, and D. Marković, "DSP Architecture Optimization in Matlab/Simulink
`Environment," in Proc. Int. Symp. on VLSI Circuits (VLSI'08), June 2008, pp. 192-193.
`[3] D. Marković, B. Nikolić, and R.W. Brodersen, "Power and Area Minimization for Multidimensional Signal
`Processing," IEEE J. Solid-State Circuits, vol. 42, no. 4, pp. 922-934, April 2007.
`[4] D. Marković, R.W. Brodersen, and B. Nikolić, "A 70GOPS 34mW Multi-Carrier MIMO Chip in
`3.5mm2," in Proc. Int. Symp. on VLSI Circuits (VLSI'06), June 2006, pp. 196-197.
`[5] D. Marković, V. Stojanović, B. Nikolić, M.A. Horowitz, and R.W. Brodersen, "Methods for True Energy-
`Performance Optimization," IEEE J. Solid-State Circuits, vol. 39, no. 8, pp. 1282-1293, Aug. 2004.
`
`
`7.3 Prof. Puneet Gupta, UCLA, Electrical Engineering (Sub-contractor)
`Puneet Gupta (http://nanocad.ee.ucla.edu)
`is currently an Assistant Professor of Electrical
`Engineering at UCLA. He received the B.Tech degree in Electrical Engineering from Indian Institute of
`Technology, Delhi in 2000 and Ph.D. in 2007 from University of California, San Diego. He co-founded
`Blaze DFM Inc. (acquired by Tela Inc.) in 2004 and served as its product architect till 2007. He is a
`recipient of NSF CAREER award, ACM/SIGDA Outstanding New Faculty Award, IBM Ph.D.
`fellowship and European Design Automation Association Outstanding Dissertation Award. Dr. Gupta's
`research has focused on building high-value bridges between physical design and semiconductor
`manufacturing for lowered cost, increased yield and improved predictability of integrated circuits. He
`will