Case 2:17-cv-04263-JVS-JCG Document 1-3 Filed 06/08/17 Page 1 of 16 Page ID #:55
`
`
`
`Exhibit C
`
`
`
`
`

`

`Case 2:17-cv-04263-JVS-JCG Document 1-3 Filed 06/08/17 Page 2 of 16 Page ID #:56
`I IIIII IIIIIIII Ill lllll lllll lllll lllll lllll lllll lllll lllll 111111111111111111
`US007279355B2
`
`c12) United States Patent
`Lee et al.
`
`(IO) Patent No.:
`(45) Date of Patent:
`
`US 7,279,355 B2
`Oct. 9, 2007
`
`(54) METHOD FOR FABRICATING A
`PACKAGING DEVICE FOR
`SEMICONDUCTOR DIE AND
`SEMICONDUCTOR DEVICE
`INCORPORATING SAME
`
`(75)
`
`Inventors: Kong Weng Lee, Penang (MY); Kee
`Yean Ng, Penang (MY); Yew Cheong
`Kuan, Penang (MY); Gin Ghee Tan,
`Penang (MY); Cheng Why Tan,
`Penang (MY)
`
`(73) Assignee: Avago Technologies ECBUIP
`(Singapore) Pte Ltd, Singapore (SG)
`
`( *) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by O days.
`
`(21) Appl. No.: 10/608,606
`
`(22) Filed:
`
`Jun. 27, 2003
`
`(65)
`
`Prior Publication Data
`US 2004/0266058 Al
`
`Dec. 30, 2004
`
`(51)
`
`Int. Cl.
`HOl/ 21/00
`(2006.01)
`(52) U.S. Cl. ....................................... 438/106; 438/125
`(58) Field of Classification Search ........ 438/106-107,
`438/111-113, 116, 118-119, 121-127, 26;
`361/719, 720, 767; 257/E21.067, 21.577,
`257/21.585, 21.588; 174/265
`See application file for complete search history.
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`2,907,925 A *
`5,006,673 A *
`5,177,593 A
`5,298,687 A *
`5,440,075 A *
`5,640,048 A
`5,670,797 A *
`
`10/1959
`4/1991
`1/1993
`3/1994
`8/1995
`6/1997
`9/1997
`
`174/265
`......................
`Parsons
`Freyman et al. ............ 174/255
`Abe
`Rapoport et al.
`Kawakita et al.
`Selna
`Okazaki
`
`......................
`
`257/91
`
`174/261
`174/265
`
`5,986,885 A
`6,084,295 A
`6,191,477 Bl
`6,268,654 Bl
`6,362,525 Bl *
`6,383,835 Bl *
`6,620,720 Bl
`6,707,247 B2 *
`6,828,510 Bl *
`7,098,593 B2
`2002/0139990 Al
`2002/0179335 Al *
`2003/0017645 Al*
`2003/0020126 Al*
`2003/0040138 Al *
`2003/0168256 Al *
`
`11/1999 Wyland
`7 /2000 Horiuchi et al.
`2/2001 Hashemi
`7/2001 Glenn et al.
`3/2002 Rahim ........................
`5/2002 Hata et al. ....................
`9/2003 Moyer et al.
`3/2004 Murano
`......................
`12/2004 Asai et al. ..................
`8/2006 Teng
`10/2002 Suehiro et al.
`174/265
`12/2002 Curcio et al ................
`1/2003 Kabayashi et al.
`......... 438/106
`1/2003 Sakamoto et al.
`.......... 257/414
`2/2003 Kobayashi et al.
`......... 438/112
`9/2003 Chien .........................
`174/264
`OTHER PUBLICATIONS
`
`257/738
`438/65
`
`313/501
`174/255
`
`Syd R. Wilson, Clarence J. Tracy, and John L. Freeman, Jr.,
`"Handbook of Multilevel Metallization
`for Integrated Circuits",
`Noyes Pub!., Westwood, New Jersey (1993), pp. 868-872.
`Electronic Packaging and Production, "Innovative PCB Reinforce(cid:173)
`ment", (Feb., 1997), p. 1.
`Johannes Adam, "New Correlations Between Electrical Current and
`Temperature Rise in PCB Traces", Proc. 20th IEEE Semi-Therm
`Symp., (Mar. 2004), pp. 1-8.
`* cited by examiner
`Primary Examiner-Sara Crane
`
`(57)
`
`ABSTRACT
`
`A substantially planar substrate having opposed major sur(cid:173)
`faces is provided. The substrate includes a through hole that
`extends between the major surfaces. The through hole is
`filled with a conductive interconnecting element. A conduc(cid:173)
`tive mounting pad and a conductive connecting pad are
`formed on different ones of the major surfaces in electrical
`contact with the conductive interconnecting element. The
`packaging device formed by the method has a volume that
`is only a few times that of the semiconductor die and can be
`fabricated from materials that can withstand high-tempera(cid:173)
`ture die attach processes. The packaging device can be
`configured as the only packaging device used in the semi(cid:173)
`conductor device or as a submount for a semiconductor die
`that requires a high-temperature die attach process.
`
`12 Claims, 8 Drawing Sheets
`
`252
`
`250
`
`254
`
`200
`
`132
`
`110
`
`114
`
`100
`
`140
`
`120
`
`142
`
`122
`
`

`

`Case 2:17-cv-04263-JVS-JCG Document 1-3 Filed 06/08/17 Page 3 of 16 Page ID #:57
`
`U.S. Patent
`
`Oct. 9, 2007
`
`Sheet 1 of 8
`
`US 7,279,355 B2
`
`120~
`
`116
`
`~-{
`, __
`
`FIG.1 A
`
`FIG.2A
`
`

`

`Case 2:17-cv-04263-JVS-JCG Document 1-3 Filed 06/08/17 Page 4 of 16 Page ID #:58
`
`U.S. Patent
`
`Oct. 9, 2007
`
`Sheet 2 of 8
`
`US 7,279,355 B2
`
`11~~~0~
`
`114
`
`140
`
`114
`
`100
`112
`
`130
`
`110
`
`112
`
`FIG.1 B
`1F
`
`130
`
`100
`
`/120
`, t,
`
`\ ~
`
`FIG.1 C
`
`1F
`FIG.1 D
`
`110
`
`114
`
`100
`
`1 140
`
`_ /'120
`, t,
`'~~
`
`FIG.1 F
`
`FIG.1 E
`
`

`

`Case 2:17-cv-04263-JVS-JCG Document 1-3 Filed 06/08/17 Page 5 of 16 Page ID #:59
`
`U.S. Patent
`
`Oct. 9, 2007
`
`Sheet 3 of 8
`
`US 7,279,355 B2
`
`254
`
`200
`
`132
`
`100
`
`140
`
`120
`
`142
`
`122
`
`110
`'")
`
`112
`'\
`
`I
`
`FIG.28
`252'\
`~2F
`
`I
`
`L----130
`
`/ 100 /200
`
`12t
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`(132
`
`I \,
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`(120
`( }
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`2LI
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`2F
`FIG.20
`
`110
`
`114
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`100
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`r140
`
`,_,
`
`110
`
`114
`
`130
`
`250
`
`254
`
`254
`
`114
`
`140
`
`120
`
`11
`
`FIG.2C
`
`200/
`252
`FIG.2F
`
`FIG.2E
`
`

`

`Case 2:17-cv-04263-JVS-JCG Document 1-3 Filed 06/08/17 Page 6 of 16 Page ID #:60
`
`U.S. Patent
`
`Oct. 9, 2007
`
`Sheet 4 of 8
`
`US 7,279,355 B2
`
`320--....,_
`
`316
`
`>r.-r
`
`"-~
`
`FIG.3A
`
`FIG.4A
`
`

`

`Case 2:17-cv-04263-JVS-JCG Document 1-3 Filed 06/08/17 Page 7 of 16 Page ID #:61
`
`U.S. Patent
`
`Oct. 9, 2007
`
`Sheet 5 of 8
`
`US 7,279,355 B2
`
`31~1~0~
`'i300
`
`3;16
`
`!{ r
`
`300
`312
`330
`
`314
`
`340
`
`FIG.3C
`
`314
`
`340
`
`320
`FIG.38
`
`310 312
`
`300
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`I
`\
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`')
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`3F
`FIG.30
`
`310 314
`
`300
`
`,340
`
`FIG.3F
`
`FIG.3E
`
`

`

`Case 2:17-cv-04263-JVS-JCG Document 1-3 Filed 06/08/17 Page 8 of 16 Page ID #:62
`
`U.S. Patent
`
`Oct. 9, 2007
`
`Sheet 6 of 8
`
`US 7,279,355 B2
`
`250
`
`/400
`
`320
`340
`FIG.48
`
`',
`
`314
`
`330
`
`250
`
`310
`
`312
`\-~
`
`I
`
`(320
`( .}
`
`4F 300 /400
`
`---·
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`330
`
`250
`
`400
`FIG.4C
`
`-4F
`FIG.40
`
`300
`
`,....,-..-.....,.,....-312
`
`314
`310
`~~+---l.--~__..£'-----""i
`
`300/400
`
`31
`
`340
`
`330
`
`250
`
`r340
`
`~ /320
`~--~)
`
`400/
`FIG.4F
`
`FIG.4E
`
`

`

`Case 2:17-cv-04263-JVS-JCG Document 1-3 Filed 06/08/17 Page 9 of 16 Page ID #:63
`
`U.S. Patent
`
`Oct. 9, 2007
`
`Sheet 7 of 8
`
`US 7,279,355 B2
`
`5;19
`it
`I
`
`FIG.5A
`
`I
`
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`r-
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`FIG.58
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`
`542
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`522
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`5145417
`FIG.50
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`521
`
`543
`
`523
`
`

`

`Case 2:17-cv-04263-JVS-JCG Document 1-3 Filed 06/08/17 Page 10 of 16 Page ID #:64
`
`U.S. Patent
`
`Oct. 9, 2007
`
`Sheet 8 of 8
`
`US 7,279,355 B2
`
`512
`
`250
`
`/600
`
`251
`
`532
`
`531
`
`533
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`542
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`522
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`541
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`FIG.GA
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`FIG.68
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`I
`I
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`I
`I
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`521
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`543
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`523
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`254 532
`
`522
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`521
`FIG.SC
`
`523
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`512 530
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`540
`514
`
`520
`
`522
`
`523
`
`FIG.60
`
`

`

`Case 2:17-cv-04263-JVS-JCG Document 1-3 Filed 06/08/17 Page 11 of 16 Page ID #:65
`
`US 7,279,355 B2
`
`1
`METHOD FOR FABRICATING A
`PACKAGING DEVICE FOR
`SEMICONDUCTOR DIE AND
`SEMICONDUCTOR DEVICE
`INCORPORATING SAME
`
`2
`packages. Modifying such processes to use a new semicon(cid:173)
`ductor device package can be expensive and can interrupt
`production. Therefore, what is additionally needed is a way
`to mount a semiconductor die that requires a high-tempera(cid:173)
`ture die attach process in a conventional packaging device.
`
`RELATED APPLICATION
`
`SUMMARY OF THE INVENTION
`
`This application is related to a simultaneously-filed U.S.
`patent application Ser. No. 10/608,605 entitled Packaging
`Device for Semiconductor Die and Semiconductor Device
`Incorporating Same of inventors Kong Weng Lee, Kee Yean
`Ng, Yew Cheong Kuan, Cheng Why Tan and Gin Ghee Tan.
`
`BACKGROUND OF THE INVENTION
`
`Many types of conventional semiconductor device are
`composed of a semiconductor die mounted in a packaging
`device. One type of packaging device widely used in the
`industry includes a metal lead frame. A metallization layer
`of aluminum located on the bottom surface of the semicon(cid:173)
`ductor die is bonded to a conductive surface that forms part
`of the lead frame to attach and electrically connect the die to
`the lead frame. Additionally, electrical connections are made
`between bonding pads on the top surface of the die and other
`leads of the lead frame to provide additional electrical
`connections to the die. The lead frame and semiconductor
`die are then encapsulated to complete the semiconductor
`device. The packaging device protects the semiconductor
`die and provides electrical and mechanical connections to 30
`the die that are compatible with conventional printed circuit
`board assembly processes.
`In such conventional semiconductor devices, the bottom
`surface of the die is typically bonded to the conductive
`surface of the lead frame using a silver epoxy adhesive that 35
`cures at a relatively low temperature, typically about 120° C.
`The curing temperature of the silver epoxy adhesive is
`compatible with the other materials of the packaging device.
`The volume of the packaging device used in such con(cid:173)
`ventional semiconductor devices, i.e., the lead frame and the 40
`encapsulant, is typically many times that the semiconductor
`die. This makes such conventional semiconductor devices
`unsuitable for use in applications in which a high packing
`density is required. A high packing density allows minia(cid:173)
`turization and other benefits. Therefore, what is needed is a 45
`semiconductor packaging device that is comparable in vol(cid:173)
`ume with the semiconductor die and that is compatible with
`conventional printed circuit board assembly processes.
`Recently, semiconductor die having a substrate surface
`metallization
`layer of a gold-tin alloy (80% Au:20% Sn 50
`approximately) have been
`introduced
`in light-emitting
`devices. Such semiconductor die typically have a substrate
`of sapphire, silicon carbide or a Group III-V semiconductor
`material, such as gallium arsenide. Semiconductor devices
`having substrates of the first two substrate materials have 55
`layers of Group III-V semiconductor materials, such as
`gallium nitride, deposited on their substrates. The die attach
`process for such semiconductor die uses a gold-tin eutectic,
`which has a melting point of about 280° C. Temperatures as
`high as about 350° C. can be encountered in the die attach 60
`process for such die. Such high temperatures are incompat(cid:173)
`ible with the materials of many conventional packaging
`devices. Thus, what is also needed is a packaging device for
`semiconductor die that use a high-temperature die attach
`process.
`Many printed circuit assembly processes and assembly
`equipment require the use of standard semiconductor device
`
`The invention provides a method for fabricating a pack-
`10 aging device for semiconductor die. In the method, a sub(cid:173)
`stantially planar substrate having opposed major surfaces is
`provided. The substrate includes a through hole that extends
`between the major surfaces. The through hole is filled with
`a conductive interconnecting element. A conductive mount-
`15 ing pad and a conductive connecting pad are formed on
`different ones of the major surfaces in electrical contact with
`the conductive interconnecting element.
`The method just described fabricates a packaging device
`usable as a submount for a semiconductor die. An extension
`20 of the method can be used to fabricate a packaging device
`usable as part of a semiconductor device. The extension
`additionally includes providing the substrate including an
`additional through hole and filling the additional through
`hole with an additional conductive interconnecting element.
`25 The process of forming the conductive pad and the conduc(cid:173)
`tive connecting pad additionally includes forming a conduc(cid:173)
`tive bonding pad and an additional conductive connecting
`pad on the different ones of the opposed surfaces of the
`substrate in electrical contact with the additional conductive
`interconnecting element.
`In fabricating both the semiconductor device and the
`submount, a semiconductor die is attached to the mounting
`pad. Additionally, in making the semiconductor device, a
`bonding wire is connected between the semiconductor die
`and the conductive bonding pad. Fabrication of the semi(cid:173)
`conductor device may be completed by encapsulating the
`semiconductor die and at least a portion of the major surface
`of the substrate on which the mounting pad is located.
`The methods described above are typically performed on
`the wafer scale in which the substrate constitutes part of a
`wafer. Performing the methods on the wafer scale signifi(cid:173)
`cantly reduces the cost of manufacturing
`the packaging
`devices and semiconductor devices. Wafer scale fabrication
`additionally includes singulating the wafer into individual
`devices. The devices may be electrically tested prior to
`singulation. In the case of optoelectronic devices, electro-
`optical testing may additionally be performed.
`The packaging device fabricated in accordance with the
`method has a volume that is only a few times that of the
`semiconductor die and can be fabricated from materials that
`can withstand a high-temperature die attach process. The
`packaging device can be configured as the only packaging
`device of the semiconductor device. The packaging device
`can alternatively be configured as a submount for a semi(cid:173)
`conductor die that requires a high-temperature die attach
`process. The submount with attached semiconductor die can
`be handled as a conventional, albeit slightly larger, semi(cid:173)
`conductor die that is then mounted in a conventional pack(cid:173)
`aging device, such as a lead frame based packaging device,
`using a conventional semiconductor device assembly pro(cid:173)
`cess, including conventional temperatures.
`A semiconductor device fabricated in accordance with the
`method can be mounted in a conventional packaging device
`as described above. Alternatively, the semiconductor device
`65 may be a stand-alone semiconductor device that has a low
`profile and that can be used in high packing density appli(cid:173)
`cations. Such semiconductor device typically additionally
`
`

`

`Case 2:17-cv-04263-JVS-JCG Document 1-3 Filed 06/08/17 Page 12 of 16 Page ID #:66
`
`US 7,279,355 B2
`
`3
`includes an encapsulant that encapsulates the semiconductor
`die and at least a portion of the major surface of the substrate
`on which the mounting pad is located.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`10
`
`FIGS. lA, 18, lC, lD, 1E and lF are respectively an
`isometric view, a side view, a front view, a top view, a
`bottom view and a cross-sectional view of a first embodi(cid:173)
`ment of a packaging device in accordance with the inven-
`tion. The cross-sectional view of FIG. lF is along the section
`line lF-lF
`in FIG. lD.
`FIGS. 2A, 28, 2C, 2D, 2E and 2F are respectively an
`isometric view, a side view, a front view, a top view, a
`bottom view and a cross-sectional view of a first embodi-
`ment of a semiconductor device in accordance with the
`invention. The cross-sectional view of FIG. 2F is along the
`section line 2F-2F
`in FIG. 2D.
`FIGS. 3A, 38, 3C, 3D, 3E and 3F are respectively an
`isometric view, a side view, a front view, a top view, a
`bottom view and a cross-sectional view of a second embodi(cid:173)
`ment of a packaging device in accordance with the inven(cid:173)
`tion. The cross-sectional view of FIG. 3F is along the section
`line 3F-3F
`in FIG. 3D.
`FIGS. 4A, 48, 4C, 4D, 4E and 4F are respectively an 25
`isometric view, a side view, a front view, a top view, a
`bottom view and a cross-sectional view of a second embodi(cid:173)
`ment of a semiconductor device in accordance with the
`invention. The cross-sectional view of FIG. 4F is along the
`section line 4F---4F in FIG. 4D.
`FIGS. SA-SC are side views illustrating a method in
`accordance with the invention for fabricating a packaging
`device for a semiconductor die.
`FIG. SD is a side view illustrating an optional additional
`process that may be included in the method illustrated in
`FIGS. SA-SC.
`FIGS. 6A-6D are side views illustrating a method in
`accordance with the invention for fabricating a semiconduc(cid:173)
`tor device.
`
`4
`Thus, interconnecting element 120 extending through sub(cid:173)
`strate 110 in through hole 116 electrically connects mount(cid:173)
`ing pad 130 to connecting pad 140. Bonding pad 132 and
`connecting pad 142 are electrically connected to opposite
`ends of interconnecting element 122. Thus, interconnecting
`element 122 extending through substrate 110 in through hole
`118 electrically connects bonding pad 132 to connecting pad
`142.
`The material of substrate 110 is a thermally-conductive
`ceramic such as alumina or beryllia. In an embodiment, the
`material of the substrate was Kyocera® Type A440 ceramic
`sold by Kyocera Corp., of Kyoto, Japan. Typical dimensions
`of the substrate are in the range from about 0.5 mm square
`to about 2 mm square. Rectangular configurations are also
`possible. Alternative substrate materials include semicon-
`ductors, such as silicon, and epoxy laminates, such as those
`used in printed-circuit boards. Other materials that have a
`high thermal conductivity and a low electrical conductivity
`20 can be used instead of those exemplified above. The coef(cid:173)
`ficient of thermal expansion of the substrate material relative
`to that of the semiconductor die to be mounted on packaging
`device 100 should also be considered
`in choosing the
`substrate material.
`As will be described in more detail below, substrate 110
`is part of a wafer (not shown) from which typically several
`hundred packaging devices 100 are fabricated by batch
`processing. After fabrication of the packaging devices, the
`30 wafer is singulated into individual packaging devices. Alter(cid:173)
`natively, the packaging devices may be left in wafer form
`after fabrication. In this case, singulation is not performed
`until after at least a die attach process has been performed to
`attach a semiconductor die to each mounting pad 130 on the
`35 wafer. In some embodiments, wafer-scale wire bonding,
`encapsulation and testing are also performed prior to singu(cid:173)
`lation. Full electrical testing, including light output testing,
`may be performed on the wafer.
`The material of interconnecting elements 120, 122 is
`40 metal or another electrically-conductive material. In an
`embodiment, the material of the interconnecting elements is
`tungsten, but any electrically-conductive material capable of
`forming a low-resistance electrical connection with the pads,
`i.e., mounting pad 130, bonding pad 132 and connecting
`45 pads 140, 142, and capable of withstanding the temperature
`of the die-attach process may be used. As noted above,
`packaging device 100 may be subject to a temperature as
`high as about 350° C. when a gold-tin eutectic is used to
`attach a semiconductor die to the mounting pad 130 of the
`50 packaging device. Interconnecting elements 120, 122 may
`be located relative to mounting pad 130 and bonding pad
`132, respectively, elsewhere than the centers shown. More(cid:173)
`over, more than one interconnecting element may be located
`within either or both of the mounting pad and the bonding
`55 pad.
`The material of pads 130, 132, 140, 142 is metal or
`another electrically-conductive material. Important consid(cid:173)
`erations in selecting the material of the pads are adhesion to
`substrate 110, an ability to form a durable, low-resistance
`electrical connection with interconnecting elements 120 and
`122 and an ability to withstand the temperature of the die
`attach process. In an embodiment, the structure of the pads
`is a seed layer of tungsten covered with layer of nickel about
`1.2 µm to about 8.9 µm thick that is in tum covered with a
`65 layer of gold about 0.75 µm thick. Other metals, alloys,
`conductive materials and multi-layer structures of such
`materials can be used.
`
`15
`
`DETAILED DESCRIPTION OF THE
`INVENTION
`
`FIGS. lA-lF are schematic diagrams illustrating a first
`exemplary embodiment 100 of a packaging device for a
`semiconductor die in accordance with the invention. Pack(cid:173)
`aging device 100 is composed of a substrate 110, intercon(cid:173)
`necting elements 120 and 122, a mounting pad 130, a
`bonding pad 132 and connecting pads 140 and 142 (FIG.
`lE).
`Substrate 110 is substantially planar, has opposed major
`surfaces 112 and 114 and defines through holes 116 and 118
`that extend through the substrate between major surfaces
`112 and 114. Interconnecting element 120 is electrically
`conductive and is located in through hole 116. Interconnect(cid:173)
`ing element 122 is electrically conductive and is located in
`through hole 118. Mounting pad 130 and bonding pad 132
`are electrically conductive, are separate from one another
`and are located on the portions of the major surface 112 of
`substrate 110 in which through holes 116 and 118 are 60
`respectively
`located. Connecting pads 140 and 142 are
`electrically conductive, are separate from one another and
`are located on the portions of the major surface 114 of
`substrate 110 in which through holes 116 and 118 are
`respectively located.
`Mounting pad 130 and connecting pad 140 are electrically
`connected to opposite ends of interconnecting element 120.
`
`

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`6
`ductor die 250 and bonding pad 132. Using low-loop wire
`bonding minimizes the maximum height of the bonding wire
`above substrate 110, and, therefore, reduces the overall
`height of semiconductor device 200. Other processes for
`providing an electrical connection between a bonding pad on
`a semiconductor die and a bonding pad on a packaging
`device are known in the art and may be used instead,
`especially in applications in which device height is a less
`important consideration.
`The material of encapsulant 252 is clear epoxy. Alterna(cid:173)
`tive encapsulant materials include silicone. Embodiments of
`semiconductor device 200 that neither emit nor detect light
`can use an opaque encapsulant.
`In the example of semiconductor device 200 described
`above, semiconductor die 250 is embodied as a light(cid:173)
`emitting diode. Semiconductor die 250 may alternatively
`embody another type of diode without modification
`to
`packaging device 100. Versions of packaging device 100
`may be used to package semiconductor die other than those
`that embody such electrical components as diodes that have
`only two electrodes. Versions of packaging device 100 may
`be used to package semiconductor die that embody such
`electronic circuit elements as transistors and integrated
`circuits that have more than two electrodes. Such versions of
`packaging device 100 have a number of bonding pads,
`interconnecting elements and connecting pads correspond(cid:173)
`ing to the number of bonding pads located on the top major
`surface of the semiconductor die. For example, a version of
`30 packaging device 100 for packaging a semiconductor die
`that embodies a transistor having collector, base and emitter
`electrodes, and in which the substrate metallization provides
`the collector electrode, has two bonding pads, two intercon(cid:173)
`necting elements and two connecting pads. Wire bonds
`35 connect the emitter bonding pad on the semiconductor die to
`one of the bonding pads on the packaging device and the
`base bonding pad on the semiconductor die to the other of
`the bonding pads on the packaging device.
`The connecting pads, e.g., connecting pads 140 and 142,
`of embodiments of packaging device 100 having multiple
`connecting pads may be arranged to conform with an
`industry standard pad layout to facilitate printed circuit
`layout. In such embodiments, the interconnecting elements
`may be offset from the centers of the respective mounting
`pads, bonding pads and connecting pads to allow the con(cid:173)
`necting pad layout to conform with such a standard pad
`layout. In some embodiments, one or more of the mounting
`pad, bonding pads and connecting pads may have a shape
`that differs from the regular shapes illustrated. Some irregu(cid:173)
`lar shapes include two main regions electrically connected
`by a narrow track. For example, an irregularly-shaped
`bonding pad includes a region to which the bonding wire is
`attached, a region connected to the interconnecting element
`and a narrow track interconnecting the two regions.
`Some versions of packaging device may accommodate
`two or more semiconductor die. In such versions, mounting
`pad 130 is sized large enough to accommodate the two or
`more semiconductor die. Additionally, such versions include
`sufficient bonding pads, interconnecting elements and con(cid:173)
`necting pads to make the required number of electrical
`connections
`to the semiconductor die. Alternatively, the
`packaging device may include two or more mounting pads.
`The mounting pads may be electrically connected to one
`another and thence to a common interconnecting element
`65 and connecting pad. Alternatively, each mounting pad may
`be electrically connected to a corresponding connecting pad
`by a respective interconnecting element.
`
`20
`
`25
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`5
`Packaging device 100 is used to package a semiconductor
`die. A semiconductor device in which a semiconductor die
`is packaged using packaging device 100 described above
`will be described next.
`illustrating an
`FIGS. 2A-2F are schematic diagrams
`exemplary embodiment 200 of a semiconductor device in
`accordance with the invention. Semiconductor device 200
`incorporates packaging device 100 in accordance with the
`invention. Elements of semiconductor device 200 that cor(cid:173)
`respond to elements of packaging device 100 described 10
`above with reference to FIGS. lA-lF are indicated using the
`same reference numerals and will not be described again in
`detail.
`Semiconductor device 200 is composed of packaging
`device 100 described above with reference to FIGS. lA-lF,
`a semiconductor die 250, encapsulant 252 and a bonding
`wire 254. In the example shown, semiconductor die 250
`embodies a light-emitting diode and has anode and cathode
`electrodes (not shown) covering at least parts of its opposed
`major surfaces. Semiconductor die 250 is mounted on pack(cid:173)
`aging device 100 with the metallization on its bottom major
`surface attached to mounting pad 130. Encapsulant 252
`covers the semiconductor die and the part of the major
`surface 112 of substrate 100 where mounting pad 130 and
`bonding pad 132 are located. Bonding wire 254 extends
`between a bonding pad located on the top major surface of
`semiconductor die 250 and bonding pad 132.
`The bonding pad on the top major surface of semicon(cid:173)
`ductor die 250 is typically part of or connected to the anode
`electrode of the light-emitting diode. The metallization on
`the bottom major surface of semiconductor die 250 typically
`constitutes the cathode electrode of the light-emitting diode.
`Thus, the anode electrode of semiconductor die 250 is
`electrically connected to connecting pad 142 by bonding
`wire 254, bonding pad 132 and interconnecting element 122,
`and the cathode electrode of semiconductor die 250 is
`electrically connected to connecting pad 140 by mounting
`pad 130 and interconnecting element 120.
`Encapsulant 252 has a thickness greater than the maxi(cid:173)
`mum height of bonding wire 254 above major surface 112. 40
`In the example shown, the encapsulant is transparent to
`enable semiconductor device 200 to emit the light generated
`by semiconductor die 250.
`Semiconductor die 250 is composed of one or more layers
`(not shown) of any semiconductor material composed of 45
`elements from Groups II, III, IV, V and VI of the periodic
`table in binary, ternary, quaternary or other form. Semicon(cid:173)
`ductor die 250 may additionally include a non-semiconduc-
`tor substrate material, such as sapphire, metal electrode
`materials and dielectric insulating materials, as is known in 50
`the art.
`In an embodiment of the above-described example in
`which semiconductor die 250 embodies a light-emitting
`diode, semiconductor die 250 is composed of a substrate of
`silicon carbide that supports one or more layers of (indium) 55
`gallium nitride. Such a light-emitting diode generates light
`in a wavelength range extending from ultra-violet to green.
`The bottom major surface (not shown) of the substrate
`remote from the layers of (indium) gallium nitride is coated
`with a metallization layer of a gold-tin alloy. A gold-tin 60
`eutectic attaches the semiconductor die to mounting pad
`130, as described above, to provide a mechanical and
`electrical connection between the semiconductor die and the
`mounting pad.
`The material of bonding wire 254 is gold. A process
`known in the art as low-loop wire bonding is used to connect
`the bonding wire between the anode electrode of semicon-
`
`

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`Case 2:17-cv-04263-JVS-JCG Document 1-3 Filed 06/08/17 Page 14 of 16 Page ID #:68
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`7
`Semiconductor device 200 is used by mounting it on a
`printed circuit board or other substrate using conventional
`surface-mount techniques or other techniques known in the
`art. Semiconductor device 200 is placed on a surface of the
`printed circuit board with connecting pads 140 and 142
`aligned with respective pads on the printed circuit board.
`The printed circuit board is then passed across a solder wave
`to form a solder joint between connecting pads 140 and 142
`and the respective pads on the printed circuit board. Alter(cid:173)
`natively, semiconductor device 200 may be affixed to a 10
`printed circuit board by a process known as infra-red reflow
`soldering in which a pattern of solder is applied to the
`printed circuit board using a stencil, semiconductor device
`200 and, optionally, other components are loaded onto the
`printed circuit board and the printed circuit board assembly 15
`is irradiated with infra-red light to heat and reflow the solder.
`Other processes for attaching electronic components
`to
`printed circuit boards are known in the art and may alter(cid:173)
`natively be used. Packaging device 100 and semiconductor
`device 200 may additionally include adhesive regions on the 20
`major surface 114 of substrate 110 external to connecting
`pads 140 and 142 to hold the semiconductor device in place
`on the printed circuit board during soldering.
`In semiconductor device 200, packaging device 100 and
`encapsulant 252 collectively have a volume that is only
`about 15 times the volume of semiconductor die 250. Thus,
`packaging device 100 is well suited for use in high packing
`density applications. Moreover, packaging device 100 is
`fabricated from materials capable of withstanding the high
`temperatures involved in a die attach process that uses a
`gold-tin eutectic. Accordingly, packaging device 100 is well
`suited for packaging semiconductor die, such as the die of
`certain light-emitting devices, that require a die attach
`process that uses a gold-tin eutectic.
`As noted above, many printed circuit board assembly 35
`processes are designed to use standard device packages, but
`many standard device packages are incapable of withstand(cid:173)
`ing the high temperatures involved in a die attach process
`that uses a gold-tin eutectic. FIGS. 3A-3F are schematic
`drawings showing a second embodiment 300 of a packaging 40
`device in accordance with the invention. Packaging device
`300 takes the form of a submount that enables semiconduc-
`tor die that are mounted using a gold-tin eutectic or other
`high-temperature die attach process to be mounted in con(cid:173)
`ventional semiconductor device packages that are incapable
`of withstanding such high temperatures. Moreover, packag(cid:173)
`ing device 300 with a semiconductor die mounted thereon
`can be mounted in a conventional semiconductor device
`package as if it were a conventional semiconductor die. This
`allows conventional die attach, wire bond and encapsulation
`processes to be used to assemble the final semiconductor
`device that incorporates the submount.
`FIGS. 3A-3F are schematic diagrams illustrating a sec(cid:173)
`ond exemplary embodiment 300 of a packaging device for
`a semiconductor die in accordance with the invention. 55
`Packaging device 300 takes the form of a submount for a
`semiconductor die. Packaging device 300 is composed of a
`substrate 310, an interconnecting element 320, a mounting
`pad 330 and a connec