(Attachments: # 1 Exhibit A, # 2 Proposed Order) (Callahan, Steven) (Entered: 07/21/2022) 109 Redacted Copy of 108 Unopposed Sealed Motion to Admit Named Inventor So's Deposition Transcript into Transfer Evidentiary Record by Cloudflare, Inc. by Cloudflare, Inc.. (Attachments: # 1 Exhibit A, # 2 Proposed Order)(Callahan, Steven) (Entered: 07/21/2022) 110 Minute Entry for proceedings held before Judge Derek T. Gilliland: Discovery Hearing held on 7/28/2022.

(DeRieux, Elizabeth) (Entered: 02/09/2023) 190 ORDER GRANTING 189 Motion to Appear Pro Hac Vice for Attorney Bryan J. Mechell for Sable IP, LLC and Sable Networks, Inc. Pursuant to our Administrative Policies and Procedures for Electronic Filing, the attorney hereby granted to practice pro hac vice in this case must register for electronic filing with our court within 10 days of this order.

04/04/2023 Centralized CM/ECF LIVE - U.S. District Court:txwd Parties shall comply with Judge Albright's updated Standing Order Governing Proceedings - Patent Cases available by clicking the hyperlink.

(ad3) (Entered: 04/10/2023) 204 MOTION to Appear Pro Hac Vice by Steven Chase Callahan for Connor A. Scott ( Filing fee $ 100 receipt number ATXWDC-17313414) by on behalf of Cloudflare, Inc.. (Attachments: # 1 Proposed Order).

(Callahan, Steven) (Entered: 04/13/2023) 205 ORDER GRANTING 204 Motion to Appear Pro Hac Vice for Attorney Connor A. Scott for Cloudflare, Inc.,Connor A. Scott for Cloudflare, Inc.. Pursuant to our Administrative Policies and Procedures for Electronic Filing, the attorney hereby granted to practice pro hac vice in this case must register for electronic filing with our court within 10 days of this order.

From complex proprietary based control and automation systems to low cost, Do-It-Yourself (DIY) approaches, all currently available solutions require varying degrees of hardware and software abstraction to accomplish their respective deployment goals.

Access to control however presents considerably greater challenges and to this day no single solution allows for the complete ad-hoc establishment and expansionof an automa- tion plant without imposing the requirement ofcomplex itera- tive developmentof said environment.

Instill another aspect, the system and methodofthe present invention provide a Fabless Development Kit (FDK) that enables device manufacturers to embed unique ASIC func- tionality within their micro-controller (MCU) design process and integration.

The FDK will typically access a databaseofstructured infor- All currently available automation, integration and control mation derived from the hierarchal class systemdefining the products and technologies are nothing more than hardware behavior, operation and communicationcharacteristics ofthe and software acting as figurative ropes and pulleys designed device into which the ASIC is to be imbedded.

Management and control of any component within the ecosystem is manifest through a homogeneous approach madepossible through a combination of data sets submitted within the FDK work-product along with defined parameters established within the class system contained within the logic ofthe imbedded element.

The designer, when defining the The program 19 can be stored in an external or internal series of operations which implement the intended func memory associated with the microprocessor on the tion of the application specific integrated circuit, may target ASIC.

Referring more particularly to FIG. 2, it will be seen tem; FIG. 4 is an illustration of a computer display screen that the ISSC system 10 includes a module or subsystem 20 called KBSC (Knowledge Based Silicon Compiler).

As shown in FIG. 2, the KBSC subsystem 20 includes a number of tion; and modules or programs which collectively provide an FIG. 7 is a schematic illustration similar to FIG. 3, but showing the particular ASIC of the design example.

FEXI displays randon access memory (RAM) 82 to execute the soft this cell list to the designer and waits for him to select a ware functions of the ASIC.

The system as defined in claim 6 wherein said the integrated circuit and by a software subsystem in design constraint input means includes means to enable cluding software instructions executed by a micro processor on the integrated circuit, comprising the user to define one or more design constraints for the application specific integrated circuit selected from the a macro library defining a set of architecture indepen group consisting of annual volume, speed, size, pin dent operations comprised of actions and condi count, packaging type, power consumption, and ther tions wherein at least one of said architecture inde mal stability.

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Because of your intimate knowledge of vending machines derived from the everyday encounters with these beasts (see Figure 7-37), along with the specifications given, Phase I is pretty well covered.

For example, though there is no mention of price changes or multi-pop selection requirements in the specifications for the pop machine, these features are included with no real extra effort or cost.

The first step in this development process is to make a state assignment in accordance with the rules set forth earlier, paying strict attention to asynchronous branching (see Figure 7-43).

This example demonstrates the ease with which small sequential machines can be implemented at the SSI gate and Flip-Flop level, knowing well that other alternatives do exist.

From the netlist it is possible using known manual tech niques or existing VLSI CAD layout systems to gener ate the detailed chip level topological information (mask data) required to produce the particular applica tion specific integrated circuit.

A flow chart is a graphic representation of an algorithm and persons skilled in the appropriate art will recognize that consists of two kinds of blocks or states, namely actions these elements can easily be embodied in other forms, and conditions (decisions).

representation, blocks are used to represent integrated Actions to be performed by each of the rectangles rep architecture specific circuit hardware components for resented in the flowchart are selected from a macro library 23.

Yoon-Pin Simon Foo & Hideaki Kobayashi, “A Framework for Managing VLSI CAD Data in Proceedings of the 1st International Conference on Applications on Artificial Intel ligence to Engineering Problems, Southampton, England, vol.

Goosens, Rabaey, Catthoor, Vanhoof, Jam, De Man, Vande walle, “A Computer-Aided Design Methodology for Map ping DSP Algorithms onto Custom Multiprocessor Archi tectures.” Proc.