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IPR2019-00274, No. 1011 Exhibit - Excerpts from Deposition of Robert L Stevenson, PhD (P.T.A.B. Nov. 9, 2018)
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IPR2019-00274, No. 1011 Exhibit - Excerpts from Deposition of Robert L Stevenson, PhD (P.T.A.B. Nov. 9, 2018)
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IPR2019-00274, No. 1012 Exhibit - Order Construing Claims (P.T.A.B. Nov. 9, 2018)
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IPR2019-00274, No. 1012 Exhibit - Order Construing Claims (P.T.A.B. Nov. 9, 2018)
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IPR2019-00274, No. 1017 Exhibit - VLSI Memory Chip Design (P.T.A.B. Nov. 9, 2018)
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IPR2019-00274, No. 1017 Exhibit - VLSI Memory Chip Design (P.T.A.B. Nov. 9, 2018)
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IPR2019-00274, No. 1002 Exhibit - Declaration of Lawrence T Clark, PhD (P.T.A.B. Nov. 9, 2018)
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IPR2019-00274, No. 1002 Exhibit - Declaration of Lawrence T Clark, PhD (P.T.A.B. Nov. 9, 2018)
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IPR2019-00274, No. 1003 Exhibit - US Patent No 6,650,589 (P.T.A.B. Nov. 9, 2018)
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IPR2019-00274, No. 1003 Exhibit - US Patent No 6,650,589 (P.T.A.B. Nov. 9, 2018)
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IPR2019-00274, No. 1013 Exhibit - Design of High Performance Microprocessor Circuits (P.T.A.B. Nov. 9, 2018)
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IPR2019-00274, No. 1013 Exhibit - Design of High Performance Microprocessor Circuits (P.T.A.B. Nov. 9, 2018)
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IPR2019-00274, No. 1018 Exhibit - Circuits, Interconnections, and Packaging for VLSI (P.T.A.B. Nov. 9, 2018)
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IPR2019-00274, No. 1018 Exhibit - Circuits, Interconnections, and Packaging for VLSI (P.T.A.B. Nov. 9, 2018)
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IPR2019-00274, No. 1019 Exhibit - File History of 559 Patent (P.T.A.B. Nov. 9, 2018)
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IPR2019-00274, No. 1019 Exhibit - File History of 559 Patent (P.T.A.B. Nov. 9, 2018)
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IPR2019-00274, No. 1009 Exhibit - Excerpts from Claim Construction Hearing Transcript (P.T.A.B. Nov. 9, 2018)
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IPR2019-00274, No. 1009 Exhibit - Excerpts from Claim Construction Hearing Transcript (P.T.A.B. Nov. 9, 2018)
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IPR2019-00274, No. 1004 Exhibit - US Patent No 6,920,071 (P.T.A.B. Nov. 9, 2018)
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IPR2019-00274, No. 1004 Exhibit - US Patent No 6,920,071 (P.T.A.B. Nov. 9, 2018)
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IPR2019-00274, No. 1007 Exhibit - Apple Incs Opening Claim Construction Brief (P.T.A.B. Nov. 9, 2018)
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IPR2019-00274, No. 1007 Exhibit - Apple Incs Opening Claim Construction Brief (P.T.A.B. Nov. 9, 2018)
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IPR2019-00274, No. 1015 Exhibit - US Patent No 3,801,831 (P.T.A.B. Nov. 9, 2018)
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IPR2019-00274, No. 1015 Exhibit - US Patent No 3,801,831 (P.T.A.B. Nov. 9, 2018)
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IPR2019-00274, No. 1010 Exhibit - Excerpts of Declaration of Robert L Stevenson (P.T.A.B. Nov. 9, 2018)
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IPR2019-00274, No. 1010 Exhibit - Excerpts of Declaration of Robert L Stevenson (P.T.A.B. Nov. 9, 2018)
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Docket
12/325,476,
U.S. Patent Application
(Dec. 1, 2008)
Cite Docket
INTEGRATED CIRCUIT WITH SEPARATE SUPPLY VOLTAGE FOR MEMORY THAT IS DIFFERENT FROM LOGIC CIRCUIT SUPPLY VOLTAGE, 12/325,476 (U.S. Pat. App.)
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