Note that in some cases where the two trees are combined, the total depth in logic blocks some variables are common in many product terms, it is possible to reduce the number of levels by one less than given by this expression.
Notice, however, that the five-input lookup ta- ble achieves similar performance in both cases, and the accuracy of these experiments makes this small spread in- D-ro-r = NL X (DIU + D R ) D,, - Std.
In addition, as noted in Section 111-A, the de- lay model does not account for the increase in delay due to extra capacitive loading from the higher number of pins, and so the marginal improvement shown in Table IV from K = 5 to K = 7 may be lost.
The actual choice of logic block might be more strongly influenced by the fact that each added input doubles the number of bits in the lookup table, and hence the area.
Rose, R. J. Francis, D. Lewis, and P. Chow, “Architecture of field-programmable gate arrays: The effect of logic block function- ality on area efficiency,” IEEE J. Solid-state Circuirs, vol.