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1019 Exhibit: Exhibit Singh

Document IPR2023-00864, No. 1019 Exhibit - Exhibit Singh (P.T.A.B. Apr. 20, 2023)
Note that in some cases where the two trees are combined, the total depth in logic blocks some variables are common in many product terms, it is possible to reduce the number of levels by one less than given by this expression.
Notice, however, that the five-input lookup ta- ble achieves similar performance in both cases, and the accuracy of these experiments makes this small spread in- D-ro-r = NL X (DIU + D R ) D,, - Std.
In addition, as noted in Section 111-A, the de- lay model does not account for the increase in delay due to extra capacitive loading from the higher number of pins, and so the marginal improvement shown in Table IV from K = 5 to K = 7 may be lost.
The actual choice of logic block might be more strongly influenced by the fact that each added input doubles the number of bits in the lookup table, and hence the area.
Rose, R. J. Francis, D. Lewis, and P. Chow, “Architecture of field-programmable gate arrays: The effect of logic block function- ality on area efficiency,” IEEE J. Solid-state Circuirs, vol.
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1023 Exhibit: Exhibit Chow

Document IPR2023-00864, No. 1023 Exhibit - Exhibit Chow (P.T.A.B. Apr. 20, 2023)
In addition, internal nodes of n-channel pass transistor circuits may not require contacts, saving area and reducing junction capacitance.
An example result is shown in Fig. 9, which shows the effect of varying the logic block output driver size on the total delay of the critical path.
In UTFPGA1 [2], we attempted to use the same C-block layout for both the vertical and horizontal channels, but this resulted in a very poor tile floor plan because it was difficult to pack the pieces together.
An added benefit that has not been explored at this point is that, with this ability to configure the tile after the hard layout work is done, it is possible to try other hard-wired interconnections for the LUT’s and other channel segmentation distributions.
He is currently with Aristo Technol- ogy Inc., Cupertino, CA, where he is developing the graphical user interface software for a set of block-level system IC planning and implementation design tools.
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1009 Exhibit: Exhibit Villero Decl Part 2

Document IPR2023-00864, No. 1009-2 Exhibit - Exhibit Villero Decl Part 2 (P.T.A.B. Apr. 20, 2023)
Recent FPGAs from Xilinx, Altera, Lucent Technologies, Actel and Yantis have all grouped several LUTs together into a larger logic block, but there has been little published work investigating any of these questions.
Instead, we follow the procedure described in Section 2.2.4; we model pass transistors and buffers by equivalent cir cuits composed of resistors, capacitors, and idealized, constant delay elements.
After a routing is complete, VPR uses these simplified models of pass transistors and buffers, as well as metal capacitance and resistance data, (all of which is specified in the architecture description file) to build an equivalent RC-tree for each net.
We ran 20 benchmark circuits through the experimental flow described in Section 6.2, and deter mined the area-efficiency and speed of each in FPGA architectures employing differ ent logic cluster sizes.
We ran the twenty largest MCNC benchmarks through the flow of Figure 7.1 and determined the routing area required and the critical path delay achieved by each cir cuit in each architecture of interest.
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1038 Exhibit: Exhibit National Judicial Caseload Profile 2022 12

Document IPR2023-00864, No. 1038 Exhibit - Exhibit National Judicial Caseload Profile 2022 12 (P.T.A.B. Apr. 20, 2023)
- - NOTE: Criminal data in this profile count defendants rather than cases and therefore will not match previously published numbers.
2,601 - - NOTE: Criminal data in this profile count defendants rather than cases and therefore will not match previously published numbers.
- - NOTE: Criminal data in this profile count defendants rather than cases and therefore will not match previously published numbers.
- - - - NOTE: Criminal data in this profile count defendants rather than cases and therefore will not match previously published numbers.
1,003 - NOTE: Criminal data in this profile count defendants rather than cases and therefore will not match previously published numbers.
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1030 Exhibit: Exhibit Japanese Complaint in Iida v Intel

Document IPR2023-00864, No. 1030 Exhibit - Exhibit Japanese Complaint in Iida v Intel (P.T.A.B. Apr. 20, 2023)

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1001 Exhibit: Exhibit US Patent No 6,812,737

Document IPR2023-00864, No. 1001 Exhibit - Exhibit US Patent No 6,812,737 (P.T.A.B. Apr. 20, 2023)

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1022 Exhibit: Exhibit Cherepacha

Document IPR2023-00864, No. 1022 Exhibit - Exhibit Cherepacha (P.T.A.B. Apr. 20, 2023)

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1004 Exhibit: Exhibit Melvin CV

Document IPR2023-00864, No. 1004 Exhibit - Exhibit Melvin CV (P.T.A.B. Apr. 20, 2023)

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1016 Exhibit: Exhibit MacPherson Decl for He

Document IPR2023-00864, No. 1016 Exhibit - Exhibit MacPherson Decl for He (P.T.A.B. Apr. 20, 2023)

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1041 Exhibit: Exhibit 2023 03 20 Iida Brief

Document IPR2023-00864, No. 1041 Exhibit - Exhibit 2023 03 20 Iida Brief (P.T.A.B. Apr. 20, 2023)

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1044 Exhibit: Exhibit Weste

Document IPR2023-00864, No. 1044 Exhibit - Exhibit Weste (P.T.A.B. Apr. 20, 2023)

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1009 Exhibit: Exhibit Villero Decl Part 3

Document IPR2023-00864, No. 1009-3 Exhibit - Exhibit Villero Decl Part 3 (P.T.A.B. Apr. 20, 2023)

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1028 Exhibit: Exhibit Cong

Document IPR2023-00864, No. 1028 Exhibit - Exhibit Cong (P.T.A.B. Apr. 20, 2023)

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1027 Exhibit: Exhibit Amano

Document IPR2023-00864, No. 1027 Exhibit - Exhibit Amano (P.T.A.B. Apr. 20, 2023)

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1009 Exhibit: Exhibit Villero Decl Part 1

Document IPR2023-00864, No. 1009 Exhibit - Exhibit Villero Decl Part 1 (P.T.A.B. Apr. 20, 2023)

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