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Displaying 189-203 of 312 results

1002 Exhibit: 945 File History Part 1 of 8

Document IPR2016-00894, No. 1002 Exhibit - 945 File History Part 1 of 8 (P.T.A.B. Apr. 15, 2016)
No. 60/429,641 filed November 27, 2002, entitled “Dividing Work Among Multiple Graphics Pipelines Using a Super-Tiling Technique", having as inventors Mark M. Leather and Eric Demers, and owned by instant assignee.
The front end circuitry 35 generates the pixel data 36 by performing, for example, clipping, lighting, spatial transformations, matrix operations and rasterizing 0013
Alternatively, the third and fourth graphics pipelines may be configured to be on multiple chips interconnected by a communication path, for example, a synchronization signal or data bus.
This is accomplished, for example, by the back end circuitry 39 performing color, shading, blending, texturing and/or z—bul'fering operations on the pixels within the portions (e.g. 81-82) of the tiles (e.g. 72 and 75) they are responsible for.
Bechen Cl Atlditianal legisttsmd ptnstidonettsi nsmud on supplemmul Itcgisaered Pl1I.c‘ll.liDl¥34' Information shut PTOJSEJOIJC numbed has-cw.\ Direct all correspondence to: Vedder, Price.
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1006 Exhibit: Perego

Document IPR2016-00894, No. 1006 Exhibit - Perego (P.T.A.B. Apr. 15, 2016)
Inventor: Richard E. Perego, San Jose, CA (US) (73) Assignee: Rambus Inc., Los Altos, CA (US) (_ * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.s.C. 154(b) by 396 days. '
The number of conductors that can be used is generally bound by cost constraints on the memory controller/graphics controller package or system board , design.
An example of the procedure described with respect to FIG. 4 will be described with reference to FIG. 5, which illustrates a graphical rendering surface divided into sixteen different sections or “tiles” (four rows and four columns).
An apparatus as recited in claim 1 further including an interconnect configured to couple a plurality of modules to the memory controller.
An apparatus as recited in claim 14 further including an interconnect configured to couple the plurality of mod- ules to the memory controller.
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1009 Exhibit: Gove

Document IPR2016-00894, No. 1009 Exhibit - Gove (P.T.A.B. Apr. 15, 2016)
First of all, an architecture must be created which allows for the eflicient movement of information, while at the same time consuming a minmum amount of precious silicon chip space in order to achieve a high performance to cost ratio.
The crossbar switch is constructed with difierenl length links serving dilferent functions so as to conserve space while still providing a high degree of operational llcxibility.
This arrange- ment also assumes a unilied contention arrangement for the memory access via bus 34 so that all ol‘ the processors can communicate and can maintain order while they each per- form their own independent operations.
Just as it is diflicult to determine the shape of an elephant from a grasp of its trunk, it is equally dilficult to obtain meaningful information from an image without access to clilferent portions of the pixel data.
The image is then moved upwards through the various possibilities for edge extraction 1109, line linkage 1107, corner or vertices recognition I105, histogram 1110, statistical properties 1108 and segmentation 1106.
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1012 Exhibit: Whitman Part 1 of 4

Document IPR2016-00894, No. 1012 Exhibit - Whitman Part 1 of 4 (P.T.A.B. Apr. 15, 2016)

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1002 Exhibit: 945 File History Part 5 of 8

Document IPR2016-00894, No. 1002-5 Exhibit - 945 File History Part 5 of 8 (P.T.A.B. Apr. 15, 2016)

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1011 Exhibit: Watt Part 4 of 6

Document IPR2016-00894, No. 1011-4 Exhibit - Watt Part 4 of 6 (P.T.A.B. Apr. 15, 2016)

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1003 Exhibit: Fussell Declaration

Document IPR2016-00894, No. 1003 Exhibit - Fussell Declaration (P.T.A.B. Apr. 15, 2016)

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1013 Exhibit: Moore

Document IPR2016-00894, No. 1013 Exhibit - Moore (P.T.A.B. Apr. 15, 2016)

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1015 Exhibit: TMS320C80 Datasheet

Document IPR2016-00894, No. 1015 Exhibit - TMS320C80 Datasheet (P.T.A.B. Apr. 15, 2016)

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1011 Exhibit: Watt Part 5 of 6

Document IPR2016-00894, No. 1011-5 Exhibit - Watt Part 5 of 6 (P.T.A.B. Apr. 15, 2016)

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1002 Exhibit: 945 File History Part 2 of 8

Document IPR2016-00894, No. 1002-2 Exhibit - 945 File History Part 2 of 8 (P.T.A.B. Apr. 15, 2016)

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1010 Exhibit: Foley Part 7 of 7

Document IPR2016-00894, No. 1010-7 Exhibit - Foley Part 7 of 7 (P.T.A.B. Apr. 15, 2016)

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1008 Exhibit: Narayanaswami

Document IPR2016-00894, No. 1008 Exhibit - Narayanaswami (P.T.A.B. Apr. 15, 2016)

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1004 Exhibit: Furtner

Document IPR2016-00894, No. 1004 Exhibit - Furtner (P.T.A.B. Apr. 15, 2016)

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1011 Exhibit: Watt Part 1 of 6

Document IPR2016-00894, No. 1011 Exhibit - Watt Part 1 of 6 (P.T.A.B. Apr. 15, 2016)

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