Descriptions of parallel computing systems are found I in US Pat. Nos. 4,636,948, assigned to IBM; 4,514,807 to Tatsuo; 4,814,980 and 4,730,322 to California Insti tute of Technology; 4,811,214 to 4,543,630 to Teradata; 4,748,660 to Jeumont-Schneider; and 4,598,400 to Thinking Machines Corp.
These patents describe vari ous architectures for parallel processing that represent 5,181,017 earlier development of routing systems similar to the subject invention.
If the received byte is a LINK-CLOSE command the processing continues in function block 9190 where the path through the crossbar switch is closed and the state becomes IDLE.
The delay between END-OF-MESSAGE and ACKNOWLEDGE or LINK-CLOSE should be as short as possible since the routing mechanism holds a path back to the source node open until the ?nal LINK CLOSE is seen.
The method as recited in claim 1, wherein in step (a) said header portion includes at least one bit position corresponding to each output link transmitter in said one node, said method comprising the further steps of: responding to a bit group state to establish said con nection to a corresponding output link transmitter, except if said corresponding output link transmitter manifests busy or inoperative signals to indicate a non-available status; and transmitting to said preceding node a link-close signal in response to said manifestation of said busy or inoperative signals.