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METHOD AND SYSTEM FOR REDUCING INTER-LAYER CAPACITANCE IN INTEGRATED CIRCUITS

10/991,107 | U.S. Patent Application

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Location ELECTRONIC
Filed Nov. 17, 2004
Examiner KEVIN M PICARDAT
Class 438
Art Group 2822
Patent No. 7,396,760
Case Type Utility - 438/626000
Status Patented Case
Child 12/156,281 Patented
Last Updated: 4 years, 7 months ago
Date # Transaction