ATTY. DKT. 63219-821530 (JBL-0071-PV)
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`SYNCHRONOUS BUCK INVERTER
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`FIELD OF THE DISCLOSURE
`
`[0001]
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`The present disclosure relates to power conversion, and, more specifically, the
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`present disclosure relates to multi-stage switching for inverters, such as may utilize zero-cross
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`discharge to reduce distortion and increase efficiency.
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`BACKGROUND
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`[0002]
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`Certain power converters are configured to convert direct current (DC) to
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`alternating current (AC). Such DC-ACconverters are commonly referred to as inverters.
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`Inverters have many industrial and commercial uses including, for example, converting DC
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`powcrfrom a battery or photovoltaic source into AC powerfor a load. Inverters may also be
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`used to supply AC powerto an electric utility grid. A grid-tied inverter is a power inverter that
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`converts direct current (DC) electricity into alternating current (AC) with an ability to
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`synchronize to interface with a utility line. The applications for such an inverter include
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`converting DC sources, such as solar panels or small wind turbines, into AC for tying with the
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`grid. Photovoltaics (PV) in, for example, the aforementioned solar panels generate electrical
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`powerby converting solar radiation into direct current electricity using semiconductors that
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`exhibit the photovoltaic effect.
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`[0003]
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`Certain inverters arc commonly configured to opcrate without a transformer.
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`Examples of such inverters are disclosed in Salmi, et al., ““Transformerless Microinverter for
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`Photovoltaic Systems’, pp. 639-650, vol. 3, issue 4, Int’] Journal of Energy and Environment
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`

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`ATTY. DKT. 63219-821530 (JBL-0071-PV)
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`(2012); Reddyet al., “Analysis and Modeling of Transformerless Photovoltaic Inverter
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`Systems”, pp. 2932-2938, vol. 3, issue 5, Int’! Journal of Modern Engineering Research (2013);
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`and Dreheret al., “Comparison of H-Bridge Single-Phase Transformerless PV String Inverters”’,
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`10th TIEEE/IAS Int’1 Conference on Industry Applications, pp.1-8 (Nov. 2012).
`
`[0004]
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`Photovoltaic (PV) power supplied to a utility grid is increasing in popularity as
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`the world’s power demandsare increasing. Solid-state inverters have been shownto be an
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`important technology for coupling PV systems into the grid. Integration of PV power generation
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`systems in the grid plays an important role in supplying electric power in an environmentally-
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`friendly manner. A commonly-configured grid-connected PV system comprises of a PV panel,
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`and a DC/AC Inverter that is operatively connected to the grid. This configuration is used for
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`powergeneration in places or sites accessed by the electric utility grid. Depending on the
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`application and requirements, a PV system can either be a stand-alone or hybrid system.
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`Gencrally the PV system comprises of a PV gcncrator whichis a set of scrics-parallcl electrically
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`interconnected solar panels. PV panels are commonly rated in terms of a nominal peak powerof
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`the panel at standard test conditions (STC). A PV generator provides the total installed power,
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`whichis the sum of nominal peak powerof each solar panel present in the PV installation. This
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`PV generator is connected to an inverter whichis, in turn, connected to an AC/DC load and/or
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`grid.
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`[0005]
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`Inverters are important componentsto grid-connected PV systems and their major
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`role is to convert DC power into AC power. Furthermore, inverter interfacing PV module(s)
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`with the grid ensures that the PV module(s) is operated at the maximum power point (MPPT).
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`Based on the photovoltaic arrays’ output voltage, output power level and applications, the
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`

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`ATTY. DKT. 63219-821530 (JBL-0071-PV)
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`photovoltaic grid-connected system may adoptdifferent topologies. The grid-connected inverter
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`may be designed for peak power and may obey conditionsrelated to issues like power quality,
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`detection of islanding operation, grounding, MPPT and long-life. Inverter maximum poweris
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`typically referred to the total installed powerof the PV generator, and should optimize the energy
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`injected to grid. Inverter PV topologies may include centralized inverters, string inverters, multi-
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`string inverter and module inverters.
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`[0006]
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`Although the foregoing discussion focuses particularly on PV systems, those
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`skilled in the art will appreciate that issues that arise in PV systems similarly arise in other
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`contexts that require power conversion/inversion. Such contexts include, but are not limited to,
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`sine wave generating inverters, micro-inverters, power supplies, and powerdistribution systems.
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`[0007]
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`A significant one of these issues with conventional power inverters is that they
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`carry excessive noise in the output signal. Therefore, improvements to inverter noise control,
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`and accordingly efficiency, are neededin theart.
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`SUMMARY
`
`[0008]
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`Accordingly, an improved inverter topology is disclosed using high frequency
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`switching control to generate a low frequency sine wave. The main switching may berealized
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`using a synchronous-buck topologythat is configured to invert every half cycle of a lower
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`frequency. The inverting process may create a positive and negative transition true sine wave.
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`The low frequency switching stage may be configured to operate as a true zero voltage switching
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`(ZVS) and zero current switching (ZCS) drive.
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`

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`ATTY. DKT. 63219-821530 (JBL-0071-PV)
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`[0009]
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`The disclosed inverter may be further configured with an output capacitor,
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`wherein the charge on the output capacitor may be discharged to zero upon every zero crossing
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`of the low frequency switching stage. The benefit of this topology, as comparedto a traditional
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`synchronous buckinverter, is that the discharge of energy from the output storage capacitor
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`every half cycle creates very low distortion. That is, during this discharge of energy, the zero
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`crossing distortion in the low frequency sine waveis greatly reduced.
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`[0010]
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`Comparisons will be madeto a full-bridge topology, currently deployed in a
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`majority of grid-tied inverters presently, to the presently disclosed exemplary embodimentsto
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`demonstrate advantageous improvements in efficiency, load variation and total harmonic
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`distortion.
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`BRIEF DESCRIPTION OF THE FIGURES
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`[OO11]
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`The present disclosure will become more fully understood from the detailed
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`description given herein below and the accompanying drawings whichare given by way of
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`illustration only, and which thus do not limit the present disclosure, and wherein:
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`[0012]
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`FIG. 1A illustrates an exemplary full bridge inverter topology that is known in the
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`art;
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`[0013]
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`VIG. 1B illustrates a switching sequence for switches S1-S4 of PIG. 1A under a
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`positive half wave and negative half wave condition;
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`[0014]
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`FIGs. 2A-2E illustrate waveforms exemplifying typical operational conditions for
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`the example of FIG. 1A;
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`

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`ATTY. DKT. 63219-821530 (JBL-0071-PV)
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`[0015]
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`FIG. 3A illustrates an exemplary synchronous buck inverter topology under one
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`exemplary embodiment, where the inverter comprises a high-frequency switching portion, a
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`synchronous buck portion and a low frequency switching stage coupled to a discharge capacitor
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`configured to be coupledto a load;
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`[0016]
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`FIG.3B illustrates a switching sequence for switches A-D of the embodimentof
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`FIG. 3A underpositive half wave and negative half wave conditions;
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`[0017]
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`T'IG. 3C provides another illustration of a synchronous buck inverter under
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`another embodiment;
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`[0018]
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`FIG.4 illustrates a switch sequence diagram that includes four switching sections
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`over the course of an exemplary sine wave for switches A-D of the embodiments of FIG. 3A and
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`3C;
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`[0019]
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`T'IGs. 4A-B illustrate an exemplary switching transitions of switches A-D ofthe
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`embodiment of FIG. 3A during a first switching section (at peak of positive sine wave) of FIG.
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`4;
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`[0020]
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`FIG 4C schematically illustrates a synchronous current flow through a load and a
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`switching configuration for switches A-D for time period (a) of FIG. 4B under one exemplary
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`embodiment;
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`[0021]
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`FIG 4D schematically illustrates a buck current flow through a load and a
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`switching configuration for switches A-D for time period (b) of FIG. 4B under one exemplary
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`embodiment;
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`

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`ATTY. DKT. 63219-821530 (JBL-0071-PV)
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`[0022]
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`FIGs. 4E-Fillustrate an exemplary switching transitions of switches A-D of the
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`embodiment of FIG. 3A during a second switching section (at positive-negative zero crossing
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`transition of sine wave) of FIG.4;
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`[0023]
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`FIG 4G schematically illustrates a buck/synchronous current flow through a load
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`and a switching configuration for switches A-D for time period (a) of FIG. 4F under one
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`exemplary embodiment;
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`[0024]
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`T'IG 411 schematically illustrates a synchronous/buck current flow through a load
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`and a switching configuration for switches A-D for time period (b) of FIG. 4F under one
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`exemplary embodiment;
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`[0025]
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`FIGs. 4]-J illustrate an exemplary switching transitions of switches A-D of the
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`embodiment of FIG. 3A during a third switching section (at peak negative of sine wave) of FIG.
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`4;
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`[0026]
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`FIG 4K schematically illustrates a synchronouscurrent flow through a load and a
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`switching configuration for switches A-D for time period (a) of FIG. 4J under one exemplary
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`embodiment;
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`[0027]
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`FIG 4L schematically illustrates a buck current flow through a load and a
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`switching configuration for switches A-D for time period (b) of PIG. 4] under one exemplary
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`embodiment;
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`

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`ATTY. DKT. 63219-821530 (JBL-0071-PV)
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`[0028]
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`FIGs. 4M-Nillustrate an exemplary switching transitions of switches A-D of the
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`embodiment of FIG. 3A during a fourth switching section (at negative-positive zero crossing
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`transition of sine wave) of FIG.4;
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`[0029]
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`FIG 40 schematically illustrates a synchronous/buck current flow through a load
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`and a switching configuration for switches A-D for time period (a) of FIG. 4N under one
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`exemplary embodiment;
`
`[0030]
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`T'IG 4P schematically illustrates a buck/synchronouscurrent flow through a load
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`and a switching configuration for switches A-D for time period (b) of FIG. 4N under one
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`exemplary embodiment;
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`[0031]
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`FIGs. 5A-B illustrate an exemplary gate drive waveform and current waveform
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`for a positive signal condition for switches A andBforthe first switching section illustrated in
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`the exemplary embodiments of FIG. 4A-D above;
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`[0032]
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`FIGs. 6A-B illustrate an exemplary gate drive waveform and current waveform
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`for a zero crossing condition for switches A and B for the second switching section illustrated in
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`the exemplary embodiments of FIG. 4E-G above;
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`[0033]
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`FIGs. 7A-B illustrate an exemplary gate drive waveform and current waveform
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`for a negative signal condition for switches A and B for the third switching section illustrated in
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`the exemplary embodiments of FIG. 4I-L above;
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`

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`ATTY. DKT. 63219-821530 (JBL-0071-PV)
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`[0034]
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`FIGs. 8A-B illustrate an exemplary gate drive waveform and current waveform
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`for a zero crossing signal condition for switches A and B for the fourth switching section
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`illustrated in the exemplary embodiments of FIG. 4M-P above;
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`[0035]
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`FIGs. 9A-E illustrate waveforms exemplifying operational conditions for the
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`embodiment of FIG. 3A;
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`[0036]
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`FIG. 10A illustrates an exemplary waveform for the synchronous-buckinverter of
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`TIG. 3A and FIG. 4 showing improved voltage and current distortion; and
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`[0037]
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`FIG. 10B illustrates an exemplary gate drive waveform for switches C and D for
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`the synchronous-buck inverter of FIG. 3A and FIG.4.
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`DETAILED DESCRIPTION
`
`[0038]
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`The figures and descriptions provided herein may have been simplified to
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`illustrate aspects that are relevant for a clear understanding of the herein described devices,
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`systems, and methods, while eliminating, for the purpose of clarity, other aspects that may be
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`found in typical similar devices, systems, and methods. Those of ordinary skill may thus
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`recognize that other elements and/or operations may be desirable and/or necessary to implement
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`the devices, systems, and methods described herein. But because such elements and operations
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`are knownin the art, and because they do not facilitate a better understanding ofthe present
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`disclosure, a discussion of such elements and operations may not be provided herein. However,
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`the present disclosure is deemed to inherently include all such elements, variations, and
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`modifications to the described aspects that would be knownto those of ordinary skill in theart.
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`

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`ATTY. DKT. 63219-821530 (JBL-0071-PV)
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`[0039]
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`Exemplary embodiments are provided throughoutso that this disclosure is
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`sufficiently thorough and fully conveys the scope of the disclosed embodiments to those who are
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`skilled in the art. Numerousspecific details are set forth, such as examples of specific
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`components, devices, and methods, to provide this thorough understanding of embodiments of
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`the present disclosure. Nevertheless, it will be apparent to those skilled in the art that specific
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`disclosed details need not be employed, and that exemplary embodiments may be embodied in
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`different forms. As such, the exemplary embodiments should not be construed to limit the scope
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`of the disclosure. In some exemplary embodiments, well-known processes, well-known device
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`structures, and well-known technologies may not be described in detail.
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`[0040]
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`The terminology used herein is for the purpose of describing particular exemplary
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`embodiments only and is not intendedto be limiting. As used herein, the singular forms "a",
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`"an
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`and "the" may be intended to include the plural forms as well, unless the context clearly indicates
`ott
`tts
`"including," and "having," arc inclusive and
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`otherwise. ‘he terms "compriscs,”
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`"comprising,"
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`therefore specify the presence of stated features, integers, steps, operations, elements, and/or
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`components, but do not preclude the presence or addition of one or more other features, integers,
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`steps, operations, elements, components, and/or groups thereof. The steps, processes, and
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`operations described herein are not to be construed as necessarily requiring their respective
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`performancein the particular order discussedor illustrated, unless specifically identified as a
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`preferred order of performance.It is also to be understoodthat additional or alternative steps may
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`be employed.
`
`[0041]
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`mor
`When an elementor layer is referred to as being "on",
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`moot
`"engaged to”,
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`"connected
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`to" or "coupled to" another elementor layer, it may be directly on, engaged, connected or
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`

`

`ATTY. DKT. 63219-821530 (JBL-0071-PV)
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`coupled to the other element or layer, or intervening elements or layers may be present. In
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`contrast, when an element is referred to as being "directly on," "directly engaged to", "directly
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`connected to" or "directly coupled to" another elementor layer, there may be no intervening
`
`elements or layers present. Other words used to describe the relationship between elements
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`should be interpreted in a like fashion (e.g., "between" versus "directly between,”
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`"adjacent"
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`versus "directly adjacent," etc.). As used herein, the term "and/or" includes any and all
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`combinations of one or more of the associated listed items.
`
`[0042]
`
`Although the termsfirst, second, third, etc. may be used herein to describe various
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`elements, components, regions, layers and/or sections, these elements, components, regions,
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`layers and/orsections should not be limited by these terms. These terms may be only used to
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`distinguish one element, component, region, layer or section from another element, component,
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`region, layer or section. Terms such as "first,"
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`"second," and other numerical terms when used
`
`hercin do not imply a sequence or order unless clearly indicated by the context.
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`‘Thus, a first
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`element, component, region, layer or section discussed below could be termed a second element,
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`component, region, layer or section without departing from the teachings of the exemplary
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`embodiments.
`
`[0043]
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`Turning now to FIG. 1A, a conventional inverter is illustrated and will be used for
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`reference for the embodiments discussed throughout, such as in connection with the discussion
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`of FIGs. 3A-10B. It should be understood by those skilled in the art that the specific
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`configuration in FIG. 1A is merely used for illustrative purposes andis not intended to limit the
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`present disclosure.
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`10
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`

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`ATTY. DKT. 63219-821530 (JBL-0071-PV)
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`[0044]
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`The inverter of FIG. 1A is configured as a full-bridge inverter topology and
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`comprises of four switches, two output inductors and an output storage capacitor. In this case,
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`L2 maybe the same as L1 andthe total common-modevoltage Vem is ’Vnc. Conventionally,
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`the full-bridge uses one of two control strategies. For the bipolar PWM control strategy, one
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`group of diagonal switches operates at a switching frequency complementaryto the other group
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`of switches. As a result, the inverter output voltage has only two levels which results in high
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`current ripple across the output inductors. An exemplary switching sequencefor the circuit of
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`FIG. 1A is shown where, for a sine wave input, switches S,; and S, are closed, while switches S2
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`and S3 are open on the positive half wave of the input. Conversely, switches S; and Sy are open,
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`while switches $2 and $3 are closed on the negative half wave of the input.
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`[0045]
`
`The major drawback of employing the full-bridge with, for example, bipolar
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`PWM isthe high powerlosses due to two [actors. Thefirst factor is the internal reactive power
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`flow inside the inverter, and the second is the double switching frequency required to obtain the
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`same inductor current ripple frequency. The second control strategy that may be applied to the
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`full-bridge of FIG. 1A is the unipolar PWM. In such modulation, the inverter output voltage has
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`three levels, which decreases significantly the current ripple across the inductors. With this
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`modulation, the inverter has high efficiency due to the absence of the internal reactive power
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`flow. However, with this control strategy, the inverter generates high leakage currentlevel.
`
`[0046]
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`Accordingly, other topologies have endeavored to combine the advantages of the
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`bipolar PWM (Cow leakage current level) and those of the unipolar PWM (Highefficiency, low
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`current ripple and three level inverter output voltages). These endeavors have been undertaken
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`by adding extra switches to the full-bridge topology. These extra switches disconnect the PV
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`11
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`ATTY. DKT. 63219-821530 (JBL-0071-PV)
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`array from the grid during the freewheeling periods. Nevertheless, these and like circuits such as
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`that illustrated in FIG. 1A carry excessive harmonic distortions in the signal, and thus operate at
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`a reducedefficiency.
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`[0047]
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`FIG. 2A is an exemplary simulated waveform for the circuit of FIG. 1A, operating
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`under a -0.7 power factor (PF) load, utilizing 100Q in series with a 26.54 uF capacitor. As can
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`be determined from the voltage (V) and current (I) waveforms, voltage distortion is
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`approximately 24%, while current distortion is approximately 34.1%. As will be appreciated by
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`those skilled in the art, the distortion is particularly acute around the zero crossing phases. As
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`the resistance is reduced to 20.63Q in series with a 130.3 uF capacitor, the total harmonic
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`distortion increases to a point that it could not be measured,as illustrated in FIG. 2B.
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`[0048]
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`In FIG. 2C, utilizing a unity power factor load of 1kQ for the circuit of FIG. 1A,
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`the total harmonic distortion measured for the voltage (V) in the simulated waveform is 26.9%,
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`and 25.1% for the current (1). Utilizing a unity power factor with a reduced load of 100Q for the
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`circuit of FIG. 1A, the total harmonic distortion measured for the voltage (V) is 2.79%, and
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`3.41%for the current (I), with a total power of 585.6W as illustrated in the simulated waveform
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`of FIG. 2D. In FIG. 2E, utilizing a unity power factor load of 28.2 at approximately 2kW,total
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`harmonic distortion measured for the voltage (V) was 1.52%, and 1.71% for the current (1), with
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`an efficiency of 98.2%.
`
`[0049]
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`Buck converters, and particularly synchronous buck converters, may
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`advantageously be configured for inverter applications to provide less noisy and moreefficient
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`power output. The use of conventional buck converters for inverters is knownin the art, and
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`examples of such applications may be found in U.S. Pat. No. 8,488,350 to Sigamani, titled “DC-
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`12
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`ATTY. DKT. 63219-821530 (JBL-0071-PV)
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`AC Inverters’’, issued July 16, 2013, and U.S. Pat. No. 7,872,887 to Nishio etal., tithed “DC-AC
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`Inverter Powering a Single Phase Commercial Power System’, issued Jan. 18, 2011, both of
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`which are incorporated by reference in their entirety herein. While the aforementioned
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`configurations provide some improvement over conventional inverter topologies, further
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`improvements mayberealized utilizing configurations disclosed herein.
`
`[0050]
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`Turning now to FIG. 3A, synchronous buck inverter topology 300 is disclosed in
`
`an exemplary embodiment. Inverter 300 comprises a DC source 301 and a house supply 302 for
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`providing positive and negative voltages to high frequency switches A-B and low frequency
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`switches C-D, as shown. In an embodiment, switches A-D are comprised of high frequency
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`switches, such as field effect transistors (FETs). It should be understood by those skilled in the
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`art that other switches or suitable switching mechanisms may be employed, depending on the
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`specific application of the inverter. Inverter 300 may comprise a high frequency switching
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`control (1) comprising controller 303 and sensing circuit 304.
`
`[0051]
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`In an embodiment, controller may comprise a current-mode PWM controller (see
`
`FIG. 3C) and sensing circuit 304 comprises a peak current sense and an output voltage sense (see
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`refs. 304A-B of FIG. 3C). Controller 303 may be operatively coupled to a gate of each of
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`switches A-D, while sensing circuit 304 may be coupled to a load line as is shownillustratively
`
`in FIG. 3A. Alternatively, controller may be a microprocessor running firmware to control
`
`switches A-D.
`
`[0052]
`
`Controller 303 may be configured to provide a low frequency sine wave(or other
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`suitable signal) to effect switching control on the synchronous-buckportion of inverter 300.
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`Main switching may berealized using synchronous-buck switching portion (2), comprising
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`13
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`

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`ATTY. DKT. 63219-821530 (JBL-0071-PV)
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`switches A and B, to invert every half cycle of the frequencyof the signal provided by controller
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`303. The inverting process thus creates a positive and negative transition of the sine wavesignal.
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`Low frequency switching stage (3) comprises switches C and D and may be configured to
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`operate as zero voltage switching (ZVS) and zero current switching (ZCS) drives
`
`[0053]
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`Notably, using the configuration of FIG. 3A, the charge on output capacitor 305 is
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`discharged to zero on every zero crossing of low frequency switching stage (3). Compared to a
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`conventional synchronous buck, the configuration of FIG. 3A advantageously discharges energy
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`every half cycle. During this discharge of energy, the zero crossing distortion in the low
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`frequency sine waveis greatly reduced.
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`[0054]
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`‘Turning now to FIG. 3B, an exemplary switching scquencecis illustrated whercin
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`switches A and B of the synchronous-buck switching portion (2) simultaneously andalternately
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`provide high frequency PWM (x) and high frequency PWM complement (x’) for each positive
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`half wave and negative half wave. Switches C and D for the low frequency switching stage (3)
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`are configured such that switch C is Orrfor each positive half wave and ON for each negative
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`half wave, while switch D is ON for each positive half wave and OFF for each negative half wave.
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`[0055]
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`FIG. 3C is another exemplary embodiment of a synchronous buck inverter,
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`similar to inverter 300, wherein high voltage regulator house supply 302 receives inpul power
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`(+HV, -HV) from a source (c.g., 301) and produccs output voltage +V for cach of the switch
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`drives (A-D Drive) and voltage +VL for current-mode PWM controller 303, peak current sense
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`304A and output voltage sense 304B. Controller 303 may provide low frequencysignals (e.g.,
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`sine wave) via low frequency oscillator 310. Controller 303 as illustrated in the embodiment of
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`FIG. 3C may comprise a high frequency (HF) switching portion and low frequency (LF)
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`14
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`

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`ATTY. DKT. 63219-821530 (JBL-0071-PV)
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`switching portion, wherein HF switching portion activates/deactivates switches associated with
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`A DRIVE and B bRIVE of synchronous-buck/buck-synchronous stage 311 (see section (2) of FIG.
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`3A). LF switching portion may activate/deactive switches associated with C DRIVE and D DRIVE
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`of inverter stage 312 (see section (3) of FIG. 3A).
`
`[0056]
`
`Turning now to FIG. 4, an exemplary switch sequence diagram for the
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`embodimentof FIG. 3A is provided for one cycle of controller output (Output) illustrated as a
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`sine wave in the figure. As can be seen, high frequency outputs for switches A and B (Agate,
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`Beate) are Shown together with low frequency outputs for switches C and D (Ceate, Deate), together
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`with an inverted half-cycle voltage output (Ref). In the exemplary embodimentof FIG. 4, the
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`cycle is separated into four sections (1-4) to better describe exemplary operation of the circuit,
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`whichis provided below.
`
`[0057]
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`FIGs. 4A-B are exemplary illustrations of a first section (Section 1) during a
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`positive peak condition (Output) in the circuit, where it can be seen that Agae and Beate provide a
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`high frequency PWM andhigh frequency PWM complementfor the positive peak. During
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`switching time (a), output voltage is at a positive peak condition for the sine wave, where Agate
`
`drive is low, Beate drive is high, Ceate drive is low and Deate drive is high. As switches A and C
`
`are open, the inductor current conducts from the B switch to the D switch via inductor 306 and
`
`load 307 in synchronous current flow as shown in F'IG. 4C. During the (b) switching time, the
`
`outputis still at a positive peak condition and the Agate drive goes high, Beate goes low, Ceate drive
`
`is low and Deate drive is high. As switch A opens and switch B closes, inductor current conducts
`
`from the A switch to the D switch as buck current flow as shown in FIG. 4D.
`
`15
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`

`ATTY. DKT. 63219-821530 (JBL-0071-PV)
`
`[0058]
`
`FIGs. 4E-F are exemplary illustrations of a second section (Section 2) during a
`
`first zero crossing (Output) positive to negative transition in the circuit. During switching time
`
`(a), output voltage is at a zero crossing condition (from positive peak to negative peak) for the
`
`sine wave, where Agate drive is high, Beate drive is low, Cate drive is low and Deate drive is high.
`
`As switches B and C are open, the inductor current instantaneously switches directions and
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`conducts from the A switch to the D switch via inductor 306 and load 307 in buck/synchronous
`
`current flow as shown in FIG. 4G. During the (b) switching time, the output crosses from the
`
`positive peak to the negative peak of the sine wave, causing the Agate drive to go low, Beate to go
`
`high, Cate to go high and Deate gate to go low. As switches B and C open and switches A and D
`
`close, inductor current instantaneously switches directions and conducts from the B switch to the
`
`C switch as synchronous/buckcurrent flow as shownin FIG. 4H.
`
`[0059]
`
`FIGs. 4I-J are exemplary illustrations of a third section (Section 3) during a
`
`negative peak condition (Output) in the circuit, where it can be seen that Agate and Beate provide a
`
`high frequency PWM andhigh frequency PWM complement for the negative peak. During
`
`switching time (a), output voltage is at a negative peak condition for the sine wave, where Agate
`
`drive is high, Bgate drive is low, Cgate drive is high and Dgate drive is low. As switches B and D
`
`are open, the inductor current conducts from the C switch to the A switch in synchronouscurrent
`
`flow as shown in FIG. 4K. During the (b) switching time, the output moves away from the
`
`negative peak condition and the Agate drive goes low, Beate goes high, Cate drive is high and Deate
`
`drive is low. As switch A opens and switch B closes, inductor current conducts from the C
`
`switch to the B switch as buck current flow as shown in FIG. 41..
`
`16
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`

`ATTY. DKT. 63219-821530 (JBL-0071-PV)
`
`[0060]
`
`FIGs. 4M-N are exemplary illustrations of a fourth section (Section 4) during a
`
`second zero crossing (Output) negative to positive transition in the circuit. During switching
`
`time (a), output voltage is approaching a zero crossing condition (from negative peak to positive
`
`peak) for the sine wave, where Agate drive is low, Beate drive is high, Cgate drive is high and Deate
`
`drive is low. As switches A andDare openat zero crossing, the inductor current instantaneously
`
`switches directions from the B switch to the D switch in synchronous/buck current flow as
`
`shown in FIG. 40. During the (b) switching time, the output crosses from the negative peak to
`
`the positive peak of the sine wave, causing the Agate drive to go high, Beate to go low, Ceate to go
`
`low and Deate gate to go high. As switches B and C open and switches A and D close, inductor
`
`current instantaneously switches directions from the A switch to the D switch in
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`buck/synchronouscurrent flow as shownin FIG. 4P.
`
`[0061]
`
`Exemplary simulated gate drive waveforms and current waveforms for
`
`synchronous-buckcircuit portion (2) of inverter 300, comprising switches A and B, are
`
`illustrated in FIGs. 5A-7B. The exemplary simulated waveforms of FIGs. 5A and 5B illustrate
`
`switching gate drive waveforms and current waveforms during a positive peak condition,
`
`discussed above in connection with FIGs. 4A-D. As can be seen from the simulated current
`
`drive waveform of FIG. 5B, switch A, operating as a buck switch, goes low as switch B,
`
`operating as a synchronous switch, goes high during PWM switching. In the simulated current
`
`waveform of FIG. 5B, it can be seen that when switch A is open, current conducts from the B
`
`switch (to the D switch) as discussed above in connection with FIG. 4C. As switch A opens and
`
`switch B closes current conducts from the A switch (to the D switch) as discussed above in
`
`connection with FIGs. 4C-D.
`
`17
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`

`ATTY. DKT. 63219-821530 (JBL-0071-PV)
`
`[0062]
`
`The exemplary simulated waveforms of FIGs. 6A and 6B illustrate switching gate
`
`drive waveforms and current waveforms duringa first zero crossing condition (i.e., from positive
`
`to negative peak), discussed above in connection with FIGs. 4E-H. As can be seen from the
`
`simulated current drive waveform of FIG. 6B, switch A operates as a buck switch before the zero
`
`crossing, and switch B operates as a buck switch after the zero crossing. As switch B opens,
`
`current instantaneously switches directions and conducts from the A switch (to the D switch).
`
`After the zero crossing (from the positive peak to the negative peak), switch B opens and switch
`
`A closes causing current to instantaneously switch directions and conducts from the B switch (to
`
`the C switch) as discussed above in connection with FIGs. G-H.
`
`[0063]
`
`The exemplary simulated waveforms of FIGs. 7A and 7B illustrate switching gate
`
`drive waveforms and current waveforms during a negative peak condition, discussed above in
`
`connection with FIGs. 4I-L. As can be seen from the simulated current drive waveform of FIG.
`
`7B, as switch B opens, and opcrating as a buck switch, current flows to the A switch (from the C
`
`switch) as a synchronous switch as discussed above in connection with FIG. 4K. As switch A
`
`opens and switch B closes, current conducts to the B switch (from the C switch) as buck current
`
`flow as discussed above in connection with FIG. 4L.
`
`[0064]
`
`The exemplary simulated waveforms of FIGs. 8A and 8Billustrate switching gate
`
`drive waveforms and current waveforms during a second zero crossing condition (1.e., from
`
`negative to positive peak), discussed above in connection with FIGs. 4M-P. As can be seen from
`
`the simulated current drive waveform of FIG. 8B, switch A operates as a synchronous switch
`
`with a large duty cycle, and switch B operates as a buck switch with a very small duty cycle
`
`before the zero crossing. After the zero crossing, A operates as a buck switch with a very small
`
`18
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`

`ATTY. DKT. 63219-821530 (JBL-0071-PV)
`
`duty cycle and switch B operates as a synchronous switch with a large duty cycle. Thus, switch
`
`A opensat zero crossing, current instantaneously switches directions from the B switch (to the D
`
`switch) in synchronous/buck current flow as discussed above in connection with FIG. 40. As
`
`the output crosses from the negalive peak to the positive peak of the sine wave, switch B opens
`
`and switch A closes, causing current to instantaneously switch directions from the A switch (to
`
`the D switch) in buck/synchronouscurrent flow as discusse