CLOCK SIGNAL GENERATOR
`
`Inventors:
`
`Yuyu Chang
`John Leete
`Hooman Darab1
`Yiannis Kokolakis
`Qiang Li
`
`BACKGROUNDOF THE INVENTION
`
`Field of the Invention
`
`[0001]
`
`The invention is generally related to systems for generating clock signals.
`
`Background Art
`
`[0002}
`
`Some computing devices, such as mobile computing devices, may havea limited
`
`battery power supply. Computing devices include butare not limited to, mobile phones,
`
`laptops, wristwatches, MP3playersetc.
`
`[0003]
`
`Methods and systems are needed to conserve battery power in such computing
`
`devices.
`
`BRIEF DESCRIPTION OF THE DRAWINGS/FIGURES
`
`[0004]
`
`The
`accompanying drawings, which are
`included to provide
`a
`further
`understanding of the invention and are incorporated in and constitute a part of this
`specification, illustrate embodiments of the invention and together with the description
`serve to explain the principles of the invention.
`In the drawings:
`
`[0005]
`
`1 illustrates an example system to generate a low-power clock signal or a
`FIG.
`low-noise clock signal according to an embodimentofthe invention.
`
`[0006]
`
`FIG. 2 illustrates an example bandgap voltage reference generator according to an
`embodimentof the invention.
`
`[0007]
`
`FIG. 3 illustrates an example system to generate a low-power clock signal or a
`low-noise clock signal according to an embodimentofthe invention.
`
`[0008]
`[0009]
`
`FIG.4 illustrates an example limiter according to an embodimentof the invention.
`FIG. 5 illustrates an example system to generate a low-powerclock signal or a
`low-noise clock signal according to an embodimentofthe invention.
`
`

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`-2-
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`[001 0}
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`FIG.6 illustrates an example flow chart of a method to generate a low-poweror a
`
`low-noise clock signal according to an embodimentof the invention.
`
`[0011]
`
`FIG.7 illustrates an example flow chart of a method to generate a low-poweror a
`
`low-noise clock signal according to an embodimentofthe invention.
`
`[0012]
`
`FIG.8 illustrates an example flow chart of a method to generate a low-poweror a
`
`low-noise clock signal according to an embodimentofthe invention.
`
`[0013]
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`FIG. 9 is a block diagram of an exemplary computer system on which the present
`
`invention can be implemented.
`
`[0014]
`
`The present invention will now be described with reference to the accompanying
`drawings.
`In the drawings,like reference numbers may indicate identical or functionally
`similar elements.
`
`DETAILED DESCRIPTION OF THE INVENTION
`
`[0015]
`
`Certain circuits in a computing device, such as radio frequency (RF) circuits,
`
`phase locked loops (PLLs) and resistive-capacitive (RC) calibration circuits typically
`require a low-noise clock signal. On the other hand, certain circuits such as MP3players,
`video players and non-RF circuits may not require a low-noise clock and can function
`
`with a clock signal that has a lower power level and possibly a higher noise level. For
`
`example, in an "airplane mode" or "sleep mode" of a computing device, such as a cell
`
`phone, RF circuitry such as a cellular integrated circuit (IC) may be powered down, while
`other circuits, such as the non-RF circuits of an MP3 player or a video game, maystill be
`functional. Battery power may be unnecessarily wasted by using a high-power/low-noise
`clock signal for such non-RF circuits. Embodiments of the invention presented herein
`fulfill the long felt need to conserve battery power whencircuits requiring a low-noise
`clock signal are inactive, but other less noise-sensitive circuits are still active.
`
`[0016]
`
`The inventors have identified bandgap voltage reference generators and limiter
`circuits of a clock signal generator as consuming the most amount of powerin portable
`power supplies. Battery power can be conserved by using a low-power bandgap voltage
`reference generator and a low-power
`limiter
`in low-power mode.
`Accordingly,
`embodiments of the invention presented herein may determine when a deviceis in low-
`
`power modeoris using low-power applications and switch to one or both of a low-power
`bandgap voltage reference generator and a low-powerlimiter to conserve power. "Low-
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`-3-
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`power" mode is defined herein as an environment where circuits that do not require a
`
`low-noise clock input, such as non-radio frequency circuits, are active and circuits that do
`
`require a low-noise clock input, such as radio frequency circuits, are not active.
`
`Furthermore, embodiments of the invention presented herein may determine whether a
`
`circuit requires a low-noise clock and switch to one or both of a low-noise bandgap
`
`voltage reference generator and a low-noise limiter. "Low-noise" mode is defined herein
`
`as an environment where circuits that require a low-noise clock input, such as radio
`
`frequency circuits, are active and circuits that do not require a low-noise clock input, such
`
`as non radio frequency circuits, are not active.
`
`It is to be noted that high power is
`
`typically required to generate a low-noise clock signal.
`
`[0017]
`
`FIG.1 illustrates an example system 100 to generate a low-powerclock signal or
`
`a low-noise clock signal according to an embodimentofthe invention.
`
`{0018}
`
`Circuit 100 includes a low-noise bandgap voltage reference generator 104, a low-
`
`power bandgap voltage reference generator 106, a switch 110, control unit 112, a low-
`
`dropout voltage regulator (LDO), crystal oscillator 124, tuning capacitors 126a-b, crystal
`
`128,
`
`limiter 130 and buffer 136.
`
`In an alternate embodiment switch 110 may be
`
`substituted with a mux. System 100 may be on a semiconductor chip 102.
`
`It is to be
`
`appreciated that someorall of the components of system 100 may be on oroff chip 102.
`
`For example, crystal 128 is off chip 102 but may be on chip 102 in analternate
`
`embodiment. Control unit 112 is on chip 102 in the present embodiment but may be off
`
`chip 102 in another embodiment.
`
`[0019]
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`Low-noise bandgap voltage reference generator 104 may generate a low-noise
`
`voltage reference signal 105. Low-power bandgap voltage reference generator 106 may
`
`generate a low-power voltage reference 107. An example circuit for a bandgap voltage
`
`reference generator according to an embodimentof the invention is described in further
`
`detail with reference to FIG. 2 below. Switch 110 mayselect between one of the low-
`
`noise bandgap voltage reference 105 or the low-power bandgap voltage reference 107
`
`based on control signal 114 that may be generated by control unit 112. Switch 110
`
`couples the selected voltage reference to voltage reference input 109 of low-dropout
`
`voltage regulator 108. Low-dropout voltage regulator 108 may provide a constant
`
`voltage output 122 to crystal oscillator 124. Crystal oscillator 124 may generate a clock
`
`signal 132 based on an output of crystal 128. The frequency of clock signal 132 may be
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`-4-
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`tuned by using oneor both of tuning capacitors 126a-b. Clock signal 132 may serve as an
`
`input to limiter circuit 130. Limiter circuit 130 voltage limits clock signal 132 to generate
`
`clock signal, 134 which is buffered by buffer 136 to generate an output clock signal 138.
`
`[0020]
`
`Control signal 114 may be used to switch voltage reference input 109 of low-
`
`dropout regulator 108 to the low-noise bandgap voltage reference 105 for circuits that
`
`require a low-noise and/or high-powerclock signal, such as radio frequency (RF) circuits.
`
`Control signal 114 may also used to switch the voltage reference input 109 of LDO 108 to
`
`the low-power bandgap voltage reference 107 for circuits that do not require a low-noise
`
`or high-power clock such as non-RF circuits. Selecting the low-noise bandgap voltage
`
`reference 105 from low-noise bandgap voltage generator 104 causes output clock signal
`
`138 to be a low-noise output clock signal, but requires more battery power(i.e. low-noise
`
`mode) . Selecting the low-power bandgap voltage reference 107 from low-power bandgap
`
`voltage reference 106 causes output clock signal 138 to be a low-power output clock
`
`signal, and results in power and battery savings compared to the low-noise mode.
`
`[0021]
`
`In an embodiment, control unit 112 may also generate control signal 116 to
`
`power-down the low-noise bandgap voltage reference generator 104 and control signal
`
`120 to power-up low-power bandgap voltage reference generator 106 (if it is inactive),
`
`upon switching the voltage reference input 109 of low-dropout regulator 108 to the low-
`
`power bandgap voltage reference 107 (i.e. low-power mode). Alternatively, control unit
`
`112 may generate control signal 120 to power-down low-power bandgap voltage
`
`reference generator 106 and control signal 116 to power-up low-noise bandgap voltage
`
`reference generator 104 (ifit is inactive) upon switching the voltage reference input 109
`
`of the low-dropout regulator 108 to the low-noise bandgap voltage reference 104 (i.e.
`
`low-noise mode).
`
`[0022]
`
`FIG,2 illustrates an example bandgap voltage reference generator 200 according
`
`to an embodimentof the invention.
`
`[0023]
`
`Bandgap voltage reference generator 200 includes PNP (p-type emitter/collector
`
`and n-type base) transistors 208 and 210, p-FETs(p-typefield effect transistors) 202 and
`
`204 and n-FETs (n-typefield effect transistors) 230. Bandgap voltage reference 200 also
`includes a comparator 206 and an emitter resistance 212.
`It is to be appreciated that the
`type oftransistors usedi.e. p-type or n-type is a design choice and maybearbitrary.
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`[0024]
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`In an embodiment, power-up/down signal 232 may beused to turn transistor 230
`
`on/off and thereby power-up or power-down bandgap voltage reference generator 200.
`
`In
`
`an example, signal 232 may be one of signals 116 or 120 that are used to power-up or
`
`power-down bandgap voltage reference generator 200.
`
`[0025]
`
`A noise factor of bandgap voltage reference generator 200 may be based on
`
`bandgap noise current 1, 220 and flicker noise voltage V, of transistors 208 and 210.
`
`Methods to reduce bandgap noise current i, 220 and flicker noise voltage V, for low-
`
`[0026]
`
`[0027]
`
`[0028]
`
`[0029]
`
`[0030]
`
`[0031]
`
`[0032]
`
`[0033]
`
`[0034]
`
`[0035]
`
`[0036]
`
`[0037]
`
`[0038]
`
`[0039]
`
`noise mode of operation are described below.
`
`Flicker noise voltage V,, may be given by equation 1 below:
`Vv. -_N_1
`- equation 1
`Ci, WLS
`
`In equation 1 above, N is a process dependent constant;
`
`C,,
`
`is the gate-oxide capacitance per unit area;
`
`W is the width ofthe transistor;
`
`Lis the length ofthe transistor; and
`
`fis the frequency of operation.
`
`The area ofa transistor is based on W and L. A larger value of W andL results in
`
`a reduced flicker noise voltage V,. By increasing W and/or L and thereby the area of a
`
`transistor, flicker noise voltage V, can be reduced.
`
`Bandgap noise current i, 220 is given by equation 2 below:
`
`“4KTR _ 4KTR
`= Kl 7B eS Ely
`
`gm
`
`gm
`
`- equation 2
`
`In equation 2 above, K is the ratio of the area oftransistor 210 to transistor 208;
`
`T is the temperature ofthe transistor;
`
`Ris the emitter resistance 212; and
`
`gm is a transconductancefactorofa transistor.
`
`A smaller value of resistance R 212 results in a reduced bandgap noise currenti,
`220. Therefore, in low-noise mode bandgap noise current in 220 can be reduced by
`decreasing resistance R 212.
`
`[0040]
`
`In an embodiment, low-noise bandgap voltage reference generator 104 and low-
`power bandgap voltage reference generator 106 may havesimilar circuits as bandgap
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`-6-
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`voltage reference 200 but have differing values of emitter resistance R and differing area
`
`(W and L values) of transistors. For example, in an embodiment, low-noise bandgap
`
`voltage reference generator 104 may have a smaller value for emitter resistance 212 than
`
`a low-power bandgap voltage reference generator 106. The smaller value of resistance
`
`212 decreases noise in an output of low-noise bandgap voltage reference generator 104 by
`
`reducing bandgap noise current i, 220. In contrast, the larger value for emitter resistance
`
`212 in low-power bandgap voltage reference generator 106 generates a low-power output
`
`voltage reference 107 but mayalso increase noise in the output voltage reference 107 by
`
`increasing bandgap noise current i, 220.
`
`[0041]
`
`In a further embodiment, in addition to, or in the alternative of, differing values of
`resistance 212, low-noise bandgap voltage generator 104 and low-power bandgap voltage
`regulator 106 maydiffer in the area of transistors, for example area of transistors 210 and
`
`208. For example, transistors in a low-noise bandgap voltage generator 104 may have a
`larger area (W and L) thantransistors in low-power bandgap voltage generator 106. As
`described above, a larger area of transistors may result in reducedflicker noise voltage
`Vn, but requires larger current and thus more power(i.e. low-noise mode).
`In contrast,
`
`the smaller area of transistors in low-power bandgap voltage reference generator 106,
`requires less bias current and therefore less power(i.e. low-power mode), but may also
`increase noise in the output voltage reference 107 due to increased flicker noise voltage
`Vie
`
`[0042]
`
`FIG.3 illustrates an example system 300 to generate a low-powerclock signal or
`a low-noise clock signal according to an embodiment of the invention. Circuit 300
`
`includes a bandgap voltage reference generator 302, a low-dropoutvoltage regulator 108,
`a crystal oscillator 124, tuning capacitors 126a-b, crystal 128, a low-powerlimiter 304, a
`low-noise limiter 306, buffers 308a-b, mux 310 and control unit 312. In an alternate
`
`It is to be appreciated thatpart
`embodiment, mux 310 may besubstituted with a switch.
`or all of system 300 may be implemented on or off chip 102. For example, circuit 300
`may be implemented on chip 102. Control unit 312 may be located off chip 102 or on
`chip 102.
`
`[0043]
`
`Bandgap voltage reference generator 302 provides a voltage reference signal 303
`to low-dropout voltage regulator 108. Low-dropout voltage regulator 108 may provide a
`constant voltage signal 122 to crystal oscillator 124. Crystal oscillator 124 may provide a
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`clock signal 132 to low-powerlimiter 304 and low-noise limiter 306. Low-powerlimiter
`
`304 may limit clock signal 132 to generate low-power clock signal output 318. Low-
`
`noise limiter 306 may limit clock signal 132 to generate low-noise clock signal 320. An
`
`example limiter circuit is described below with reference to FIG. 4. Buffers 308a and
`
`308b buffer the low-powerclock signal 318 and low-noise clock signal 320 respectively
`
`to generate low-power output clock signal 322 and low-noise output clock signal 324.
`
`Mux 310 selects one of low-power output clock signal 322 and low-noise output clock
`signal 324 to be output clock signal 326 based on control signal 314 that may be
`
`generated by control unit 312. For example, control signal 314 may be usedto select
`
`low-power output clock signal 322 for circuits that may be able to function with a low-
`
`power, and possibly higher noise, clock signal such as non-RF circuits (i.e. low-power
`mode). Alternatively, control signal 314 may be used to select low-noise output clock
`signal 324 for circuits that may require a low-noise clock signal such as RF circuits (i.e.
`
`low-noise mode).
`
`[0044]
`
`In an embodiment, control unit 312 may generate a first control signal 316a to
`power-down low-noise limiter 306 and a control signal 316b to power-up low-power
`limiter 304 (if it is inactive) if control signal 314 selects low-power output clock signal
`322 for low-power mode of operation. Control unit 312 mayalso generate control signal
`316b to power-down low-powerlimiter 304 and control signal 316a to power-up low-
`noise limiter 316a (if it is inactive) if control signal 314 selects low-noise output clock
`signal 324 for low-noise modeofoperation.
`
`[0045]
`
`[0046]
`
`FIG. 4 illustrates an example limiter 400 according to an embodiment of the
`invention. Limiter 400 may include resistors 406 and 408. Limiter 400 mayalso include
`p-FETs (p-type field effect transistors) 402 and 404 and n-FETs(n-type field effect
`transistors) 410, 412, 414 and 440.
`It is to be appreciated that the type oftransistor used,
`1.€. a p-type or a n-typetransistor, is a design choice and mayvary.
`inputs 420a-b and
`Limiter 400 may be a differential
`limiter with differential
`differential outputs 416a-b.
`In an example, limiter 400 may be used to convert an analog
`sine wave clock signal input 132 from crystal oscillator 124 into a digital square wave
`clock output.
`
`[0047]
`
`in faster
`Using a large bias current for transistors in limiter 400 may result
`switching times and thereby better noise performance. Limiting a clock signal, for
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`example clock signal 132, using a low bias current may result in a low-power output
`
`clock signal.
`
`In an example, strength of a bias current may be based on the size of
`
`transistor 404 and transistor 414. For example, larger transistor sizes for transistor 404
`
`and 414 may lead to larger bias currents,
`
`faster switching time and lower noise.
`
`Furthermore, larger transistor sizes may also result in reduced flicker noise as described
`above with reference to equation 1. For low-power applications a bias current for
`transistors may be reduced resulting in a low-power output. Bias current may be reduced
`
`by reducing the size of one or moretransistors, for example transistors 404 and 414, in
`
`limiter 400. In an embodiment, power-up/down signal 442 may be used to turn transistor
`
`440 on/off and thereby power-up or power-downlimiter 400.
`
`In an example, signal 442
`
`may be oneofsignals 316a or 316b.
`
`It is noted that the transistor size/powerrelationship
`
`described above applies to the band-gap voltage reference generator in FIG. 2 as well.
`
`[0048]
`
`In an embodiment,
`
`low-noise limiter 306 may employ a large bias current
`
`resulting in faster switching time for its transistors and lower output noise. Limiting a
`
`clock signal, for example clock signal 132, using a high bias current mayresult in a high-
`
`poweroutput clock signal.
`
`In an embodiment, a large bias current may be obtained in
`
`limiter 306 by increasing the size of transistors 404 and 414. Thelarge transistor sizes
`
`may also result in reduced flicker noise.
`
`[0049]
`
`In an embodiment, low-power limiter 304 may reduce power consumption by
`
`reducing bias current for transistors in limiter 400. Bias current may be reduced by
`
`reducing the size of transistors 404 and 414. The reduced transistor size may result in
`
`reduced bias current and lower power consumption but may also result in increased
`
`flicker noise.
`
`[0050]
`
`FIG. 5 illustrates an example system 500 to generate a low-powerclock signal or
`
`a low-noise clock signal according to an embodimentof the invention.
`
`[0051]
`
`System 500 includes low-noise bandgap voltage reference generator 104,
`
`low-
`
`power bandgap voltage reference generator 106, control unit 112, low-dropout voltage
`
`regulator 108, crystal oscillator 124, tuning capacitors 126a-b, crystal 128, low-power
`
`limiter 304, low-noise limiter 306, buffers 308a-b, mux 310 and control unit 312.
`
`It is to
`
`be appreciated that someorall of components of system 500 may be implemented on or
`
`off chip 102.
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`-9-
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`[0052]
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`In an embodiment, control unit 112 may initiate (based on internal or external
`
`input e.g. user input/selection) low-power mode and generate control signal 114 that may
`
`cause switch 110 to switch voltage reference input 109 to low-power bandgap voltage
`
`reference signal 107.
`
`In an embodiment, control unit 112 may also generate control
`
`signal 116 to power-down low-noise bandgap voltage generator 104 and control signal
`
`120 to power-up low-power bandgap voltage reference 106 in the event that low-power
`
`bandgap voltage reference generator 106 was powered-down. Further, in low-power
`
`mode, control unit 312 may generate control signal 314 that may cause mux 310 to select
`
`low-poweroutput clock signal 322 as output clock signal 326.
`
`In an embodiment, upon
`
`determining low-power mode, control unit 312 may generate control signal 316a to
`
`power-down low-noise limiter 306 and control signal 316b to power-up low-power
`
`limiter 304 in the event that low-powerlimiter 304 was powered-down.
`
`[0053]
`
`In an embodiment, contro] unit 112 may initiate low-noise mode and generate
`
`control signal 114 that may cause switch 110 to switch voltage reference input 109 to
`
`low-noise bandgap voltage reference 105.
`
`In low-noise mode, control unit 112 mayalso
`
`generate signal 120 to power-down low-power bandgap voltage reference 106 and may
`
`also generate contro] signal 116 to power-up low-noise bandgap voltage reference 104 in
`
`the event that low-noise bandgap voltage reference 104 was powered-down. In low-noise
`
`mode, control unit 312 may generate control signal 314 that causes mux 310 to select
`
`low-noise output clock signal 324 to be output clock signal 326. Upon determining low-
`
`noise mode, control unit 312 may also generate control signal 316b to power-down low-
`
`powerlimiter 304 and control signal 316a to power-up low-noise limiter 306 in the event
`
`that low-noise limiter 306 is powered-down.
`
`[0054]
`
`It is to be appreciated that control unit 112 and control unit 312 may be on chip
`
`In an embodiment, control unit 112 and control unit 312 may be a
`102 or off chip 102.
`combined into a single control unit that may generate control signals 114, 116, 120, 314,
`
`316a and 316b in addition to determining low-power mode or low-noise mode.
`
`In an
`
`embodiment, control unit 112 and contro] unit 312 may determine low-power mode or
`
`high power mode upon receiving input from, for example, a user that selects low-power
`
`mode (such as silent mode or airplane mode) on a computing device (such as a cell
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`phone).
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`-10-
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`[0055]
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`FIG.6 illustrates an example flow chart 600 illustrating steps to generate a low-
`
`poweror a low-noise clock signal according to an embodimentof the invention. Flow
`
`chart 600 will be described with continued reference to the example operating
`
`environment depicted in FIGs. 1-5. However, flow chart 600 is not limited to theses
`
`embodiments. Note that some steps shown in flow chart 600 do not necessarily have to
`
`occur in the order shown.
`
`[0056]
`
`In step 602, it is determined whether a low-power clock or a low-noise clock is
`
`_
`
`required.
`
`If it is determined that a clock is required for low-power mode ofoperation,
`
`then control proceeds to step 604. Ifit is determined that a clock is required for low-noise
`
`mode of operation, then control proceeds to step 606. For example, contro] unit 112 may
`
`determine whether a low-powerclock or a low-noise clock is required.
`
`[0057]
`
`In step 604, a voltage reference input is switched to a low-power bandgap voltage
`
`reference. For example, control unit 112 may generate signal 114 that causes switch 110
`
`to switch voltage reference input 109 of low-dropout voltage regulator 108 to low-power
`
`bandgap voltage reference 107.
`
`In the event that low-power bandgap voltage reference
`
`generator 106 is powered-down,control unit 120 mayalso generate signal 120 to power-
`
`up low-powerbandgap voltage reference generator 106.
`
`[0053]
`
`In step 608, the low-noise bandgap voltage reference generator is powered down.
`
`For example, control unit 112 may generate a control signal 116 to power-down low-
`
`noise bandgap voltage reference generator 104.
`
`[0059]
`
`In step 606, a voltage reference input is switched to a low-noise bandgap voltage
`reference. For example, control unit 112 may generate signal 114 that causes switch 110
`
`to switch the voltage reference input 109 to low-noise bandgap voltage reference 105.
`In
`the event that low-noise bandgap voltage reference 104 is inactive or powered-down
`control unit 112 may provide signal 116 to activate low-noise bandgap voltage reference
`
`generator 104.
`
`[0060]
`
`In step 610, the low-power bandgap voltage reference is powered down. For
`example, in the event that low-power bandgap voltage reference 106 is active, control
`
`[0061]
`
`unit 112 generates signal 120 to power-down low-power bandgap voltage reference 106.
`In step 612, a constant voltage output is provided by the low-dropout voltage
`regulatorto a crystal oscillator. For example, low dropout voltage regulator 108 provides
`
`a constant voltage output 122 to crystal oscillator circuit 124.
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`-11-
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`[0062]
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`In step 614, the crystal oscillator generates a clock signal that may be limited by a
`limiter circuit and buffered to generate an output clock signal. For example, crystal
`oscillator 124 may generate an clock signal 132 which is limited by limiter 130 to
`
`generate limited clock signal 134 that is buffered by buffer 136 to generate output clock
`
`signal 138.
`
`[0063]
`
`FIG. 7 illustrates an example flow chart 700 illustrating steps performed to
`
`generate a low-power clock signal or a low-noise clock signal according to an
`embodimentof the invention. Flow chart 700 will be described with continued reference
`
`to the example operating environment depicted in FIGs. 1-5. However, flow chart 700 is
`not limited to these embodiments. Note that some of the steps shown in flow chart 700
`
`do not necessarily have to occur in the order shown.
`
`[0064]
`
`In step 702, it is determined whether a low-powerclock or a low-noise clock is
`
`[0065]
`
`[0066]
`
`[0067]
`
`[0068]
`
`[0069}
`
`required. For example, control unit 312 determines whether a low-powerclock or a low-
`noise clock is required.
`If a low-power clock is required, then control proceeds to step
`704. Ifa low-noise clock is required, then control proceedsto step 706.
`In step 704, a low-power output clock is selected. For example, control unit 312
`
`selects low-powerclock 322 by providing signal 314 to mux 310.
`
`In the event that low-
`
`powerlimiter 304 is inactive, contro] unit 312 may provide control signal 316b to power-
`up low-powerlimiter 304.
`
`In step 708, a low-noise limiter is powered down. For example, control unit 312
`generates control signal 316a to power down low-noise limiter 306.
`In step 706, a low-noise output clock signal is selected. For example, control unit
`312 provides signal 314 to mux 310 to select low-noise clock signal 324.
`In the event
`that low-noise limiter 306 is inactive, control unit 312 may also provide control signal
`316a to activate or power-up low-noise limiter 306.
`
`In step 710, the low-powerlimiter is powered down. For example, control unit
`312 provides control signal 316b to power down the low-powerlimiter 304.
`FIG. 8 illustrates an example flow chart 800 illustrating steps performed to
`provide a low-power or a low-noise clock signal according to an embodiment of the
`invention. Flow chart 800 will be described with continued reference to the example
`operating environment depicted in FIGs. 1-5. However, flow chart 800 is not limited to
`
`these embodiments. Note that some of the steps shown in flow chart 800 do not
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`necessarily have to occur
`
`in the order
`
`shown, and one or more could occur
`
`simultaneously.
`
`[0070]
`
`In step 802, it is determined whether a low-powerclock or a low-noise clock is
`
`required, For example, control unit 112 and/or control unit 312 may determine whether a
`
`low-power clock or a low-noise clock is required.
`
`If it is determined that a low-power
`
`clock is required, then control proceeds to step 804. If it is determined that a low-noise
`
`clock is required, then contro] proceedsto step 806.
`
`[0071]
`
`In step 804, a voltage reference input of a low-dropout voltage regulator is
`
`switched to a low-power bandgap voltage reference. For example, control unit 112
`
`provides control signal 114 to switch 110 to switch voltage reference input 109 of low
`
`dropout voltage regulator 108 to low-power voltage reference 107.
`
`In the event that low-
`
`powerbandgap voltage reference generator 106 is inactive or powered-down,control unit
`
`112 may provide signal 120 to power-up low-powerbandgap voltage regulator 106.
`
`[0072]
`
`In step 808, the low-noise bandgap voltage reference generator is powered down.
`
`For example, control unit 112 may provide control signal 116 to power down low-noise
`
`bandgap voltage reference generator 104.
`
`[0073]
`
`In step 812, a constant voltage output is provided, using the low-dropout voltage
`regulator, to a crystal oscillator which generates a clock signal that is provided to a low-
`
`powerlimiter. The low-powerlimiter limits the clock signal to generate a limited clock
`signal that is buffered to generate a low-power output clock signal. For example, low-
`dropout voltage regulator 108 provides a constant voltage 122 to crystal oscillator 124
`
`that generates clock signal 132 that is limited by low-power limiter 304 to generate low-
`
`powerclock signal 318, which is buffered by buffer 308a to generate low-power output
`clock signal 322.
`In the event that low-power limiter 304 is inactive, control unit 312
`
`mayalso generate control signal 316b to activate low-powerlimiter 304.
`
`[0074]
`
`In step 816, a low-power output clock signal is selected. For example, control
`unit 312 provides a control signal 314 to mux 310 that selects low-power output clock
`signal 322.
`
`[0075]
`
`In step 820, the low-noise limiter is deactivated or powered down. For example,
`control unit 312 generates control signal 316a to power-down low-noise limiter 306.
`
`[0076]
`
`In step 806, a voltage reference input of a low dropout voltage regulator is
`switched to a low-noise bandgap voltage reference.
`For example, control unit 112
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`generates control signal 114 that causes switch 110 to switch voltage reference 109 of
`
`low-dropout voltage regulator 108 to low-noise bandgap voltage reference 105.
`
`In the
`
`event that low-noise bandgap voltage reference generator 104 is inactive, control unit 112
`
`may generate control signal 116 to activate low-noise bandgap voltage reference
`
`generator 104.
`
`[0077]
`
`In step 810, the low-power bandgap voltage reference generator is powered down.
`
`For example, contro] unit 112 generates control signal 120 to power down low-power
`
`bandgap voltage reference generator 106.
`
`[0078]
`
`In step 814, a constant voltage is provided by the low-dropout voltage regulator to
`
`crystal oscillator which generates a clock signal input that is limited by a low-noise
`
`limiter to generate a low-noise clock signal. Low-noise clock signal 320 may be buffered
`
`by buffer 308b to generate low-noise output clock signal 324. For example, low-dropout
`
`voltage regulator 108 generates a constant voltage reference 122 that is provided to
`
`crystal oscillator 124 that generates an input clock signal 132 that is limited by low-noise
`
`limiter 306 to generate low-noise clock signal 320. Low-noise clock signal 320 is
`buffered by buffer 308b to generate low-noise output clock signal 324.
`In the event that
`
`low-noise limiter 306 is inactive, control unit 312 may generate control signal 316 to
`
`powerup low-noise limiter 306.
`
`[0079]
`
`In step 818, low-noise output clock signal is selected. For example, control unit
`
`312 generates control signal 314 that causes mux 310 to select low-noise output clock
`
`324.
`
`[0080]
`
`In step 822, the low-powerlimiter is powered down. For example, control unit
`
`312 generates control signal 316b to power-down low-powerlimiter 304.
`
`[0081]
`
`The present invention, or portions thereof, can be implemented in hardware,
`
`firmware, software, and/or combinations thereof.
`
`[0082]
`
`The following description of a general purpose computer system is provided for
`completeness.
`The present
`invention can be implemented in hardware, or as a
`combination of software and hardware. Consequently, the invention may be implemented
`in the environment of a computer system or other processing system. An example of such
`a computer system 900 is shown in FIG. 9. The computer system 900 includes one or
`
`more processors, such as processor 904. Processor 904 can be a special purpose or a
`general purpose digital
`signal processor.
`The processor 904 is connected to a
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`communication infrastructure 906 (for example, a bus or network), Various software
`implementations are described in terms of this exemplary computer system. After
`
`reading this description, it will become apparent to a person skilled in the relevant art how
`to implement the invention using other computer systems and/or computerarchitectures.
`
`[0083]
`
`Computer system 900 also includes a main memory 905, preferably random
`access memory (RAM), and mayalso include a secondary memory 901. The secondary
`memory 901 may include, for example, a hard disk drive 912, and/or a removable storage
`drive 914, representing a floppy d