DISPLAY DEVICE
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`CROSS-REFERENCE TO RELATED APPLICATION
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`[0001] This application claims priority to and benefits of Korean Patent Application No.
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`10-2022-0052199 under 35 U.S.C. § 119, filed on April 27, 2022, in the Korean Intellectual
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`Property Office (KIPO), the entire disclosure of which is incorporated herein by reference.
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`BACKGROUND
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`1. Technical Field
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`[0002] Embodiments of the disclosure relate to a display device.
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`2. Description of the Related Art
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`[0003] A display device may include a display region in which an imageis displayed, and a
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`non-display region in which an imageis not displayed and surrounding the display region. A
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`pixel structure configured to emit light and wires configured to transmit an electrical signal to
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`the pixel structure may be disposed in the display region.
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`Some of the wires may extend
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`from the display region to the non-display region so as to be disposed in the non-display
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`region and electrically connected to a driving member configured to provide the electrical
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`signal.
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`[0004] As an area occupied by someofthe wires in the non-display region increases, an area
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`of a bezel of the display device may be increased.
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`In addition, some of the wires disposed in
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`the non-display region may be damaged by moisture, a gas, andthelike.
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`SUMMARY
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`[0005] One object of the disclosure is to provide a display device including a bezel having a
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`relatively small area.
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`[0006] Another object of the disclosure is to provide a display device capable of preventing
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`a wire from being damaged.
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`[0007] However, objects of the disclosure are not limited to the above-described objects, and
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`may be variously expanded without departing from the idea and scope of the disclosure.
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`[0008]
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`In order to achieve the above objects of the disclosure, according embodiments ofthe
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`disclosure, a display device includes a display region; a first wire region extending in a
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`direction from a side of the display region; a second wire region extending in the direction
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`from the first wire region; a peripheral region surrounding the display region, the first wire
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`region, and the second wire region; a pixel structure disposed on a substrate in the display
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`region; a first wire part disposed on the substrate in the first wire region, and includingfirst
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`wires electrically connected to the pixel structure; an inorganic insulating layer covering the
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`first wire part; a second wire part disposed on the inorganic insulating layer in the second wire
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`region, and including second wires electrically contacting the first wires through first
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`through-holes formed through the inorganic insulating layer and arranged along a boundary
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`between the first wire region and the second wire region, respectively; an organic insulating
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`layer covering the second wire part; and a protective layer disposed on the organic insulating
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`layer, and at least partially overlapping the first through-holes in a plan view.
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`[0009] According to an embodiment, the display device may further include a sealing region
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`defined by a sealing opening that penetrates the organic insulating layer, and surrounding the
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`display region.
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`[0010] According to an embodiment, the second wire region may be spaced apart from the
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`sealing region in a plan view, and a portion of the first wire region may overlap a portion of
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`the sealing region in a plan view.
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`[0011] According to an embodiment,
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`the protective layer may cover a portion of a top
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`surface of the inorganic insulating layer exposed by the sealing opening in a region where the
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`portion of the first wire region overlaps the portion of the sealing region in a plan view.
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`[0012] According to an embodiment,
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`the protective layer may further cover the sealing
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`opening and the entire top surface of the inorganic insulating layer exposed by the sealing
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`opening in the region where the portion of the first wire region overlaps the portion of the
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`sealing region in a plan view.
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`[0013] According to an embodiment,
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`the display device may further include a sealing
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`member disposed within the sealing opening; and a cover member supported by the sealing
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`member.
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`[0014] According to an embodiment, the pixel structure may include a semiconductor layer
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`disposed on the substrate; a gate electrode disposed on the semiconductor layer and at least
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`partially overlapping a portion of the semiconductor layer in a plan view, the gate electrode
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`and the first wire part including a same material; the inorganic insulating layer covering the
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`gate electrode; a source-drain electrode disposed on the inorganic insulating layer and
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`electrically contacting another portion of the semiconductor layer, the source-drain electrode
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`and the second wire including a same material; the organic insulating layer covering the
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`source-drain electrode; and a pixel electrode layer disposed on the organic insulating layer
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`and electrically contacting the source-drain electrode,
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`the pixel electrode layer and the
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`protective layer including a same material.
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`[0015] According to an embodiment, the first wire part may include a material havingafirst
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`resistivity, and the second wire part may include a material having a secondresistivity that is
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`lowerthan the first resistivity.
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`[0016] According to an embodiment, the display device may further include a first power
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`supply electrode layer disposed on the substrate and adjacentto the side of the display region,
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`and receiving a first power supply voltage; and a second power supply electrode layer
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`disposed on the substrate in the peripheral region, and receiving a second power supply
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`voltage.
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`[0017] According to an embodiment,
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`the first power supply electrode layer and the
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`protective layer may include a same material.
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`[0018] According to an embodiment,
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`the first power supply electrode layer may be
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`electrically insulated from the protective layer.
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`[0019] According to an embodiment, the protective layer may be electrically connected to
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`the second powersupply electrode layer.
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`[0020]
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`In order to achieve the above objects of the disclosure, according embodiments of the
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`disclosure, a display device includes a display region,a first wire region extending from a side
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`of the display region, a second wire region extending from the first wire region, and a
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`peripheral region surrounding the display region, the first wire region, and the second wire
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`region, and including a pad region in which pad electrodes are disposed; a pixel structure
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`disposed on a substrate in the display region; a first wire part disposed on the substrate in the
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`first wire region, and including first wires electrically connected to the pixel structure; an
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`inorganic insulating layer covering the first wire part; a second wire part disposed on the
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`inorganic insulating layer in the second wire region, and including second wires electrically
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`contacting the first wires through first through-holes formed through the inorganic insulating
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`layer and arranged along a boundary betweenthefirst wire region and the second wire region,
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`respectively; an organic insulating layer covering the second wire part; and a first power
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`supply electrode layer disposed on the organic insulating layer, electrically connected to at
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`least one of the pad electrodes, and at least partially overlapping the first through-hole in a
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`plan view.
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`[0021] According to an embodiment, the display device may further include a sealing region
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`defined by a sealing opening that penetrates the organic insulating layer, and surrounding the
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`display region.
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`[0022] According to an embodiment, the second wire region may be spaced apart from the
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`sealing region in a plan view, and a portion of the first wire region may overlap a portion of
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`the sealing region in a plan view.
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`[0023] According to an embodiment, the first power supply electrode layer may cover the
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`sealing opening and an entire top surface of the inorganic insulating layer exposed by the
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`sealing opening in a region where the portion of the first wire region overlaps the portion of
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`the sealing region in a plan view.
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`[0024] According to an embodiment,
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`the display device may further include: a sealing
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`member disposed within the sealing opening; and a cover member supported by the sealing
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`member.
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`[0025] According to an embodiment, the pixel structure may include a semiconductor layer
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`disposed on the substrate; a gate electrode disposed on the semiconductor layer and at least
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`partially overlapping one portion of the semiconductor layer in a plan view, the gate electrode
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`and the first wire part including a same material; the inorganic insulating layer covering the
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`gate electrode; a source-drain electrode disposed on the inorganic insulating layer and
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`electrically contacting another portion of the semiconductor layer, the source-drain electrode
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`and the second wire part including a same material; the organic insulating layer covering the
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`source-drain electrode; and a pixel electrode layer disposed on the organic insulating layer
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`and electrically contacting the source-drain electrode, the pixel electrode layer and thefirst
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`powersupply electrode layer including a same material.
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`[0026] According to an embodiment, the first wire part may include a material havingafirst
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`resistivity, and the second wire part may include a material having a secondresistivity that is
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`lowerthanthe first resistivity.
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`[0027] According to an embodiment, the display device may further include a second power
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`supply electrode layer disposed on the substrate in the peripheral region. The first power
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`supply electrode layer may receive a first power supply voltage, and the second power supply
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`electrode layer may receive a second powersupply voltage.
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`[0028] According to the embodiments of the disclosure, the display device may include a
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`first wire part including first wires disposed on a substrate in a first wire region; an inorganic
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`insulating layer covering the first wire part; second wires disposed on the inorganic insulating
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`layer in a second wire region, and electrically contacting the first wires through first
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`through-holes formed through the inorganic insulating layer and arranged along a boundary
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`betweenthe first wire region and the second wire region, respectively.
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`Since the first wires
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`makeelectrical contact with the second wires, wire widths of the first wires and the second
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`wires can be relatively reduced, so that an area of a bezel of the display device can be
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`relatively reduced.
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`[0029] According to the embodiments of the disclosure, the display device may include a
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`second wire part, and a protective layer at least partially overlapping the first through-hole, so
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`that the protective layer can prevent the first wire part and the second wire part, which are
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`adjacentto the first through-hole, from being damaged.
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`[0030] According to the embodiments of the disclosure, the display device may include a
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`second wire part, and a first power supply electrode layer at least partially overlapping the
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`first through-hole, so that the first power supply electrode layer can preventthe first wire unit
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`and the second wire part, which are adjacentto the first through-hole, from being damaged.
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`[0031] However, effects of the disclosure are not limited to the above-described effects, and
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`may be variously expanded without departing from the idea and scopeofthe disclosure.
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`BRIEF DESCRIPTION OF THE DRAWINGS
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`[0032] FIG.
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`1
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`is a schematic plan view illustrating a display device according to an
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`embodimentof the disclosure.
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`[0033] FIG. 2 is a schematic sectional view illustrating a pixel structure included in the
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`display device of FIG.1.
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`[0034] FIG. 3 is a schematic enlarged plan viewillustrating a region A of FIG.1.
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`[0035] FIG. 4 is a schematic sectional view taken alongline I-I' of FIG.3.
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`[0036] FIG. 5 is a schematic plan view illustrating a display device according to another
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`embodimentof the disclosure.
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`[0037] FIG. 6 is a schematic enlarged plan view showing region B ofFIG.5.
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`[0038] FIG. 7 is a schematic sectional view taken alongline II-II' of FIG. 6.
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`[0039] FIG.8 is a schematic plan view illustrating a display device according tostill another
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`embodimentofthe disclosure.
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`[0040] FIG.9 is a schematic enlarged plan view illustrating a region C of FIG. 8.
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`[0041] FIG. 10 is a sectional view taken along line IJJ-I' of FIG. 9.
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`DETAILED DESCRIPTION OF THE EMBODIMENTS
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`[0042] Hereinafter, a display device according to embodiments of the disclosure will be
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`described in more detail with reference to the accompanying drawings. The sameor similar
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`reference numerals will be used for the same components in the accompanying drawings.
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`[0043] Spatially relative terms, such as "beneath," "below,"
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`"under," "lower,"
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`"on," "above,"
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`"upper,"
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`"over," "higher,"
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`"side" (e.g., as in "sidewall"), and the like, may be used herein for
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`descriptive purposes, and, thereby, to describe one elements relationship to another element(s)
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`as illustrated in the drawings.
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`Spatially relative terms are intended to encompass different
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`orientations of an apparatus in use, operation, and/or manufacture in addition to the
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`orientation depicted in the drawings. For example, if the apparatus in the drawingsis turned
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`over, elements described as "below" or "beneath" other elements or features would then be
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`oriented "above" the other elements or features. Thus, the term "below" can encompassboth
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`an orientation of above and below. Furthermore, the apparatus may be otherwise oriented
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`(e.g.,
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`rotated 90 degrees or at other orientations), and, as such,
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`the spatially relative
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`descriptors used herein should be interpreted accordingly.
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`[0044] When an element, such as a layer, is referred to as being "on,"
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`"connected to," or
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`"coupled to" another element or layer, it may be directly on, connected to, or coupled to the
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`other elementor layer or intervening elements or layers may be present. When, however, an
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`element or layer is referred to as being "directly on," "directly connected to," or "directly
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`coupled to" another elementor layer, there are no intervening elements or layers present.
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`To
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`this end, the term "connected" may refer to physical, electrical, and/or fluid connection, with
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`or without intervening elements.
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`[0045]
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`Ifa first object "overlaps" a second object, at least part of the first object may face at
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`least part of the second object in a direction or view.
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`[0046] The term "and/or" includes all combinations of one or more of which associated
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`configurations may define. For example, "A and/or B" may be understood to mean "A, B, or
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`A and B."
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`[0047] For the purposes of this disclosure, the phrase "at least one of A and B" may be
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`construed as A only, B only, or any combination of Aand B. Also, "at least one of X, Y, and
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`Z" and "at least one selected from the group consisting of X, Y, and Z" may be construed as X
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`only, Y only, Z only, or any combination of two or more of X, Y, and Z.
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`[0048] Unless otherwise defined or implied herein, all
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`terms (including technical and
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`scientific terms) used herein have the same meaning as commonly understood by those skilled
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`in the art to which this disclosure pertains.
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`It will be further understood that terms, such as
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`those defined in commonly used dictionaries, should be interpreted as having a meaning that
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`is consistent with their meaning in the context of the relevant art and the disclosure, and
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`should not be interpreted in an ideal or excessively formal sense unless clearly so defined
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`herein.
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`[0049] FIG.
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`1
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`is a schematic plan view illustrating a display device according to an
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`embodimentof the disclosure.
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`[0050] Referring to FIG. 1, according to an embodimentof the disclosure, a display device
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`DDa mayinclude a substrate SUB, a pixel structure PX, and a protective layer PLa. The
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`substrate SUB (and/or the display device DDa) may include a display region DA, a wire
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`region LA, and a peripheral region PA. The peripheral region PA mayinclude a pad region
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`PDA.
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`[0051] The pixel structure PX and wireselectrically connected to the pixel structure PX may
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`be disposed in the display region DA. According to an embodiment, the wires may include a
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`data line DL,a first power supply voltage line PL1, and a scan line SL.
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`[0052] The pixel structure PX may receive an electrical signal
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`to emit light having a
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`luminance corresponding to an intensity of the electrical signal. Each of the data line DL,
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`the first power supply voltage line PL1, and the scan line SL maytransmit the electrical signal
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`to the pixel structure PX.
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`For example, the data line DL maytransmit a data signal to the
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`pixel structure PX, the scan line SL may transmit a scan signal to the pixel structure PX, and
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`the first power supply voltage line PL1 may transmit a first power supply voltage to the pixel
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`structure PX.
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`[0053] Although FIG. 1 illustrates one pixel structure PX, one data line DL, onefirst power
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`supply voltage line PL1, and one scan line SL for convenience of description, multiple pixel
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`structures, and multiple data lines, multiple first power supply voltage lines, and multiple scan
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`lines, which are electrically connected to the pixel structures, may be disposed in the display
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`region DA.
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`[0054] The pad region PDA maybe located on a lower portion of the substrate SUB.
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`Pad
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`electrodes may be disposed in the pad region PDA. Although not shown in FIG. 1, the pad
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`electrodes maybeelectrically coupled (or electrically connected) to a flexible circuit film and
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`the like.
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`[0055]
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`In some embodiments, the pad region PDA mayincludea first pad region PDA1 in
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`which first pad electrodes are disposed and a second pad region PDA2 in which second pad
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`electrodes are disposed. An area of each ofthe first pad electrodes may be greater than an
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`area of each of the second pad electrodes in a plan view, and a numberof the second pad
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`electrodes may be greater than a number of the first pad electrodes. However,
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`the
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`embodimentsare not limited thereto.
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`[0056] The wire region LA mayextendin the first direction DR1 fromaside of the display
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`region DA. The wire region LA maybedefined as a region in which the wires disposed in
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`the display region DA extend so asto be disposed outside the display region DA,or a region
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`in which wires electrically contacting the wires disposed in the display region DA are
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`disposed outside the display region DA.
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`[0057] According to an embodiment, the wire region LA mayinclude a first wire region
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`LAI, a second wire region LA2, and a third wire region LA3.
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`[0058] The first wire region LA1 mayextendin the first direction DR1 from the side of the
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`display region DA. Wires (e.g., CLa of FIG. 3) may be disposed in the first wire region
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`LAI. According to an embodiment, the wires disposed in the first wire region LA1 may
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`electrically contact the data line DL. As another example, according to another embodiment,
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`the wires disposed in the first wire region LAI maybe an extension part in which the data line
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`DLdisposed in the display region DA extends outside the display region DA.
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`[0059] The second wire region LA2 may extendin thefirst direction DR1 from thefirst wire
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`region LAl. Wires (e.g., CLb of FIG. 3) may be disposed in the second wire region LA2,
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`and the wires disposed in the second wire region LA2 mayelectrically contact the wires
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`disposed in the first wire region LAI and a driving chip DC disposed in the peripheral region
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`PA.
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`[0060] The third wire region LA3 may extend from the driving chip DC inthe first direction
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`DR1. Wires may be disposed in the third wire region LA3, and the wires disposed in the
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`third wire region LA3 mayelectrically contact the driving chip DC and the second pad
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`electrodes disposed in the second pad region PDA2.
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`[0061] The peripheral region PA may surround the display region DA and the wire region
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`LA. Driving members configured to drive the display device DDa may be disposed in the
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`peripheral region PA.
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`For example, a first power supply electrode layer ELVDD, a second
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`power supply electrode layer ELVSS, a gate driving member GDYV,and the driving chip DC
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`may be disposedin the peripheral region PA.
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`[0062] Thefirst power supply electrode layer ELVDD may be adjacent to the side of the
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`display region DA. The first power supply electrode layer ELVDD may beelectrically
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`connected to the first power supply voltage line PL1, and may provide the first power supply
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`voltage to the first power supply voltage line PL1. According to an embodiment, the first
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`power supply electrode layer ELVDD maybeelectrically connected to some ofthe first pad
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`electrodes disposedin the first pad region PDA1 througha third connection line CL3.
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`[0063] The second powersupply electrode layer ELVSS may be disposed at a periphery of
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`the display region DA except for the side of the display region DA. The second power
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`supply electrode layer ELVSS may beelectrically connected to the pixel structure PX, and
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`may provide a second power supply voltage to the pixel structure PX. According to an
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`embodiment, the second powersupply electrode layer ELVSS may beelectrically connected
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`to some of the first pad electrodes disposed in the first pad region PDA1 throughafirst
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`connection line CL1.
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`[0064] The gate driving member GDV maybe adjacent to at least one side of the display
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`region DA. The gate driving member GDV maybeelectrically connected to the scan line
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`SL and may provide the scan signal to the scan line SL. According to an embodiment, the
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`gate driving member GDV maybeelectrically connected to some ofthe first pad electrodes
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`disposedin the first pad region PDA1 through a second connection line CL2.
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`[0065] The driving chip DC may bedisposed betweenthe first power supply electrode layer
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`ELVDDandthe second pad region PDA2. According to an embodiment, the driving chip
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`DC may be omitted. The wire region LA mayincludeonly thefirst wire region LAI and the
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`second wire region LA2, the second wire region LA2 may extend from the first wire region
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`LAI to the second pad region PDA2, and the wires disposed in the second wire region LA2
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`mayelectrically contact the wires disposed in the first wire region LA1 and the second pad
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`electrodes disposed in the second pad region PDA2.
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`[0066] A sealing region SA surroundingthe display region DA maybelocated at a periphery
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`of the display region DA.
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`Thesealing region SA will be described in detail below with
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`reference to FIG. 2.
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`[0067] A portion of the protective layer PLa may overlap a boundary between the first wire
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`region LAI and the second wire region LA2. According to an embodiment, another portion
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`of the protective layer PLa may partially overlap a region in which the sealing region SA
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`overlaps the first wire region LA1.
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`[0068] The protective layer PLa may beelectrically insulated (or electrically disconnected)
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`from the wires disposed in the first wire region LA1 and the wires disposed in the second wire
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`region LA2.
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`In detail, the protective layer PLa may be disposed on the wires disposed in the
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`first wire region LAI and the wires disposed in the second wire region LA2, and at least one
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`insulating layer may be disposed between the protective layer PLa and the wires disposed in
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`the first wire region LA1 and between the protective layer PLa and the wires disposed in the
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`second wire region LA2.
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`[0069]
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`In some embodiments, the protective layer PLa maybe electrically connected to the
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`second power supply electrode layer ELVSS, and the protective layer PLa may not be
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`electrically coupled to the wires disposed in the first wire region LA1 and the wires disposed
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`in the second wire region LA2. For example, the protective layer PLa may beelectrically
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`connected to the first connection line CL1 by a floating line FLa.
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`[0070] According to an embodiment, the protective layer PLa and the first power supply
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`electrode layer ELVDD mayinclude a same material, and may be disposed on a samelayer.
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`The protective layer PLa may be electrically insulated from the first power supply electrode
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`layer ELVDD.
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`Theprotective layer PLa will be described in detail below with reference to
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`FIGS. 3 and 4.
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`[0071] FIG. 2 is a schematic sectional view illustrating a pixel structure included in the
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`display device of FIG.1.
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`[0072] Referring to FIG. 2, the pixel structure PX mayincludea first insulating layer ILD1,
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`a second insulating layer ILD2, an inorganic insulating layer ILD3, a semiconductor layer
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`ATV,a gate electrode GE, first and second source-drain electrodes SD1 and SD2, an organic
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`insulating layer VIA, a pixel electrode layer PXE, a pixel defining layer PDL,a light emitting
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`material EL, and a commonelectrode layer CE.
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`[0073] The first insulating layer ILD1 may be disposed on the substrate SUB.
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`Thefirst
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`insulating layer ILD1 may include an inorganic insulating material. The first insulating
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`layer ILD1 may block impurities from being introduced from the substrate SUB.
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`[0074] The semiconductor layer ATV may be disposed on the first insulating layer ILD1.
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`The semiconductor layer ATV may include a semiconductor material.
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`For example, the
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`semiconductor
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`layer ATV may include
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`an oxide
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`semiconductor
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`and/or
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`a.
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`silicon
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`semiconductor. However, the embodiments are not limited thereto.
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`[0075] The secondinsulating layer ILD2 may be disposed onthefirst insulating layer ILD1,
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`and may cover the semiconductor layer ATV. The second insulating layer ILD2 mayinclude
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`an inorganic insulating material. The second insulating layer ILD2 mayelectrically insulate
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`the gate electrode GE, which will be described below, from the semiconductor layer ATV.
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`[0076] The gate electrode GE maybe disposed on the second insulating layer ILD2. The
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`gate electrode GE mayoverlap at least a portion of the semiconductor layer ATV. According
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`to an embodiment, the gate electrode GE maybeelectrically connected to the scan line SL
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`described with reference to FIG. 1, and may receive the scan signal from the scan line SL.
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`In case that the scan signal is provided to the gate electrode GE, electrical conductivity of the
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`semiconductor layer ATV mayberelatively increased.
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`[0077] The inorganic insulating layer ILD3 may be disposed on the second insulating layer
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`ILD2, and may cover the gate electrode GE. The inorganic insulating layer ILD3 may
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`electrically insulate the gate electrode GE from the first and second source-drain electrodes
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`SD1 and SD2.
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`[0078] The first and second source-drain electrodes SD1 and SD2 maybe disposed on the
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`inorganic insulating layer ILD3. Each of the first and second source-drain electrodes SD1
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`and SD2 mayelectrically contact the semiconductor layer ATV through a through-hole
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`formed through the second insulating layer ILD2 and the inorganic insulating layer ILD3 to
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`expose a top surface of the semiconductor layer ATV. According to an embodiment,the first
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`source-drain electrode SD1 maybe electrically connected to at least one of the first power
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`supply voltage line PL1 and the data line DL, which are described with reference to FIG. 1.
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`[0079] The organic insulating layer VIA may be disposed on the inorganic insulating layer
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`ILD3, and may coverthe first and second source-drain electrodes SD1 and SD2.
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`[0080] Thepixel electrode layer PXE may be disposed on the organic insulating layer VIA.
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`The pixel electrode layer PXE may include a conductive material. The pixel electrode layer
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`PXE mayelectrically contact the second source-drain electrode SD2 through a through-hole
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`formed through the organic insulating layer VIA to expose a top surface of the second
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`source-drain electrode SD2. According to an embodiment, the pixel electrode layer PXE
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`may be referred to as an anodeelectrode.
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`[0081] The pixel defining layer PDL maybe disposed on the organic insulating layer VIA
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`and the pixel electrode layer PXE.
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`Thepixel defining layer PDL maydefine a pixel opening
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`that exposes at least a portion of the pixel electrode layer PXE.
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`[0082] The light emitting material EL may be disposed on the pixel electrode layer PXE
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`within the pixel opening. According to an embodiment, the light emitting material EL may
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`include an organic light emitting material.
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`[0083] The commonelectrode layer CE may cover the pixel defining layer PDL and the
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`light emitting material EL. The commonelectrode layer CE maybeelectrically connected
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`to the second powersupply electrode layer ELVSS, and may receive the second powersupply
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`voltage from the second power
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`supply electrode layer ELVSS.
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`According to an
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`embodiment, the common electrode layer CE maybereferred to as a cathode electrode.
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`[0084] Referring again to FIGS. 1 and 2, each ofthe first and second insulating layers ILD1
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`and ILD2, the inorganic insulating layer ILD3, and the organic insulating layer VIA may be
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`disposed over the whole substrate SUB.
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`For example, each ofthe first and secondinsulating
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`layers ILD1 and ILD2, the inorganic insulating layer ILD3, and the organic insulating layer
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`VIA may bedisposed on the substrate SUB in the display region DA andthe wire region LA,
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`and may be disposed on the substrate SUB in a portion of the peripheral region PA.
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`[0085] According to an embodiment, the display device DDa mayincludethe sealing region
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`SA. The sealing region SA may be defined as a region in which a sealing opening that opens
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`(or penetrates) the organic insulating layer VIA is formed.
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`[0086]
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`In the sealing region SA, a sealing member (SM of FIG. 4) may be disposed in the
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`sealing opening. A cover member CV supported by the sealing member SM may be
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`disposed on the sealing member (SM of FIG. 4). According to an embodiment, the sealing
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`region SA may surround the display region DA,so that the display region DA may besealed
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`by the sealing member SM and the cover memberCV.
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`[0087] FIG. 3 is a schematic enlarged plan view illustrating region Aof FIG. 1.
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`FIG. 4isa
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`schematic sectional view taken alongline I-I' of FIG. 3.
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`[0088] Referring to FIGS. 1 to 4, a first wire part including first wires CLa may be disposed
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`in the first wire region LAI, and a second wire part including second wires CLb may be
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`disposed in the second wire region LA2.
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`[0089] Thefirst wires CLa and the gate electrode GE may include a same material, and may
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`be disposed on a samelayer.
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`In other words, the first wires CLa may be disposed on the
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`second insulating layer ILD2.
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`[0090] The second wires CLb andthefirst and second source-drain electrodes SD1 and SD2
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`may include a same material, and may be disposed on a same layer.
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`In other words, the
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`second wires CLb maybe disposed on the inorganic insulating layer ILD3.
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`[0091] The second wires CLb may electrically contact the first wires CLa through first
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`through-holes CNT1 formed through the inorganic insulating layer ILD3 to expose portions
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`of the first wires CLa, respectively. The first through-holes CNT1 may be arranged along
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`the boundary betweenthe first wire region LA1 and the second wire region LA2.
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`[0092] According to an embodiment, the first wires CLa may include a material having a
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`first resistivity, and the second wires CLb may include a material having a secondresistivity
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`that
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`is lower than the first resistivity.
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`For example,
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`the first wires CLa may include
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`molybdenum, and the second wires CLb may include aluminum. According to the
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`disclosure, since the first wires CLa electrically contact the second wires CLb, even in case
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`that a wire width of each of the first wires CLa and the second wires CLb becomesrelatively
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`small, a total resistance of the first wires CLa and the second wires CLb electrically
`
`contacting the first wires CLa may becomerelatively low, and thus widths of the first wire
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`region LAI and the second wire region LA2in thefirst direction DR1 may becomerelatively
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`small. As a result, an area of a bezel of the display device DDa may becomerelatively
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`small.
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`[0093] According to an embodiment, the second wire region LA2 may be spaced apart from
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`the sealing region SA in thefirst direction DR1 in a plan view, and a portion of the first wire
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`region LAI mayoverlap a portion of the sealing region SA in a plan view.
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`In case that the
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`sealing region SA overlaps the second wire region LA2 in a plan view, when the sealing
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`opening is formed by removing a portion of the organic insulating layer VIA, the second
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`wires CLb disposed in the second wire region LA2 may be damaged. For example, when
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`the sealing opening is formed by removing the portion of the organic insulating layer VIA by
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`a dry etching scheme,
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`the s