TILED DISPLAY DEVICE
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`CROSS-REFERENCE TO RELATED APPLICATION(S)
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`[0001] The application claims priority to and the benefit of Korean patent
`
`application number 10-2021-0109077 under 35 U.S.C. § 119,
`
`filed on
`
`August 18, 2021, the entire contents of which are incorporated herein by
`
`reference.
`
`1. Technical Field
`
`BACKGROUND
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`[0002] Various embodiments of the disclosure relate to a tiled display
`
`device.
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`2. Description of the Related Art
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`[0003] Recently, as interest in information display is increasing, research
`
`and development of display devices are continuously made.
`
`SUMMARY
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`[0004] Various embodiments of
`
`the disclosure are directed to a tiled
`
`
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`display device, improved and_processin which external visibility is
`
`
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`productivity is improved.
`
`[0005] The disclosure is not
`
`limited to the above-described objects, and
`
`other objects that are not mentioned will be clearly understood by those
`
`skilled in the art from the following description.
`
`[0006] An embodiment of the disclosure mayprovide a tiled display device
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`SD-211120-SKA
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`1
`
`
`
`CROSS-REFERENCE TO RELATED APPLICATION(S)
`
`[0001] The application claims priority to and the benefit of Korean patent
`
`application number 10-2021-0109077 under 35 U.S.C. § 119,
`
`filed on
`
`August 18, 2021, the entire contents of which are incorporated herein by
`
`reference.
`
`1. Technical Field
`
`BACKGROUND
`
`[0002] Various embodiments of the disclosure relate to a tiled display
`
`device.
`
`2. Description of the Related Art
`
`[0003] Recently, as interest in information display is increasing, research
`
`and development of display devices are continuously made.
`
`SUMMARY
`
`[0004] Various embodiments of
`
`the disclosure are directed to a tiled
`
`
`
`display device, improved and_processin which external visibility is
`
`
`
`productivity is improved.
`
`[0005] The disclosure is not
`
`limited to the above-described objects, and
`
`other objects that are not mentioned will be clearly understood by those
`
`skilled in the art from the following description.
`
`[0006] An embodiment of the disclosure mayprovide a tiled display device
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`SD-211120-SKA
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`1
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`
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`including a first panel
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`including a first display element
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`layer; a second
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`panel
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`including a second display element
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`layer; and a shared layer
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`including a color conversion part. The shared layer mayincludeafirst
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`portion and a second portion. The first portion may overlap the first
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`panel in a plan view. The second portion may overlap the second panel in
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`a plan view. The color conversion part may change a wavelength oflight
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`provided from the first panel and the second panel.
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`[0007] In an embodiment, the first panel and the second panel may form a
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`lower panel of the tiled display device, and the shared layer may form an
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`upper panel of the tiled display device.
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`[0008] In an embodiment, the first panel and the second panel may be
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`disposed on a same layer, and the first panel and the second panel may be
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`spaced apart from each other, and a bonding area is disposed between the
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`first panel and the second panel.
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`[0009] In an embodiment, the bonding area may overlap the shared layer
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`in a plan view.
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`[0010] In an embodiment, the color conversion part may include a first
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`color part providing light of a first color, a second color part providing light
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`of a second color, and a third color part providing light of a third color.
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`The first color part, the second color part, and the third color part may
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`overlap the first panel and the second panel in a plan view.
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`[0011] In an embodiment, the tiled display device may further include a
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`first sub-pixel area emitting the light of the first color and overlapping the
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`first color part in a plan view; a second sub-pixel area emitting the light of
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`the second color and overlapping the second color part in a plan view; and
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`a third sub-pixel area emitting the light of the third color and overlapping
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`the third color part in a plan view.
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`[0012] In an embodiment,
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`the shared layer may further include a first
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`SD-211120-SKA
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`color filter overlapping the first sub-pixel area in a plan view, a second
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`color filter overlapping the second sub-pixel area in a plan view, and a
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`third color filter overlapping third sub-pixel area in a plan view.
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`[0013] In an embodiment, wherein the first display element
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`layer may
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`include a first light emitting element, and the second display element layer
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`includes a second light emitting element. The tiled display device may
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`further include an emission area in which the first light emitting element
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`and the second light emitting element are disposed, and the emission area
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`may be defined by components included in the first display element layer
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`and the second display element layer.
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`[0014] In an embodiment, each of the first display element layer and the
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`second display element layer may include a bank protruding in a display
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`direction of the tiled display device, and the bank may have a shape
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`enclosing the emission area.
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`[0015] In an embodiment, the emission area mayinclude a first emission
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`area overlapping the first sub-pixel area in a plan view, a second emission
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`area overlapping the second sub-pixel area in a plan view, and a third
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`emission area overlapping third sub-pixel area in a plan view.
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`[0016] In an embodiment,
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`the first color part may be disposed to be
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`misaligned from the first emission area in a plan view, the second color
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`part may be disposed to be misaligned from the second emission area in a
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`plan view, and the third color part may be disposed to be misaligned from
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`the third emission area in a plan view.
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`[0017] In an embodiment, at least part of the first color part may overlap
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`the first emission area in a plan view, and other part of the first color part
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`may not overlap the first emission area in a plan view.
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`[0018] In an embodiment,
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`the first panel and the first portion of the
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`shared layer may form a first display device, the second panel and the
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`SD-211120-SKA
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`second portion of the shared layer may form a second display device,
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`in
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`the first display device and the second display device, the first sub-pixel
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`area,
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`the second sub-pixel area, and the third sub-pixel area may be
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`adjacent to each other and may be spaced apart from each other bya first
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`separation distance, a first adjacent sub-pixel area of the first display
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`device and a second adjacent sub-pixel area of the second display device
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`may be spaced apart from each other by a second separation distance,
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`the first adjacent sub-pixel area may be an area closest to the second
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`display device, among the first sub-pixel area, the second sub-pixel area,
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`and the third sub-pixel area disposed in the first display device,
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`the
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`second adjacent sub-pixel area may be an area closest to the first display
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`device, among the first sub-pixel area, the second sub-pixel area, and the
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`third sub-pixel area disposed in the second display device, and the first
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`separation distance may be equal to the second separation distance.
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`[0019] In an embodiment, in the first and second display devices, the first
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`emission area, the second emission area, and the third emission area may
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`be adjacent to each other and may be spaced apart from each other by a
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`first emission separation distance, a first adjacent emission area of the
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`first display device and a second adjacent emission area of the second
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`display device may be spaced apart from each other by a second emission
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`separation distance,
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`the first adjacent emission area may be an area
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`closest to the second display device, among the first emission area, the
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`second emission area, and the third emission area disposed in the first
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`display device, the second adjacent emission area may be an area closest
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`to the first display device, among the first emission area,
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`the second
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`emission area, and the third emission area disposed in the second display
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`device, and the first emission separation distance may be different from
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`the second emission separation distance.
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`[0020] In an embodiment, the second emission separation distance may
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`be greater than the second separation distance.
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`[0021] In an embodiment, when viewed from an outside, the light of the
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`first color may be observed in the first sub-pixel area, the light of the
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`second color may be observed in the second sub-pixel area, and the light
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`of the third color may be observed in the third sub-pixel area.
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`[0022] In an embodiment, the first panel and the second panel may be
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`disposed on a same layer, the first panel and the second panel may be
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`spaced apart from each other, a bonding area may be disposed between
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`the first panel and the second panel, and a thickness of the bonding area
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`may be smaller than the second separation distance.
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`[0023] In an embodiment, the first color part may include a first quantum
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`dot converting the light of the third color into the light of the first color,
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`and the second color part may include a second quantum dot converting
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`the light of the third color into the light of the second color.
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`[0024] In an embodiment, each of the first light emitting element and the
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`second light emitting element may emit the light of the third color.
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`[0025] In an embodiment, a color provided by the first adjacent sub-pixel
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`area and a color provided by the second adjacent sub-pixel area may be
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`different from each other.
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`[0026] In an embodiment, each of the first light emitting element and the
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`second light emitting element may be an organic light emitting diode or a
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`light emitting diode having a size in a range of a nanoscale to a microscale.
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`[0027] An embodiment of the disclosure may provide a tiled display device
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`including a first display device including a first substrate, a first display
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`element
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`layer disposed on the first substrate, and a first upper layer
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`disposed on the first display element layer; and a second display device
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`including a second substrate, a second display element layer disposed on
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`the second substrate, and a second upper layer disposed on the second
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`display element layer. The first upper layer and the second upper layer
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`may be integral with each other, and each of the first upper layer and the
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`second upper layer may include a first color part including a first quantum
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`dot and a second color part including a second quantum dot.
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`[0028] An embodiment of the disclosure mayprovide a tiled display device
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`including a first sub-pixel area emitting light of a first color, a second sub-
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`pixel area emitting light of a second color, and a third sub-pixel area
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`emitting light of a third color, the tiled display device including a first panel
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`including a first substrate, and a first display element layer disposed on
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`the first substrate and including a first light emitting element emitting the
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`light of the third color; a second panel including a second substrate, and a
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`second display element
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`layer disposed on the second substrate and
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`including a second light emitting element configured to emit the light of
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`the third color; and a shared layer including a first area overlapping the
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`first panel in a plan view, and a second area overlapping the second panel
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`in a plan view,
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`in a plan view. The first sub-pixel area, the second sub-
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`pixel area, and the third sub-pixel area may be defined by the shared layer.
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`[0029] The disclosure is not limited to the above-described embodiments,
`
`and other embodiments that are not mentioned will be clearly understood
`
`by those skilled in the art from the specification and the accompanying
`
`drawings.
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`BRIEF DESCRIPTION OF THE DRAWINGS
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`[0030] An additional appreciation according to the embodiments of the
`
`disclosure will become more apparent
`
`by describing in detail
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`the
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`embodiments thereof with reference to the accompanying drawings,
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`SD-211120-SKA
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`wherein:
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`[0031] FIG. 1 is a schematic plan view illustrating a tiled display device in
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`accordance with an embodiment of the disclosure.
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`[0032] FIG. 2 is a schematic perspective view illustrating a tiled display
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`device in accordance with an embodiment of the disclosure.
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`[0033] FIG. 3 is a schematic block diagram illustrating a tiled display
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`device in accordance with an embodiment of the disclosure.
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`[0034] FIG. 4 is a schematic diagram of an equivalent circuit illustrating a
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`pixel circuit included in a pixel
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`in accordance with an embodiment of the
`
`disclosure.
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`[0035] FIG. 5 is a schematic plan view illustrating a pixel
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`in accordance
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`with a first embodiment of the disclosure.
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`[0036] FIG. 6 is a schematic cross-sectional view taken along line II-II’ of
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`FIG. 5.
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`[0037] FIG. 7 is a schematic cross-sectional view illustrating a pixel
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`in
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`accordance with a second embodiment of the disclosure.
`
`[0038] FIG. 8 is a schematic cross-sectional view illustrating a pixel
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`including a shared layer, and is a cross-sectional view taken along line I -
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`I' of FIG. 1.
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`[0039] FIGS. 9 to 11 are schematic enlarged viewsillustrating area EA1 of
`
`FIG. 1.
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`DETAILED DESCRIPTION OF THE EMBODIMENTS
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`[0040] Since embodiments described herein are intended to clearly convey
`
`the spirit of the disclosure to those skilled in the art, the disclosure is not
`
`limited to the embodiments.
`
`It should be interpreted that various
`
`changes and modifications may be made in
`
`the disclosure without
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`SD-211120-SKA
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`departing from the spirit and scope thereof.
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`[0041] The terms "about" or "approximately" as used herein is inclusive of
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`the stated value and means within an acceptable range of deviation for
`
`the particular value as determined by one of ordinary skill
`
`in the art,
`
`considering the measurement in question and the error associated with
`
`measurement of
`
`the particular quantity (i.e.,
`
`the limitations of
`
`the
`
`measurement system).
`
`For example, "about" may mean within one or
`
`more standard deviations, or within + 30%, 20%, 10%, 5% of the stated
`
`value.
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`[0042] It will be understood that the terms "contact," "connected to," and
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`"coupled to" may include a physical and/or electrical contact, connection,
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`or coupling, and vice versa.
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`[0043] The phrase "at least one of" is intended to include the meaning of
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`"at least one selected from the group of" for the purpose of its meaning
`
`and interpretation.
`
`For example, "at
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`least one of A and B" may be
`
`understood to mean "A, B, or A and B."
`
`[0044] Unless otherwise defined or implied herein, all
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`terms (including
`
`technical and scientific terms) used herein have the same meaning as
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`commonly understood by thoseskilled in the art to which this disclosure
`
`pertains.
`
`It will be further understood that terms, such as those defined
`
`in commonly used dictionaries, should be interpreted as having a meaning
`
`that is consistent with their meaning in the context of the relevant art and
`
`the disclosure, and should not be interpreted in an ideal or excessively
`
`formal sense unless clearly so defined herein.
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`[0045] The accompanying drawings are for the purpose of easily describing
`
`particular embodiments, and may be exaggerated as necessary to aid in
`
`understanding of
`
`the disclosure.
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`The disclosure is not
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`limited to
`
`embodiments shown in the drawings.
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`SD-211120-SKA
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`[0046] When it is determined that the detailed description of the known art
`
`related to the disclosure may obscure the gist of the disclosure,
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`the
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`detailed description will be omitted.
`
`[0047] Various embodiments of the disclosure relate to a tiled display
`
`device.
`
`Hereinafter,
`
`a
`
`tiled display device in accordance with an
`
`embodiment will be described with reference to the accompanying
`
`drawings.
`
`[0048] FIG. 1 is a schematic plan view illustrating a tiled display device in
`
`accordance with an embodiment.
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`[0049] A tiled display device TDD may be configured to provide visual
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`information to a user. The tiled display device TDD mayprovide (or emit)
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`light in a display direction (e.g., a third direction DR3) of the tiled display
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`device TDD.
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`[0050] The tiled display device TDD may be provided by combining display
`
`devices DD. According to an embodiment, the tiled display device TDD
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`may display a large screen by combining the display devices DD, and thus
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`may be applied to a field requiring a wide display surface such as the
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`surface of an outdoor billboard.
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`[0051] The display devices DD included in the tiled display device TDD
`
`may include first to fourth display devices DD1 to DD4. According to an
`
`embodiment, the tiled display device TDD mayinclude four display devices.
`
`However, the number of display devices forming (or configuring) the tiled
`
`display device TDD is not limited to a specific example. Hereinafter, for
`
`the convenience of description, an embodiment
`
`including four display
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`devices DD1, DD2, DD3, and DD4 will be described.
`
`[0052] The tiled display device TDD mayinclude a pixel PXL, a display area
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`DA, a non-display area NDA, and a bonding area BA.
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`[0053] Light may be output in the display area DA. The pixel PXL may be
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`SD-211120-SKA
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`disposed on the display area DA. The display area DA may be formed on
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`a surface of the tiled display device TDD. However, the disclosure is not
`
`limited thereto. The display area DA may be formed on a side surface
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`and/or a
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`rear surface of
`
`the tiled display device TDD.
`
`Herein, an
`
`embodiment in which the display area DA is formed on a surface of the
`
`tiled display device TDD will be described.
`
`[0054] The pixel PXL may be disposed in the display area DA.
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`The pixel
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`PXL mayinclude a first sub-pixel SPXL1, a second sub-pixel SPXL2, and a
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`third sub-pixel SPXL3. The first to third sub-pixels SPXL1, SPXL2, and
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`SPXL3 may output light of different colors, respectively.
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`For example, the
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`light of a first color may be output from the first sub-pixel SPXL1, the light
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`of a second color may be output from the second sub-pixel SPXL2, and the
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`light of a third color may be output from the third sub-pixel SPXL3.
`
`[0055] Each of the first to third sub-pixels SPXL1, SPXL2, and SPXL3 may
`
`include a light emitting element LD (see FIG. 4).
`
`The light emitting
`
`element LD is configured to emit light.
`
`[0056] Light may not be output in the non-display area NDA. The non-
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`display area NDA is an area other than the display area DA and the
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`bonding area BA, and the pixel PXL may not be disposed on the non-
`
`display area NDA.
`
`[0057] According to an embodiment, the non-display area NDA may have
`
`a shape that encloses a portion of the display area DA. However, the
`
`disclosure is not limited to the above example.
`
`For instance, the non-
`
`display area NDA maybe selectively disposed inside the display area DA.
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`[0058] The bonding area BA may mean an area between first to fourth
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`panels PNL1i to PNL4 (see FIG. 2) included in each of the display devices
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`DD included in the tiled display device TDD. According to an embodiment,
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`at least a portion of the bonding area BA may be disposed between the
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`SD-211120-SKA
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`first panel PNL1 and the second panel PNL2.
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`For instance, the bonding
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`area BA mayinclude a first bonding area disposed between the first panel
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`PNL1 and the second panel PNL2,
`
`a
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`second bonding area disposed
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`between the first panel PNL1 and the third panel PNL3, a third bonding
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`area disposed between the second panel PNL2 and the fourth panel PNL4,
`
`and a fourth bonding area disposed between the third panel PNL3 and the
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`fourth panel PNL4.
`
`[0059] According to an embodiment, the bonding area BA may overlap a
`
`shared layer 100 (see FIG. 2)
`
`in a plan view.
`
`For instance, at least a
`
`portion of the shared layer 100 may be provided in the bonding area BA.
`
`[0060] According to an embodiment,
`
`the tiled display device TDD may
`
`include the shared layer 100 disposed across the first to fourth display
`
`devices DD1 to DD4. The shared layer 100 mayoverlap the first to fourth
`
`panels PNL1 to PNL4 in a plan view. The shared layer 100 may overlap
`
`the bonding area BA in a plan view.
`
`[0061] Hereinafter,
`
`the description of
`
`a
`
`tiled display device TDD in
`
`accordance with an embodiment will be focused on the shared layer 100
`
`with reference to FIGS. 2 and 3.
`
`[0062] FIG. 2 is a schematic perspective view schematically illustrating a
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`tiled display device in accordance with an embodiment.
`
`FIG. 3 is a block
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`diagram illustrating
`
`a
`
`tiled display device
`
`in
`
`accordance with
`
`an
`
`embodiment.
`
`[0063] Referring to FIGS. 2 and 3,
`
`the tiled display device TDD may
`
`include a first panel PNL1, a second panel PNL2, a third panel PNL3, a
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`fourth panel PNL4, and a shared layer 100. Here,
`
`the first
`
`to fourth
`
`panels PNL1 to PNL4 may be provided as a lower structure of the tiled
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`display device TDD, while the shared layer 100 may be provided as an
`
`upper structure.
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`[0064] The first display device DD1 mayinclude the first panel PNL1 and at
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`least a portion of the shared layer 100.
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`For instance, the first display
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`device DD1 mayinclude the first panel PNL1 and a first shared layer (or a
`
`first upper layer). The first shared layer is a portion of the shared layer
`
`100 and may overlap the first panel PNL1. The first panel PNL1 may
`
`overlap a first area (e.g., a first portion) of the shared layer 100 in a plan
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`view.
`
`[0065] The second display device DD2 mayinclude the second panel PNL2
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`and at least a portion of the shared layer 100.
`
`For instance, the second
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`display device DD2 may include the second panel PNL2 and a second
`
`shared layer (or a second upper layer). The second shared layer is a
`
`portion of the shared layer 100 and may overlap the second panel PNL2.
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`The second panel PNL2 may overlap the second area (e.g., a second
`
`portion) of the shared layer 100 in a plan view.
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`[0066] The third display device DD3 mayinclude the third panel PNL3 and
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`at least a portion of the shared layer 100.
`
`For instance, the third display
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`device DD3 mayinclude the third panel PNL3 and a third shared layer (or
`
`a third upper layer). The third shared layer is a portion of the shared
`
`layer 100 and may overlap the third panel PNL3. The third panel PNL3
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`may overlap the third area (e.g., a third portion) of the shared layer 100
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`in a plan view.
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`[0067] The fourth display device DD4 mayinclude the fourth panel PNL4
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`and at least a portion of the shared layer 100.
`
`For instance, the fourth
`
`display device DD4 mayinclude the fourth panel PNL4 and a fourth shared
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`layer (or a fourth upper layer). The fourth shared layer is a portion of the
`
`shared layer 100 and may overlap the fourth panel PNL4. The fourth
`
`panel PNL4 may overlap the fourth area (e.g., a fourth portion) of the
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`shared layer 100 in a plan view.
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`[0068] According to an embodiment, the first to fourth shared layers may
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`be integrated with each other.
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`[0069] The first panel PNL1 may be connected to at least a portion of the
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`shared layer 100.
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`For instance, an upper surface of the first panel PNL1
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`and a lower surface of the shared layer 100 may be connected by an
`
`adhesive member.
`
`The adhesive member may include an adhesive
`
`material, but the disclosure is not limited to a specific example. Likewise,
`
`each of the second to fourth panels PNL2 to PNL4 may be connected to a
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`portion of the shared layer 100.
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`[0070] The first panel PNL1i
`
`is a part of the first display device DD1 and
`
`may refer to a lower panel of the first display device DD1. Similarly, the
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`second to fourth panels PNL2 to PNL4 are parts of the second to fourth
`
`display devices DD2 to DD4, respectively, and may refer to lower panels of
`
`the second to fourth display devices DD2 to DD4.
`
`[0071] According to an embodiment,
`
`the first
`
`to fourth panels PNL1 to
`
`PNL4 may be spaced apart from each other.
`
`For example, as described
`
`above, the first panel PNL1 may be spaced apart from the second panel
`
`PNL2, the third panel PNL3, and the fourth panel PNL4 with the bonding
`
`area BA interposed therebetween. According to an embodiment, adjacent
`
`panels (e.g., the first panel PNL1 and the second panel PNL2) may be
`
`connected in the bonding area BA.
`
`[0072] According to an embodiment,
`
`the first panel PNL1,
`
`the second
`
`panel PNL2,
`
`the third panel PNL3, and the fourth panel PNL4 may be
`
`placed on a same layer.
`
`[0073] The first panel PNL1 may include a first substrate SUB1, a first pixel
`
`circuit part PCL1, and a first display element part DPL1.
`
`The first
`
`substrate SUB1,
`
`the first pixel circuit part PCL1, and the first display
`
`element part DPL1 may be successively stacked in the thickness direction
`
`SD-211120-SKA
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`13
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`
`
`(e.g., the third direction DR3) of the first substrate SUB1. Similarly, the
`
`second to fourth panels PNL2 to PNL4 may include second to fourth
`
`substrates SUB2 to SUB4, second to fourth pixel circuit parts PCL2 to PCL4,
`
`and second to fourth display element parts DPL2 to DPL4, respectively,
`
`which are successively stacked in the third direction DR3.
`
`[0074] The first
`
`to fourth panels PNL1 to PNL4 may emit
`
`light.
`
`For
`
`instance, the first to fourth display element parts DPL1 to DPL4 included in
`
`the first to fourth panels PNL1 to PNL4, respectively, may include light
`
`emitting elements LD configured to emit light.
`
`[0075] For example, the first display element part DPL1 mayinclude a first
`
`light emitting element, the second display element part DPL2 may include
`
`a second light emitting element, the third display element part DPL3 may
`
`include a third light emitting element, and the fourth display element part
`
`DPL4 mayinclude a fourth light emitting element.
`
`[0076] According to an embodiment,
`
`"display element part" may be
`
`referred to as a "display element
`
`layer". For example, the first display
`
`element part DPL1 may bea first display element layer, the second display
`
`element part DPL2 may be a second display element
`
`layer,
`
`the third
`
`display element part DPL3 may be a third display element layer, and the
`
`fourth display element part DPL4 may be a fourth display element layer.
`
`[0077] The first panel PNL1 may overlap the shared layer 100 in a plan
`
`view. According to an embodiment, the first panel PNL1 may overlap a
`
`color conversion part CCL and/or a color filter part CFL included in the
`
`shared layer 100 when viewed in a plan view.
`
`Similarly, each of the
`
`second to fourth panels PNL2 to PNL4 may overlap the shared layer 100 in
`
`a plan view. This will be described below in detail with reference to FIG.
`
`8.
`
`[0078] The first panel PNL1 and the second to fourth panels PNL2 to PNL4
`
`SD-211120-SKA
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`14
`
`
`
`may be formed by different processes.
`
`For instance, the first panel PNL1
`
`may be manufactured by a
`
`separate process and be coupled (or
`
`connected) with the second to fourth panels PNL2 to PNL4.
`
`[0079] The first display device DD1 mayinclude the first panel PNL1 and at
`
`least a portion of the shared layer 100.
`
`For instance, the first display
`
`device DD1 mayinclude the first panel PNL1 and a first shared layer. The
`
`first shared layer is a portion of the shared layer 100 and mayrefer to a
`
`portion overlapping the first panel PNL1.
`
`[0080] Hereinafter, display devices DD included in the tiled display device
`
`TDD in accordance with an embodiment will be described in detail.
`
`However, for the convenience of description, the first display device DD1
`
`among the display devices DD will be described.
`
`According to an
`
`embodiment, the technical features described with reference to the first
`
`display device DD1 may be applied to the second to fourth display devices
`
`DD2 to DD4.
`
`[0081] According to an embodiment, the structure illustrated in FIGS. 4 to
`
`7 may represent the first panel PNL1 of the first display device DD1.
`
`[0082] First, a pixel circuit PXC of the pixel PXL included in the first display
`
`device DD1 according to an embodiment will be described with reference
`
`to FIG. 4.
`
`FIG. 4 is a schematic diagram illustrating an equivalent pixel
`
`circuit included in a pixel in accordance with an embodiment.
`
`[0083] Referring to FIG. 4,
`
`the pixel PXL may include a light emitting
`
`element LD and a pixel circuit PXC.
`
`[0084] The light emitting element LD may be electrically connected
`
`between a first power line VDD and a second power line VSS. A first end
`
`(e.g., a P-type semiconductor) of the light emitting element LD may be
`
`electrically connected to the first power line VDD via a first electrode ELT1
`
`and the pixel
`
`circuit
`
`PXC, while
`
`a
`
`second end (e.g.,
`
`an N-type
`
`SD-211120-SKA
`
`15
`
`
`
`semiconductor) of
`
`the light emitting element LD may be electrically
`
`connected to the second power line VSS via a second electrode ELT2.
`
`[0085] In an embodiment, the light emitting element LD may emit light
`
`having a luminance corresponding to driving current supplied thereto
`
`through the pixel circuit PXC.
`
`[0086] In an embodiment,
`
`the light emitting elements LD may be
`
`electrically connected to each other through various connecting structures
`
`between the first power line VDD and the second power line VSS.
`
`For
`
`instance, the light emitting elements LD may be electrically connected to
`
`each other only in parallel or only in series. As another example, the light
`
`emitting elements LD may be electrically connected in a serial-parallel
`
`mixed structure.
`
`[0087] The first and second power lines VDD and VSS may havedifferent
`
`potentials to allow the light emitting elements LD to emit light. The first
`
`and second power lines VDD and VSS may have a potential difference to
`
`allow light to be emitted during the light emission period of the pixel PXL.
`
`For example, the first power line VDD may be set to a potential higher
`
`than that of the second power line VSS.
`
`[0088] The pixel circuit PXC may electrically connect the first power line
`
`VDD to the light emitting element LD. The pixel circuit PXC may include a
`
`first transistor T1, a second transistor T2, a third transistor T3, and a
`
`storage capacitor Cst.
`
`[0089] According to an embodiment, a first electrode of the first transistor
`
`T1 may be electrically connected to the first power line VDD, while a
`
`second electrode thereof may be electrically connected to a first electrode
`
`(e.g., an anode electrode) of the light emitting element LD.
`
`A gate
`
`electrode of the first transistor T1 may be electrically connected to a first
`
`node Ni. The first transistor T1 may control a current flowing through
`
`SD-211120-SKA
`
`16
`
`
`
`the light emitting element LD in response to a voltage applied thereto
`
`through the first node N1.
`
`[0090] According to an embodiment,
`
`a
`
`first electrode of
`
`the second
`
`transistor T2 may be electrically connected to a data line DL, while a
`
`second electrode thereof may be electrically connected to the first node
`
`Ni.
`
`A gate electrode of the second transistor T2 may be electrically
`
`connected to a scan line SL.
`
`In case that a scan signal is supplied from
`
`the scan line SL, the second transistor T2 may be turned on.
`
`In this case,
`
`a data signal provided from the data line DL may be transmitted to the
`
`first node N1.
`
`[0091] According to an embodiment,a first electrode of the third transistor
`
`T3 may be electrically connected to a sensing line SENL, while a second
`
`electrode thereof may be electrically connected to a second node N2. A
`
`gate electrode of the third transistor T3 may be electrically connected to a
`
`sensing signal line SEL.
`
`In case that the third transistor T3 is turned on
`
`in response to a sensing signal provided from the sensing signal line SEL,
`
`a reference voltage may be provided to the second node N2 through the
`
`sensing line SENL.
`
`[0092] According to an embodiment, the reference voltage may serve to
`
`set or initialize the voltage of the electrode (e.g., a source electrode of the
`
`first transistor T1) of the first transistor T1 electrically connected to the
`
`light emitting element LD to a constant value.
`
`For example, the reference
`
`voltage may be set to be less than or equal to the voltage of the second
`
`power line VSS.
`
`[0093] According to an embodiment, in case that the third transistor T3 is
`
`turned on in response to a sensing signal provided from the sensing signal
`
`line SEL, the sensing current may be transmitted to the sensing line SENL.
`
`[0094] In an embodiment, the sensing current may be used to calculate
`
`SD-211120-SKA
`
`17
`
`
`
`changesin mobility and threshold voltage of the first transistor T1.
`
`[0095] The storage capacitor Cst may be electrically connected between
`
`the first node Ni (or the gate electrode of the first transistor T1) and the
`
`second node N2 (or the second electrode of the first transistor T1). The
`
`storage capacitor Cst may store information about a difference in voltage
`
`between the first node N1 and the second node N2.
`
`[0096] The structure of the pixel circuit PXC is not limited to the structure
`
`illustrated in FIG. 4, and various types of structures may be implemented.
`
`FIG. 4 illustrates the first
`
`to third transistors Ti
`
`to T3 as an N-type
`
`transistor. However, the disclosure is not
`
`limited thereto.
`
`The first to
`
`third transistors T1 to T3 may be formed of the P-type transistor according
`
`to an embodiment.
`
`[0097] Hereinafter,
`
`the structure of
`
`the pixel
`
`PXL according to an
`
`embodiment will be described with reference to FIGS. 5 to 7. Contents
`
`that may overlap the above-described contents will be briefly described or
`
`omitted.
`
`[0098] In an embodiment, the pixel PXL may include the light emitting
`
`element LD.
`
`For example, the light emitting element LD may be a light
`
`emitting diode or an organic light emitting diode (OLED) having a size
`
`from a nanoscale to a microscale.
`
`[0099] First, an embodiment where the light emitting element LD as the
`
`pixel PXL of the first embodiment is a light emitting diode having a size
`
`from a nanoscale to a microscale will be described with reference to FIGS.
`
`5 and 6.
`
`[00100] FIG. 5 is a schematic plan view illustrating a pixel
`
`in accordance
`
`with a first embodiment of the disclosure. The pixel PXL shown in FIG
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