(10) International Publication Number
`
`(12) INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT)
`
`,
`(19) World Intellectual Property Organization a | I
`International Bureau
`
`p
`
`2) VAIO MTUAAA
`
`(43) International Publication Date
`30 July 2009 (30.07.2009)
`
`(51) International Patent Classification:
`HOLL 31/042 (2006.01)
`
`(21) International Application Number:
`PCT/US2009/03 1886
`
`(22) International Filing Date: 23 January 2009 (23.01.2009)
`
`(25) Filing Language:
`
`(26) Publication Language:
`
`English
`
`English
`
`WO 2009/094578 A2
`
`(81) Designated States (unless otherwise indicated, for every
`kind of national protection available): AE, AG, AL, AM,
`AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA,
`CH, CN, CO, CR, CU, CZ, DE, DK, DM,DO,DZ, EC, EE,
`EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU,ID,
`IL, IN,IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK,
`LR, LS, LY, LU, LY, MA, MD, ME, MG, MK, MN, Mw,
`Mx,MY, MZ, NA,NG,NI, NO, NZ, OM,PG,PH,PL, PT,
`RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY. TJ,
`‘TM, ‘IN, TR, TT, 17Z, UA, UG, US, UZ, VC, VN, ZA, 2M,
`ZW.
`
`(30) Priority Data:
`61/023,342
`
`24 January 2008 (24.01.2008)
`
`US
`
`(71) Applicant (for all designated States except US): AP-
`PLIED MATERIALS, INC.
`[US/US]; 3050 Bowers
`Avenue, Santa Clara, CA 95054 (US).
`
`(72) Inventor: BORDEN,Peter; 118 Seville Way, San Mateo,
`CA 94402 (US).
`
`(84) Designated States (unless otherwise indicated, for every
`kind of regional protection available): ARIPO (BW, GH,
`GM, KL, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM,
`ZW), Eurasian (AM, AZ, BY, KG, KZ, MD, RU, TJ, ‘I'M),
`European (AT, BE, BG, CH, CY, CZ, DE, DK,EE, ES, FI,
`FR, GB, GR, IIR, IIU, TE, IS, IT, LT, LU, LV, MC, MK,
`MT, NL, NO, PL, PL, RO, SE, SL SK, TR), OAPI (BE, BJ,
`CE, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN,
`TD, TG).
`
`(74) Agent: DANIELSON, Mark, J.; Pillsbury Winthrop
`Shaw Pittman LLP, P.O. Box 10500, McLean, VA 22102
`(US).
`
`Published:
`
`without international search report and to be republished
`upon receipt ofthat report
`
`(54) Title: IMPROVED HIT SOLAR CELL STRUCTURE
`
`S F
`
`IG. 2A
`
`TCO 222
`
`7 ¥Si(p) 224 (50A)
`__-— a-Si(i) 226 (S0A)
`—— SiO, 228 (12A)
`
`__ Si 206
`
`(57) Abstract: The present invention relates to improved IIIT type or polysilicon emitter solar cells. According to certain aspects,
`the invention includes forming a masking oxidelayer on the front and backofthe cell and then patterning holes in the masking oxide.
`N
`© A HIT cell structure or polysilicon emitter solar cell structure is then formed overthe patterned oxide, creating the cell junction only
`© in the areas where holes have been cut. Benefits of the invention include thatit provides a controlled interface for the IIIT cell
`through insertion of a thin tunnel oxide. Moreover, the tunnel oxide prevents epitaxial growth of amorphoussilicon, allowing it to
`remain amorphousfor the optimum band structure. Still further, it provides a layer to protect the surface from plasma damage during
`
`iS deposition ofthe a-Si layer. Further, it may be used in conjunction with a point contact structure to further increase efficiency.
`
`094578AIMMUNITYATICA
`
`

`

`WO 2009/094578
`
`PCT/US2009/031886
`
`IMPROVED HIT SOLAR CELL STRUCTURE
`
`CROSS-REFERENCE TO RELATED APPLICATIONS
`
`(0001)
`
`The presentapplication claimspriority to U.S. Prov. Appin. No.61/023,342 filed
`
`January 24, 2008,the contents of which are incorporated herein by referencein their entirety.
`
`FIELD OF THE INVENTION
`
`[0002]
`
`The present invention relates to photovoltaic devices, and more particularly to
`
`methods and apparatuses for providing an improved structure of a HIT type or polysilicon emitter
`
`type solar cells.
`
`BACKGROUND
`
`[0003]
`
`HITtype solar cells are high efficiency devices with relatively simple structures.
`
`Sanyo Corporation of Japan has reported lab efficiencies of 21.5% and manufacturingefficiency
`
`in the mid-19% range. Many other groups have worked on this device, although none has shown
`
`as high efficiencies.
`
`[0004]
`
`A typical HIT typesolarcell structure is shown in FIG. 1A and 1B. Thedevice is
`
`symmetric, with the front and backof the n-type substrate 106 both coated with a coating 102
`
`and 110, respectively and metal grid lines 104 and 108, respectively. As shown in the blowup
`
`portion of FIG. 1B,the coating 102 on the front consists of two amorphoussilicon layers, an
`
`intrinsic layer 126 under a p-type layer 124, both about 50 Angstromsthick. On the back,the
`
`amorphoussilicon layer consists of an intrinsic (i) layer under an n-type layer. As further shown
`
`in FIG. 1B,the coating 102 further includesa layer of transparent conductive oxide (TCO) 122.
`
`

`

`WO 2009/094578
`
`PCT/US2009/031886
`
`[0005]
`
`The purpose ofthe thin a-Si layers is to both passivate the surface and to provide a
`
`heterojunction with a wide bandgap windowlayer to improve the open circuit voltage, as shown
`
`in FIG. 1C. Moreparticularly, FIG.
`
`1C illustrates the band structure of such a device. As shown
`
`in FIG. 1C,there is a large potential step at the front surface, creating a junction muchlike a
`
`junction found at the step between p- and n-type dopants. However, because this junction is
`
`formed by depositing a layer of amorphoussilicon, it is very abrupt, and nearly ideal.
`
`[0006]
`
`Despite their benefits, these amorphoussilicon layers also introduce considerable
`
`complexity into the fabrication of the HIT cell. For example, the layers must be formed on a
`
`carefully prepared surface, whose preparation details have not been published. Further, they
`
`must notcrystallize, as can happen when the amorphoussilicon is seeded by the crystal silicon
`
`substrate, as this will eliminate the beneficial passivation and heterojunction effects.
`
`[0007]
`
`Therefore, there is a lingering need for an improvedinterface that is well
`
`controlled and understood and easy to manufacture, and does not seed crystal growth.
`
`SUMMARY
`
`[0008]
`
`The present invention relates to improved HIT type or polysilicon emitter solar
`
`cells. Accordingto certain aspects, the invention includes forming a masking oxide layer on the
`
`front and back ofthe cell and then patterning holes in the masking oxide. A HIT cell structure or
`
`polysilicon emitter solar cell structure is then formed overthe patterned oxide, creating the cell
`
`junction only in the areas where holes have been cut. Benefits of the inventionincludethatit
`
`provides a controlled interface for the HIT cell throughinsertion ofa thin tunneloxide.
`
`Moreover, the tunnel oxide prevents epitaxial growth of amorphoussilicon, allowing it to remain
`
`amorphousfor the optimum bandstructure. Still further, 1t provides a layer to protect the surface
`
`

`

`WO 2009/094578
`
`PCT/US2009/031886
`
`from plasma damage during deposition of the a-Si layer. Further, it may be used in conjunction
`
`with a point contact structure to further increase efficiency.
`
`[0009]
`
`In furtherance of these and otheraspects,a solar cell according to embodiments of
`
`the invention comprises an amorphous semiconductor layer formed over a substrate; and a
`
`dielectric layer interposed between the substrate and the amorphous semiconductorlayer,
`
`wherein the dielectric layer is sufficiently thin so as to support a tunneling current therethrough.
`
`[0010]
`
`In additional furtherance of these and other aspects, a method offabricating a
`
`solar cell according to embodiments of the invention includes forming a dielectric layer on a
`
`substrate, wherein the dielectric layer is sufficiently thin so as to support a tunneling current
`
`therethrough; and forming an amorphous semiconductorlayer formed overthe dielectric layer.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`(0011)
`
`These and other aspects and featuresof the present invention will become
`
`apparent to those ordinarily skilled in the art upon review of the following description of specific
`
`embodiments ofthe invention in conjunction with the accompanying figures, wherein:
`
`[0012]
`
`[0013]
`
`FIGs. 1A to 1C show a conventional HITcell and its bandstructure.
`
`FIGs. 2A and 2B show an examplesolar structure of the present invention andits
`
`bandstructure, respectively.
`
`[0014]
`
`FIG.3 is a diagram illustrating an example process flow to form the structure of
`
`FIG. 2 according to aspects of the invention.
`
`DETAILED DESCRIPTION
`
`(0015]
`
`The present invention will now be described in detail with reference to the
`
`drawings, which are providedasillustrative examples of the invention so as to enable those
`
`

`

`WO 2009/094578
`
`PCT/US2009/031886
`
`skilled in the art to practice the invention. Notably, the figures and examples below are not meant
`
`to limit the scope of the present invention to a single embodiment, but other embodiments are
`
`possible by way of interchange of some orall of the describedorillustrated elements. Moreover,
`
`wherecertain elements of the present invention can bepartially or fully implemented using
`
`known components, only those portions of such known components that are necessary for an
`
`understanding of the present invention will be described, and detailed descriptions of other
`
`portions of such known components will be omitted so as not to obscure the invention. In the
`
`present specification, an embodiment showing a singular component should not be considered
`
`limiting; rather, the invention is intended to encompass other embodiments includinga plurality
`
`of the same component, and vice-versa, unless explicitly stated otherwise herein. Moreover,
`
`applicants do notintend for any term in the specification or claimsto be ascribed an uncommon
`
`or special meaning unless explicitly set forth as such. Further, the present invention
`
`encompassespresent and future known equivalents to the known components referred to herein
`
`by way ofillustration.
`
`[0016]
`
`In general, the present inventors recognize that thin tunnel oxide layers can be
`
`used in solar cells. For example, some MIS cells can be made using aluminum overtunnel
`
`oxides. The present inventors further recognize that tunnel oxides can be used betweenaheavily
`
`doped or insulating layer of polysilicon and a crystal silicon substrate, forming a polysilicon
`
`emitter solar cell. Such a solar cell has a similar band structure to a HIT cell, essentially
`
`replacing the TCO and a-Silayers with polysilicon. However, such cells do not provide the
`
`heterojunction and its benefit of a higher cell voltage due to the higher bandgapof a-Si.
`
`

`

`WO 2009/094578
`
`PCT/US2009/031886
`
`[0017]
`
`An example solar cell structure according to embodimentsof the invention and
`
`the associated band structure is shown in FIGs, 2A and 2B, respectively.
`
`[0013]
`
`As shown in FIG, 2A, which can be part of a front surface of a HIT-type solar cell
`
`similar to that shown in FIG.1, a thin dielectric layer 228 (e.g. tunnel oxide) is provided between
`
`the a-Si layers 224 and 226 and the n-type substrate 206 in a HIT cell. The dielectric layeris
`
`preferably thin, on the order of 8-15A,in order to support a tunneling current between the
`
`substrate and a-Si layers. As will be described in more detail below, layer 228 can be formed
`
`using conventional methods such as rapid thermal oxidation, furnace oxidation, or the Chemox
`
`process (formation in an ozonated H)O, bath). In some cases, the layer maybenitrided or
`formed using other materials such assilicon nitride or silicon oxynitride.
`
`[0019]
`
`As shown in FIG. 2B, added dielectric layer at the interface provides a bandgap
`
`much larger than the bandgap of the semiconductors. Carriers cannot get over the energy barrier,
`
`but tunnel throughif the layer is sufficiently thin (<15A). Note that oxide and nitride will have
`
`different barrier heights, so the layer shown is not meant to represent any one material. The
`
`barrier height for nitride is about 2.5 eV and is symmetric. The barrier height for oxide is
`
`asymmetric (lower for electrons).
`
`[0020]
`
`The benefits provided by dielectric layer 228 are several-fold. For example,it
`
`may be formed using conventional surface cleaning and preparation methods, as are used to make
`
`MOS gates for ICs. Therefore, the surface preparation is well known and understood, and
`
`routinely implemented in high volume manufacturing. Moreover,as it is an amorphouslayer,it
`
`separates the subsequenta-Si layer from the substrate, preventing epitaxial seeding of crystal
`
`

`

`WO 2009/094578
`
`PCT/US2009/031886
`
`growth in the a-Si layer. Further, it provides an intervening layer to protect the crystal silicon
`
`surface from plasma damage during deposition of the a-Silayer.
`
`[0021}
`
`It should be noted that, although benefits of the invention are obtained with a-Si
`
`layers formed overa crystalline silicon substrate, that this is not limiting, and that the invention
`
`can be applied to other types of substrates and thin semiconductor layers. It should be further
`
`noted that many solar cells use heterojunctions. So, for example, the invention could be used
`
`with a thin film solar cell with amorphoussilicon on micro-crystal silicon. It could also be used
`
`on CdTe, CIGS or AlGaAs/GaAscells, all of which use heterojunctions.
`
`{0022}
`
`That said, it should bestill further noted that amorphoussilicon onsilicon is
`
`known to provide excellent passivation properties, nearly eliminating surface recombination.
`
`This is because the high band bendingat the surfacerepels carriers. Accordingly,this is one
`
`advantage of using amorphoussilicon onsilicon.
`
`[0023]
`
`FIG.3 is a diagram illustrating an example processflow used to makethe
`
`structure of FIG. 2A. First, in step $302, the front surface of the n-type substrate is textured.
`
`This may be accomplished using conventional etching, such as isopropyl] alcohol and KOH.
`
`Next in step $304, the surface is provided with a standard MOS clean to remove native oxides,
`
`ionic contamination, and organics.
`
`[0024]
`
`In one embodiment, a rapid thermal oxide processis then used in step $306 to
`
`form a thin tunnel oxide, typically 12A thick, on the front surface. In another embodiment of the
`
`invention, the oxide is formed on both front and back at the same time. Next the a-Si layers are
`
`deposited on the front surface. In one embodiment, the a-Si is formed as a two layer stack on the
`
`front surface, with an intrinsic a-Si, 20-50 A thick formedfirst in step S308, for example by
`
`

`

`WO 2009/094578
`
`PCT/US2009/031886
`
`plasma enhanced chemical vapor deposition (PE-CVD), which is the decompositionofsilane in a
`
`plasma, often with hydrogen present. These processes are well known in theliterature. Boron
`
`may be addedto provide p-type doping, and phosphorous may be addedto provide n-type
`
`doping. Next, a p-type a-Si, 20-50 A thick is formed ontopofthe intrinsic a-Si layer in step
`
`S312, for example by the same PE-CVDprocess. In another embodiment, only a doped p-type
`
`layer is formed on the front surface in step S310, withoutthe i-type layer. The TCO is deposited
`
`in step S314, which may be a quarter wavethick layer of indium tin oxide.
`
`[0025]
`
`The wafer is then flipped over in step $316, and the structure is deposited in the
`
`same manneronthe back side, now using n-type a-Si instead of p-type. As shown, depending on
`
`whetherthe oxide layer has already been formed, processing returns to step $306 or step $308. It
`
`should be further apparent that processing could also return to step $310 if the oxide layer has
`
`already been formed. Finally, contacts are formed in step S318, for example by screen printing
`
`or sputtering.
`
`[0026]
`
`Additionally or alternatively to the process described above, a method to form
`
`point contacts for HIT or polysilicon emitter solar cells, as described in co-pending application
`
`No. _ (AMAT-12964), the contents of which are incorporated herein by reference in their
`
`entirety, may be performed.
`
`[0027]
`
`Althoughthe present invention has been particularly described with reference to
`
`the preferred embodimentsthereof, it should be readily apparentto those of ordinary skill in the
`
`art that changes and modifications in the form and details may be made without departing from
`
`the spirit and scope of the invention.
`
`It is intended that the appended claims encompass such
`
`changes and modifications.
`
`

`

`WO 2009/094578
`
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`
`WHATIS CLAIMEDIS:
`
`1. A solar cell comprising:
`
`an amorphous semiconductor layer formed over a substrate;
`
`a dielectric layer interposed between the substrate and the amorphous semiconductor
`
`layer, wherein the dielectric layer is sufficiently thin so as to support a tunneling current
`
`therethrough.
`
`2. A solar cell according to claim 1, wherein the substrate comprises silicon and the dielectric
`
`layer comprises silicon dioxide.
`
`3. Asolar cell according to claim 1, wherein the substrate comprises silicon and the dielectric
`
`layer comprisesnitrogen.
`
`4. A solar cell according to claim 1, wherein the amorphous semiconductor layer comprises
`
`silicon.
`
`5. A solar cell according to claim 1, wherein the amorphous semiconductor layer comprises a
`
`two-layer stack of an intrinsic amorphoussilicon layer and a doped amorphoussilicon layer.
`
`6. A solar cell according to claim 1, wherein the amorphous semiconductorlayer is formed on a
`
`front surface of the substrate, wherein the solar cell further comprises:
`
`

`

`WO 2009/094578
`
`PCT/US2009/031886
`
`another amorphous semiconductor layer is formed on an opposite back surtace of the
`
`substrate; and
`
`anotherdielectric layer interposed between the substrate and the another amorphous
`
`semiconductor layer, wherein the another dielectric layer is sufficiently thin so as to support a
`
`tunneling current therethrough.
`
`7. A solar cell according to claim 6, wherein both the amorphous semiconductorlayer and the
`
`another amorphous semiconductor layer comprise a two-layer stack of an intrinsic amorphous
`
`silicon layer and a doped amorphoussilicon layer.
`
`8. A methodoffabricating a solar cell, comprising:
`
`forming a dielectric layer on a substrate, wherein the dielectric layer is sufficiently thin so
`
`as to support a tunneling current therethrough; and
`
`forming an amorphous semiconductor layer formed overthe dielectric layer.
`
`9. A method according to claim 8, wherein the step of forming the amorphous semiconductor
`
`layer includes forming a two-layer stack of an intrinsic amorphoussilicon layer and a doped
`
`amorphoussilicon layer.
`
`10. A method according to claim 8, further comprising:
`
`texturing a surface of the substrate before forming the dielectric layer.
`
`

`

`WO 2009/094578
`
`PCT/US2009/031886
`
`11. A method according to claim 8, wherein a rapid thermal oxide process is used to form the
`
`dielectric layer.
`
`12. A method according to claim 9, wherein the intrinsic and doped amorphoussilicon layers are
`
`both about 20-50 A thick.
`
`13. A method accordingto claim 8, further comprising depositing a layer of TCO over the
`
`amorphous semiconductorlayer.
`
`14. A method according to claim 13, wherein the TCO comprises a quarter wavethick layer of
`
`indium tin oxide.
`
`15. A method according to claim 8, wherein the amorphous semiconductor layer is formed on a
`
`front surface of the substrate, wherein the method further comprises:
`
`forming anotherdielectric layer on an opposite back surface of the substrate, wherein the
`
`anotherdielectric layer is sufficiently thin so as to support a tunneling current therethrough, and
`
`forming another amorphous semiconductor layer over the anotherdielectric layer.
`
`10
`
`

`

`WO 2009/094578
`
`PCT/US2009/031886
`
`
`
`FIGLIA
`
`
`
`
`
`
`
`
`
`
`IN /,
`YN \YI
`
`
`
`\—
`
`a-Si(p) 124 (504)
`
`
`
`a-Sid) 126 (504)
`n-Si 106
`
`BIG. 1B
`
`G-SEEip) @-SLA
`
`
`
` c-Siai Ex
`
`Jront
`
`back
`
`FIG ic
`
`1/3
`
`

`

`WO 2009/094578
`
`PCT/US2009/031886
`
`IW/\JwTCO222
`NW)J
`
`U7 #Silp) 224 (50A)
`_— a-Si(i) 226 (50A)
`—— SiO, 228 (12A)
`
`_ Si 206
`
`FIG. 2A
`
`pli}
`
`o@-SiHi{p) o-Si]
`
`
`
`
`
`
`c-Sitni Ey OSH)sit)
`
`Added tunnel
`oxide
`
`
`
`
`Jront
`
`back
`
`FIG. 2B
`
`2/3
`
`

`

`WO 2009/094578
`
`PCT/US2009/031886
`
`
`
`
`Texture front
`surface
`$302
`
`MOS clean
`$304
`
`a-Si(doped)
`$310
`
`
`S316 a-Si(doped)
`
`
`
`
`
`Flip wafer
`
`
`$312
`
`Contacts
`$318
`
`FIG. 3
`
`3/3
`
`