EMISSIVE DISPLAY DEVICE
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`CROSS-REFERENCE TO RELATED APPLICATION(S)
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`[0001] This application claims priority to and benefits of Korean Patent Application
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`No. 10-2021-0156576 under 35 U.S.C. §119, filed on November 15, 2021, in the Korean
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`Intellectual Property Office, the entire contents of which are incorporated herein by
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`reference.
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`1. Technical Field
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`BACKGROUND
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`[0002] The disclosure relates to an emissive display device including light emitting
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`diodes.
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`2. Description of the Related Art
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`[0003] An emissive display device may include light emitting diodes (LEDs)
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`corresponding to pixels, and may display an image by controlling luminance of each
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`of the light emitting diodes. Unlike a non-emissive display devices such as a liquid
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`crystal displays, the emissive display devices may not require a separate light sources,
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`making it possible to reduce their thickness and weight.
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`The emissive display
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`devices have characteristics such as high luminance, high contrast ratio, high color
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`reproduction, high response speed, and thelike, to display a high quality image.
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`[0004] Because of such advantages, the emissive display devices are applied to various
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`electronic devices including mobile devices such as smart phones and_tablets,
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`monitors, televisions, and the like, and have been a focusof interest as display devices
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`for vehicles.
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`[0005] It is to be understoodthat this backgroundof the technologysectionis, in part,
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`intended to provide useful background for understanding the technology. However,
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`this background of the technology section may also include ideas, concepts, or
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`recognitions that were not part of what was knownor appreciated by those skilled in
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`the pertinent art prior to a corresponding effective filing date of the subject matter
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`disclosed herein.
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`SUMMARY
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`[0006] An emissive display device may includea pixel electrode, an emission member,
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`and a commonelectrode constituting a light emitting diode. The emission member
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`may include multiple layers, and at least some of the layers may span over multiple
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`pixels. Accordingly, the electric current supplied to a pixel may leak to a neighboring
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`pixel, and cause the neighboring pixel to unintentionally emit light or increase its
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`luminance.
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`[0007] Embodiments provide an emissive display device that prevents such leakage of
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`light from occurring between neighboring pixels.
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`[0008] An embodiment provides an emissive display device that may include a
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`transistor disposed on a substrate, a first insulating layer disposed on the transistor, a
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`separation line disposed on the first insulating layer, a second insulating layer
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`disposed on the first insulating layer the second insulating layer includingafirst
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`opening overlapping the separation line in a plan view,a first pixel electrode and a
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`second pixel electrode disposed at opposite sides of the separationline, the first pixel
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`electrode and the second pixel electrode disposed on the second insulating layer, a
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`pixel defining layer disposed on the second insulating layer, the pixel defining layer
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`including a second opening overlapping the separation line in a plan view, and an
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`emission member disposed on thefirst pixel electrode, the second pixel electrode, the
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`pixel defining layer, and the separation line, the emission memberbeing separated by
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`the separation line. The emission member may includea first emission unit, a charge
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`generating layer disposed on the first emission unit, and a second emission unit
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`disposed on the charge generating layer.
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`[0009] The charge generating layer may include an n-type charge generating layer and
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`a p-type charge generating layer. The charge generating layer may be separated at
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`opposite sides of the separationline.
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`[0010] The charge generating layer may have a portion disposed on the separationline.
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`[0011] The separation line may include a first conductive layer, a second conductive
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`layer, and a third conductive layer. The first conductive layer, the second conductive
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`layer, and the third conductive layer may be sequentially stacked. The common
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`electrode mayelectrically contact a side surface of the first conductive layer.
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`[0012] The commonelectrode mayelectrically contact a side surface of the second
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`conductive layer.
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`[0013] The separation line may include a first conductive layer, a second conductive
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`layer, and a third conductive layer. The first conductive layer, the second conductive
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`layer, and the third conductive layer may be sequentially stacked. A width of the
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`third conductive layer may be wider than a width of the second conductivelayer.
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`[0014] The third conductive layer may include a transparent conductive oxide layer.
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`[0015] The third conductive layer may includeafirst transparent conductive oxide
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`layer, a metal layer, and a second transparent conductive oxide layer. The first
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`transparent conductive oxide layer, the metal layer, and the second transparent
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`conductive oxide layer may be sequentially stacked.
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`[0016] The third conductive layer, the first pixel electrode, and the second pixel
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`electrode may include a same material and may be formed in a same process.
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`[0017] The emissive display device may further include a connector disposed on the
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`first insulating layer,
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`the connector being an electrode of the transistor, or the
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`connector being electrically connected to the electrode of the transistor.
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`The
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`connector may includea first conductive layer, a second conductive layer, and a third
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`conductive layer. The first conductive layer, the second conductive layer, and the
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`third conductive layer may be sequentially stacked. The first conductive layer of the
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`separation line and the second conductive layer of the separation line, and thefirst
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`conductive layer of the connector and the second conductive layer of the connector
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`may include a same material. The third conductive layer of the separation line and
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`the third conductive layer of the connector may include a different material.
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`[0018] The second conductive layer of the separation line may be thinner than the
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`second conductive layer of the connector.
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`[0019] The pixel defining layer may have an opening overlapping the connector in a
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`plan view.
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`Thefirst pixel electrode may be connected to the connector through the
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`opening of the pixel defining layer.
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`[0020] Each of the first emission unit and the second emission unit may include a hole
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`transport layer, an electron transport layer disposed on the hole transport layer, and a
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`first emission layer overlapping the first pixel electrode in a plan view,the first
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`emission layer disposed between the hole transport layer and the electron transport
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`layer, and a second emission layer overlapping the second pixel electrode in a plan
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`view, the second emission layer disposed between the hole transport layer and the
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`electron transportlayer.
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`[0021] The emissive display device may further include a commonelectrode disposed
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`on the light emitting member. The common electrode may be separated by the
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`separation line.
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`[0022] The separation line may include a first conductive layer, a second conductive
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`layer, and a third conductive layer. The first conductive layer, the second conductive
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`layer, and the third conductive layer may be sequentially stacked. The common
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`electrode mayelectrically contact a side surface of the second conductivelayer.
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`[0023] The commonelectrode may havea portion disposed on the separationline.
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`[0024] An embodiment provides an emissive display device that may include a
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`transistor disposed on a substrate, a first insulating layer disposed on the transistor, a
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`bypass line disposed onthefirst insulating layer, a second insulating layer disposed
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`on the first insulating layer,
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`the second insulating layer including an opening
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`overlapping the bypassline in a plan view,a first pixel electrode and a second pixel
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`electrode disposed at opposite sides of the bypassline,the first pixel electrode and the
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`second pixel electrode disposed on the second insulating layer, a pixel defining layer
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`disposed on the secondinsulating layer, the pixel defining layer including an opening
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`overlapping the bypass line in a plan view; a emission member disposed on thefirst
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`pixel electrode, the secondpixel electrode, the pixel defining layer, and the bypassline,
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`and a commonelectrode disposed on the emission member. The emission member
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`may extendoverthefirst pixel electrode and the second pixel electrode.
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`<A surface of
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`the emission member may contact a surface of the bypassline.
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`[0025] A voltage applied to the commonelectrode may be substantially equal to a
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`voltage applied to the bypassline.
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`[0026] The bypassline may includea first conductive layer, a second conductivelayer,
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`and a third conductive layer.
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`Thefirst conductive layer, the second conductive layer,
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`and the third conductive layer may be sequentially stacked. The third conductive
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`layer may include a transparent conductive oxidelayer.
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`[0027] The emission member may contact the third conductive layer.
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`The third
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`conductive layer, the first pixel electrode, and the second pixel electrode may include
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`a same material, and may be formedin a sameprocess.
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`[0028] According to the embodiments, it is possible to prevent leakage of light from
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`occurring between neighboring pixels, thereby improving display quality of the
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`emissive display device. Further, according to the embodiments, other advantages
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`may be apparent throughoutthe specification.
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`BRIEF DESCRIPTION OF THE DRAWINGS
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`[0029] The above and other aspects and features of the disclosure will become more
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`apparent by describing in detail embodiments thereof with reference to the attached
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`drawings, in which:
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`[0030] FIG. 1 illustrates a schematic perspective view showing an emissive display
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`device according to an embodiment.
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`[0031] FIG.2 illustrates a schematic plan view of pixels disposed in a display area in
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`an emissive display device according to an embodiment.
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`[0032] FIG.3 illustrates a schematic cross-sectional view of an emissive display device
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`taken along line A-A'in FIG. 2 according to an embodiment.
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`[0033] FIG. 4 illustrates a schematic cross-sectional view of an emission memberin an
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`emissive display device according to an embodiment.
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`[0034] FIG. 5 to FIG. 10 illustrate schematic process cross-sectional views showing a
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`manufacturing method of an emissive display device according to an embodiment.
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`[0035] FIG. 11 and FIG. 12 each illustrate a schematic cross-sectional view of an
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`emissive display device taken along line A-A' in FIG. 2 according to an embodiment.
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`[0036] FIG. 13, FIG. 14, and FIG. 15 eachillustrate a schematic cross-sectional view of
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`a pixel area in a display panel according to an embodiment.
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`DETAILED DESCRIPTION OF THE EMBODIMENTS
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`[0037] The disclosure will be described more fully hereinafter with reference to the
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`accompanying drawings, in which embodiments are shown. This disclosure may,
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`however, be embodied in different forms and should not be construed as limited to
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`the embodiments set forth herein. Rather, these embodiments are provided so that
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`this disclosure will be thorough and complete, and will fully convey the scope of the
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`disclosure to those skilled in the art.
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`[0038] It will be understood that when an element such as a layer, film, area, or
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`substrate is referred to as being “on” another element, it can be directly on the other
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`element or intervening elements may also be present.
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`In contrast, when an element
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`is referred to as being “directly on” another element, there are no intervening elements
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`present.
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`[0039] Unless explicitly described to the contrary, the word “comprise” and variations
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`such as “comprises” or “comprising” will be understood to imply the inclusion of stated
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`elements but not the exclusion of any other elements.
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`[0040]
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`It will be understood that when an element(or a region, a layer, a portion, a
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`surface, or the like) is referred to as “being on,”
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`“connected to,”
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`“contacting,” or
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`“coupled to” another element in the specification, it can be directly disposed on,
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`connected, contacting, or coupled to another element mentioned above, or intervening
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`elements may be disposed therebetween.
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`[0041] It will be understood that the terms “connected to,” “contacting,” or “coupled
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`to” may include a physicalor electrical connection or coupling.
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`[0042] In the drawings, signs "x", "y", and "z" are used to indicate directions, wherein
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`x is used for indicating a first direction, y is used for indicating a second direction that
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`is perpendicularto thefirst direction, and z is used for indicating a third direction that
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`is perpendicularto the first direction and the seconddirection.
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`[0043] As used herein, the singular forms, “a,” “an,” and “the” are intended to include
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`the plural formsas well, unless the context clearly indicates otherwise.
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`[0044] In the specification and the claims, the term “and/or”is intended to include any
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`combination of the terms “and” and “or” for the purpose of its meaning and
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`interpretation. For example, “A and/or B” may be understood to mean “A, B, or A
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`and B.” The terms “and” and “or” may be used in the conjunctive or disjunctive
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`sense and maybe understood to be equivalent to “and/or.”
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`[0045] In the specification and the claims, the phrase “at least one of” is intended to
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`include the meaning of “at least one selected from the group of” for the purposeofits
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`meaning and interpretation.
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`For example, “at least one of A and B” may be
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`understood to mean “A, B, or A and B.”
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`[0046] The terms “overlap” or “overlapped” meanthata first object may be above or
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`below orto a side of a second object, and vice versa. Additionally, the term “overlap”
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`may include layer, stack, face or facing, extending over, covering, or partly covering
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`or any other suitable term as would be appreciated and understood by those of
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`ordinary skill in theart.
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`[0047] When an elementis described as ‘not overlapping’ or ‘to not overlap’ another
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`element, this may include that the elements are spaced apart from each other, offset
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`from eachother, or set aside from each other or any other suitable term as would be
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`appreciated and understood by those of ordinaryskill in theart.
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`[0048] “About,” “substantially,” or “approximately” as used herein is inclusive of the
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`stated value and means within an acceptable range of deviation for the particular value
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`as determined by one of ordinary skill in the art, considering the measurement in
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`question and the error associated with measurementof the particular quantity (i.e., the
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`limitations of the measurement system). For example, "about" may mean within one
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`or more standard deviations, or within + 30%, 20%, 10%, 5% of the stated value.
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`[0049] Unless otherwise defined or implied herein, all terms (including technical and
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`scientific terms) used herein have the same meaning as commonly understood by one
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`of ordinary skill in the art to which the disclosure pertains.
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`It will be further
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`understood that terms, such as those defined in commonly used dictionaries, should
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`be interpreted as having a meaningthat is consistent with their meaning in the context
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`of the relevant art and will not be interpreted in an idealized or overly formal sense
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`unless expressly so defined herein.
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`[0050] FIG. 1 illustrates a schematic perspective view showing an emissive display
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`device according to an embodiment.
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`[0051] Referring to FIG. 1, the emissive display device (hereinafter, simply referred to
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`as a “display device”) may include a display panel 10, a flexible printed circuit film 20
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`bondedto the display panel 10, and a driving device including an integrated circuit
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`chip 30 andthelike.
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`[0052] The display panel 10 may include a display area DA correspondingto a screen
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`on which an imageis displayed and a non-display area NA, and circuits and/or signal
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`lines for generating and/or transferring various signals and voltages applied to the
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`display area DA are disposed in the non-display area NA. The non-display area
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`NDAmaysurrounda periphery of the display area DA.
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`In FIG.1, inside and outside
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`of a dotted rectangle correspondto the display area DA and the non-display area NA,
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`respectively.
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`[0053] Pixels PX are disposed in a matrix form in the display area DA of the display
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`panel 10. Signal lines such as a gate line (also referred to as a scan line), a data line,
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`and a driving voltage line may be disposed in the display areaDA.Agate line, a data
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`line, a driving voltage line, etc. may be connected to each pixel PX, and each pixel PX
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`may receive a gate signal (also referred to as a scan signal), a data voltage, and a
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`driving voltage (also referred to as a first power voltage or a high potential power
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`voltage) from these signal lines. The pixel PX may be implementedasa light-emitting
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`device such asa light emitting diode.
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`[0054] A touch sensorfor detecting a user's touch and/or a non-contact touch may be
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`disposed in the display area DA. Although the display area DAis illustrated as
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`having a substantially rectangular shape, the display area DA may have various
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`shapes such as a polygonal shape, a circular shape, an elliptical shape, and thelike.
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`[0055] A pad portion PP with padsfor receiving signals from the outside of the display
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`panel 10 may bedisposed in the non-display area NA of the display panel 10. The
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`pad portion PP may extendin a first direction x along an edge of the display panel 10.
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`The flexible printed circuit film 20 may be bonded to the pad portion PP, and pads of
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`the flexible printed circuit film 20 may beelectrically connected to pads of the pad
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`portion PP.
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`[0056] A driving unit may be disposed in the non-display area NA ofthe display panel
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`10 and may generate and/or process various signals for driving the display panel 10.
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`The driving unit may includea data driver for applying a data voltage to the dataline,
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`a gate driver for applying a gate signal to the gate line, and a signal controller for
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`controlling the data driver and the gate driver. The pixels PX mayreceive the data
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`voltage according to a selected timing depending on the gate signal generated by the
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`gate driver. The gate driver may be integrated in the display panel 10, and may be
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`disposed on at least one side of the display area DA. The data driver and the signal
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`controller may be provided as an integrated circuit chip (also referred to as a driving
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`IC chip) 30, and the integrated circuit chip 30 may be mountedin the non-display area
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`NA of the display panel 10. The integrated circuit chip 30 may be mounted on the
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`flexible printed circuit film 20 or the like to be electrically connected to the display
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`panel10.
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`[0057] FIG.2 illustrates a schematic plan view of pixels disposed in a display area in
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`an emissive display device according to an embodiment, and FIG. 3 illustrates a
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`schematic cross-sectional view of an emissive display device taken along line A-A'in
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`FIG.2 according to an embodiment.
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`[0058] FIG.2 illustrates pixels PXa, PXb, and PXc disposed in the display area DA of
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`the display panel 10. Althoughsix pixels are illustrated, the pixels PXa, PXb, and PXc
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`may be regularly arranged in a matrix direction in the display area DA.
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`Thepixels
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`PXa, PXb, and PXc may includefirst pixels PXa, second pixels PXb, and third pixels
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`PXc. The first pixel PXa, the second pixel PXb, and the third pixel PXc may display
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`different colors, and each maydisplay one of primary colors. For example, one of the
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`first pixel PXa, the second pixel PXb, and the third pixel PXc maydisplay red, another
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`may display green, and the other may display blue. For example, the first pixel PXa
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`may display red, the second pixel PXb may display green, and the third pixel PXc may
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`display blue.
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`[0059] The first pixels PXa, the second pixels PXb, and the third pixels PXc may be
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`evenly distributed.
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`Asillustrated, the first pixel PXa and the second pixel PXb may
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`be alternately and repeatedly disposed along a second direction y.
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`Thefirst and
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`second pixels PXa and PXb andthethird pixel PXc may bealternately and repeatedly
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`disposed (or positioned)in a first direction x.
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`In other examples, the arrangementof
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`the pixels PXa, PXb, and PXc maybe changed.
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`[0060] A separation line SL may be disposed betweenthefirst pixel PXa and the second
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`pixel PXb. The separation line SL may be disposed between thefirst pixel PXa and
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`the third pixel PXc, and also between the second pixel PXb and the third pixel PXc.
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`The separation line SL may extend in the first direction x or in the second directiony.
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`[0061] Referring to FIG. 2 and FIG.3, the display panel 10 may include a substrate SB
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`and layers and elements disposed on the substrate SB. For example, an insulating
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`layer IL1 may be disposed on the substrate SB. Althoughnotillustrated, a transistor,
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`a capacitor,etc. for driving the pixels PXa, PXb, and PXc may be disposed between the
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`substrate SB and the insulating layer IL1, and will be described below.
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`[0062] The separation line SL and a connector CL may be disposed onthe insulating
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`layer IL1. The separation line SL may be in a floating state or may have a common
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`voltage (also referred to as a second powervoltage or a low potential powervoltage).
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`The connector CL maybeelectrically connected to an electrode of the transistor. The
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`connector CL may correspondto an electrodeof the transistor.
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`[0063] The separation line SL and the connector CL may each have a multi-layered
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`structure, and may include multiple conductive layers. The separation line SL may
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`include a first conductive layer Sa, a second conductive layer Sb, and a third
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`conductive layer Sc that are sequentially stacked. The connector CL may include a
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`first conductive layer Ca, a second conductive layer Cb, and a third conductive layer
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`Cc that are sequentially stacked.
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`The first conductive layer Sa and the second
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`conductive layer Sb of the separation line SL andthefirst conductive layer Ca and the
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`second conductive layer Cb of the connector CL may be formed of (may include) a
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`same material, respectively. The third conductive layer Sc of the separation line SL
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`and the third conductive layer Cc of the connector CL may be made of (may include)a
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`different material. For example, the first conductive layers Sa and Ca may be made
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`of a refractory metal such as titanium (Ti), molybdenum (Mo), chromium (Cr), or
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`tantalum (Ta), and the second conductive layers Sb and Cb may be madeof a metal
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`having low specific resistance, such as aluminum (Al), copper (Cu), or silver (Ag).
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`The third conductive layer Sc of the separation line SL, the pixel electrodes Ela, E1b,
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`and Elc may be madeof (may include) a same material. The third conductive layer
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`of the connector Cc may be made of a refractory metal such as titanium (Ti),
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`molybdenum (Mo), chromium (Cr), or tantalum (Ta). The third conductive layer Sc
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`of the separation line SL may have a multi-layered structure. For example, the third
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`conductive layer Sc may includeatriple layer including a transparent conductive
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`oxide layer (a first transparent conductive oxide layer, for example, an indium tin
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`oxide (ITO)layer), a metal layer(e.g., a silver (Ag) layer), and a transparent conductive
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`oxide layer (a second transparent conductive oxide layer, for example, a second ITO
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`layer) that are stacked sequentially.
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`[0064] In the separation line SL, the third conductive layer Sc may be wider than the
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`second conductive layer Sb.
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`In the separation line SL, the side surface of the third
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`conductive layer Sc may protrude compared to the side surface of the second
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`conductive layer Sb. The separation line SL may have an overall reverse tapered
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`structure, in which the width of the third conductive layer Sc is wider than that of the
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`lower second conductive layer Sb. The second conductive layer Sb of the separation
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`line SL maybethinner than the second conductive layer Cb of the connector CL.
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`[0065] An insulating layer IL2 may be disposed on the insulating layer IL1. The
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`insulating layer IL2 may cover a portion of the connector CL, but may not cover the
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`separation line SL. The insulating layer IL2 may have an opening OP1 overlapping
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`the separation line SL, and the width of the opening OP1 may be wider than that of
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`the separation line SL. The opening OP1 may have an elongated trench shapein the
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`longitudinal direction of the separation line SL.
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`The opening OP1 may extend
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`through the insulating layer IL2 in a third direction z.
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`[0066] Pixel electrodes Ela, E1b, and Elc maybe disposed on the insulating layer IL2.
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`Each of the pixel electrodes Ela, Elb, and Elc maybe electrically connected to the
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`corresponding connector CL through a contact hole H formedin the insulating layer
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`IL2. The adjacent pixel electrodes Ela, E1b, and Elc may be disposed on opposite
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`sides of the separation line SL and the pixel electrodes Ela, E1lb, and Elc may be
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`separated from each other.
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`[0067] A pixel defining layer PDL having (or including) openings Oa, Ob, and Oc
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`respectively overlapping the pixel electrodes Ela, E1b, and Elc may be disposed on
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`the insulating layer IL2._ The pixel defining layer PDL maycoveredgesof the pixel
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`electrodes Ela, Elb, and Elc.
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`The pixel defining layer PDL may not cover the
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`separation line SL.
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`The pixel defining layer PDL may have an opening OP2
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`overlapping the separation line SL, and a width of the opening OP2 maybe widerthan
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`that of the separation line SL and may be narrower than the width of the opening OP1.
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`The opening OP2 may extend through the pixel defining layer PDL in the third
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`direction z.
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`[0068] An emission member EM maybe disposed on the pixel electrodes Ela, E1b, and
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`Elc and the pixel defining layer PDL.
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`The emission member EM may include
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`multiple layers. Some of the layers may be formedas a single layer substantially
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`covering the entire display area DA, and some may be formed as individual layers
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`corresponding to each of the pixel electrodes Ela, Elb, and Elc.
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`A detailed
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`configuration of the emission member EM will be described below. The emission
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`member EM maybe disposed on the separation line SL. However, the emission
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`member EM may be separated by the separation line SL having a reverse tapered
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`structure.
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`For example, the emission member EM of the first pixel PXa and the
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`emission member EM of the second pixel PXb may be separated at opposite sides of
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`the separation line SL. Accordingly, current leakage between neighboring pixels
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`through the emission member EM may be prevented, and luminance of a low gray
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`pixel may be prevented from increasing due to a leakage current.
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`[0069] A commonelectrode E2 may be disposed on the emission member EM. The
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`commonelectrode E2 may also be disposed on the separation line SL. The common
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`electrode E2 may be separated at opposite sides of the separation line SL by the
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`separation line SL having an inversely tapered structure.
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`[0070] In each of the pixels PXa, PXb, and PXc, the pixel electrodes Ela, E1b, and E1c,
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`the emission member EM, and the commonelectrode E2 together may comprise the
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`light emitting diodes LEDa, LEDb, and LEDc.
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`Thepixel electrodes Ela, E1b, and Elc
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`may be anodes and the commonelectrode E2 may be a cathode.
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`[0071] A capping layer (refer to FIGS. 13, 14, and 15) may be disposed on the common
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`electrode E2, and an encapsulation layer(refer to FIGS. 13, 14, and 15) may be disposed
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`on the capping layer.
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`[0072] FIG. 4 illustrates a schematic cross-sectional view of an emission memberin an
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`emissive display device according to an embodiment.
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`[0073] Referring to FIG. 4, the stacked structure of the emission member EM of the
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`pixels PXa, PXb, and PXcis illustrated. The emission member EM maybe disposed
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`(or positioned) between the pixel electrodes Ela, Elb, and Elc, and the common
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`electrode E2. The emission member EM mayinclude multiple emission units, for
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`example, a first emission unit LUa and a second emission unit LUb. When the
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`display device displays an image, the first emission unit LUa and the second emission
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`unit LUb emit
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`light at
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`the same time,
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`thereby improving the image display
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`characteristic of the display device.
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`[0074] The first emission unit LUa may includea hole injection layer HIL, a hole
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`transport layer HTL, emission layers LEa, LEb, and LEc, and anelectron transport
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`layer ETL.
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`[0075] Each of the hole injection layer HIL, the hole transport layer HTL, and the
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`electron transport layer ETL may be formed as a single layer over the pixels PXa, PXb,
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`and PXc. For example, the hole injection layer HIL, the hole transport layer HTL, and
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`the electron transport layer ETL maybe disposed not only in the openings Oa, Ob, and
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`Oc of the pixel defining layer PDL, but also on the pixel defining layer PDL outside
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`the openings Oa, Ob, and Oc.
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`Thehole injection layer HIL, the hole transport layer
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`HTL, and the electron transport layer ETL may also be disposed on the separation line
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`SL, but may be separated at opposite sides of the separation line SL.
`
`In some
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`examples, the hole injection layer HIL, the hole transport layer HTL, and/or the
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`electron transport layer ETL may be omitted.
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`[0076] The emission layers LEa, LEb, and LEc may overlap the corresponding pixel
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`electrodes Ela, Elb, and Elc ina plan view. The emission layers LEa, LEb, and LEc
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`may be disposed (or positioned) in the corresponding openings Oa, Ob, and Ocof the
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`pixel defining layer PDL. The emission layers LEa, LEb, and LEc may be separated
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`from the emission layers LEa, LEb, and LEc of the neighboring pixels PXa, PXb, and
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`PXc. The emission layers LEa, LEb, and LEc maynotbe disposed on the separation
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`line SL. Each of the emission layers LEa, LEb, and LEc may include an organic
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`material emitting light of a primary color represented by each of the pixels PXa, PXb,
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`and PXc.
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`[0077] In each of the pixels PXa, PXb, and PXc, auxiliary layers ALa, ALb, and ALc
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`may be disposed betweenthe emission layers LEa, LEb, and LEc and the hole transport
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`layer HTL. The thickness of the auxiliary layers ALa, ALb, and ALc mayadjusts the
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`length of a light path reciprocating between the pixel electrodes Ela, E1b, and Elc and
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`the commonelectrode E2 to match the resonance conditions. At least some of the
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`auxiliary layers ALa, ALb, and ALc, e.g., the auxiliary layer ALc of the third pixel PXc,
`
`may block electrons of the emission layer LEc from passing to the hole transport layer
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`HTL. Whenthefirst pixel PXa represents red, the second pixel PXb represents green,
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`and the third pixel PXc represents blue, auxiliary layer ALa may bethe thickest and
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`auxiliary layer ALc may be the thinnest.
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`In some examples, the auxiliary layers ALa,
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`ALb, and ALc may be omitted.
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`[0078] The second emission unit LUb mayinclude the hole transport layer HTL, the
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`emission layers LEa, LEb, and LEc, a buffer layer BUF, andthe electron transport layer
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`ETL.
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`[0079] The emission layers LEa, LEb, and LEc of the second emission unit LUb may
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`have a samefunction and characteristics as those of the emission layers LEa, LEb, and
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`LEc of the first emission unit LUa.
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`[0080] In each of the pixels PXa, PXb, and PXc, auxiliary layers ALa, ALb, and ALc
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`may be disposed betweenthe emission layers LEa, LEb, and LEc and the hole transport
`
`layer HTL. The auxiliary layers ALa, ALb, and ALc may have a same function and
`
`characteristic as those of the auxiliary layers ALa, ALb, and ALc of the first emission
`
`unit LUa.
`
`[0081] Each of the hole transport layer HTL, the buffer layer BUF, and the electron
`
`transport layer ETL maybe formedasa single layer over the pixels PXa, PXb, and PXc.
`
`For example, each of the hole transport layer HTL, the buffer layer BUF, and the
`
`electron transport layer ETL maybe disposed not only in the openings Oa, Ob, and Oc
`
`of the pixel defining layer PDL, but also on the pixel defining layer PDL outside the
`
`openings Oa, Ob, and Oc. The hole transport layer HTL, the buffer layer BUF, and
`
`the electron transport layer ETL mayalso be disposed on the separation line SL, but
`
`may be separated at opposite sides of the separation line SL. The buffer layer BUF
`
`may include an insulating material.
`
`The buffer layer BUF and/or the electron
`
`transport layer ETL may be omitted.
`
`[0082] A charge generating layer CGL may be disposed betweenthefirst emission unit
`
`LUa and the second emission unit LUb. The charge generating layer CGL may
`
`include an n-type charge generating l