CLAIMS
`
`1. An electrostatic protection circuit for a chip comprising a ground pad andat least one
`
`probe pad, the electrostatic protection circuit comprising: a monitoring unit, a discharge unit
`
`and a controllable voltage dividing unit,
`
`wherein the monitoring unit
`
`is connected to the discharge unit,
`
`the controllable
`
`voltage dividing unit and the at least one probe pad, and the monitoring unit is configured to
`
`generate a first trigger signal in responseto that an electrostatic pulse is present on any probe
`
`pad;
`
`the discharge unit is connected between the ground pad andthe at least one probe pad,
`
`and configured to form, under control of the first
`
`trigger signal, at least one path for
`
`discharging electrostatic charges to the ground pad; and
`
`the controllable voltage dividing unit
`
`is connected to the discharge unit and
`
`configured to share a part of voltage of the first trigger signal for the discharge unit.
`
`2. The circuit of claim 1, wherein the discharge unit comprises at least one transistor; the
`
`controllable voltage dividing unit comprises: a first voltage dividing element havingafirst
`
`end and a second end, and a second voltage dividing element having a first end and a second
`
`end,
`
`the first voltage dividing element and the second voltage dividing element being
`
`configured to share the part of voltage of the first trigger signal for the at least one transistor,
`
`wherein the first ends of the first voltage dividing element and the second voltage
`
`dividing element are correspondingly connected to a gate of a respective one of the at least
`
`one transistor,
`
`the second end of the first voltage dividing element is connected to the
`
`monitoring unit, and the second end of the second voltage dividing element is connected to a
`
`ground terminal.
`
`17
`
`

`

`3. The circuit of claim 2, wherein the at least one transistor comprises a second transistor and
`
`a fourth transistor; the first voltage dividing element comprises a first resistor and a third
`
`resistor; and the second voltage dividing element comprises a second resistor and a fourth
`
`resistor,
`
`wherein a first end of the first resistor and a first end of the second resistor are both
`
`connected to a gate of the secondtransistor, and a first end of the third resistor and a first end
`
`of the fourth resistor are both connected to a gate of the fourth transistor; and
`
`a second end ofthe first resistor and a second end ofthe third resistor are respectively
`
`connected to the monitoring unit, and a second end of the second resistor and a second end of
`
`the fourth resistor are both connected to the ground terminal.
`
`4. The circuit of claim 3, wherein the discharge unit further comprises a first transistor and a
`
`third transistor,
`
`a drain of the first transistor and a drain of the third transistor being respectively
`
`connected to a respective one of the at least one probe pad;
`
`a gate of the first transistor and a gate of the third transistor being respectively
`
`connected to the monitoring unit; and
`
`a source of the first transistor being connected to a drain of the second transistor, and
`
`a source of the third transistor being connectedto a drain of the fourth transistor.
`
`5. The circuit of claim 1, wherein the monitoring unit comprises: a capacitor module
`
`configured to generate the first trigger signal by resistance-capacitance coupling, in response
`
`to that the electrostatic pulse is present on any probe pad,
`
`wherein a first end of the capacitor module is connected to the at least one probe pad,
`
`18
`
`

`

`a second end of the capacitor module is connected to the discharge unit, and a third end of the
`
`capacitor module is connected to the controllable voltage dividing unit.
`
`6. The circuit of claim 5, wherein the capacitor module comprises: a first capacitor, a second
`
`capacitor, a third capacitor and a fourth capacitor,
`
`wherein a first end of the first capacitor and a first end of the third capacitor are
`
`respectively connected to a respective one of the at least one probe pad, the first end of the
`
`first capacitor and the first end of the third capacitor serving as a first end of the capacitor
`
`module;
`
`a second end of the first capacitor and a second end of the second capacitor are both
`
`connected to a gate of a first transistor of the discharge unit, a second end of the third
`
`capacitor and a second end of the fourth capacitor are both connected to a gate of a third
`
`transistor of the discharge unit, wherein a connection terminal connecting the first capacitor
`
`and the second capacitor and a connection terminal connecting the third capacitor and the
`
`fourth capacitor serve as the second end of the capacitor module; and
`
`a first end of the second capacitor and a first end of the fourth capacitor are
`
`respectively connected to the controllable voltage dividing unit, wherein the first end of the
`
`second capacitor and the first end of the fourth capacitor serves as the third end of the
`
`capacitor module.
`
`7. The circuit of claim 4, wherein the at least one probe pad comprises a first probe pad and a
`
`second probe pad,
`
`both the drain of the first transistor and a first end of a first capacitor of a capacitor
`
`module of the monitoring unit are connected to the first probe pad; and
`
`both the drain of the third transistor and a first end of a third capacitor of the capacitor
`
`19
`
`

`

`module are connected to the second probe pad.
`
`8. The circuit of claim 4, wherein a first end of a second capacitor of a capacitor module of
`
`the monitoring unit is connected to the second end of the first resistor; and a first end of a
`
`fourth capacitor of the capacitor module is connected to the second endofthe third resistor.
`
`9. The circuit of claim 1, wherein the chip further comprises a power supply pad,
`
`the monitoring unit
`
`is further connected to the power supply pad, and further
`
`configured to generate a second trigger signal in response to that an electrostatic pulse is
`
`present on the power supply pad; and
`
`the discharge unit is further connected between the power supply pad and the ground
`
`pad, and further configured to be turned on undercontrol of the secondtrigger signal, so as to
`
`discharge the electrostatic charges to the ground pad.
`
`10. The circuit of claim 9, wherein the monitoring unit further comprisesa fifth capacitor and
`
`a fifth resistor,
`
`wherein a first end of the fifth capacitor is connected to the power supply pad, a
`
`second end of the fifth capacitor is connected to a first end of the fifth resistor, and a second
`
`end ofthe fifth resistor is connected to the ground pad,
`
`wherein the fifth capacitor is configured to generate the second trigger signal by
`
`resistance-capacitance coupling, in response to that the electrostatic pulse is present on the
`
`powersupply pad.
`
`20
`
`

`

`11. The circuit of claim 10, wherein the discharge unit further comprisesa fifth transistor,
`
`a drain of the fifth transistor being connected to the power supply pad, a source of the
`
`fifth transistor being connected to the ground pad, and the second endofthe fifth capacitor
`
`and the first end of the fifth resistor being also both connected to a gate of the fifth transistor,
`
`wherein the fifth transistor is configured to be turned on under control of the second
`
`trigger signal, so as to discharge the electrostatic charges to the ground pad.
`
`12. The circuit of claim 4, wherein the first transistor,
`
`the second transistor,
`
`the third
`
`transistor and the fourth transistor are all Negative-channel Metal-Oxide-Semiconductor
`
`(NMOS)transistors.
`
`13. A chip comprising a ground pad and at least one probe pad, wherein the chip further
`
`comprises an electrostatic protection circuit comprising: a monitoring unit, a discharge unit
`
`and a controllable voltage dividing unit,
`
`wherein the monitoring unit
`
`is connected to the discharge unit,
`
`the controllable
`
`voltage dividing unit and the at least one probe pad, and the monitoring unit is configured to
`
`generate a first trigger signal in responseto that an electrostatic pulse is present on any probe
`
`pad;
`
`the discharge unit is connected between the ground pad andthe at least one probe pad,
`
`and configured to form, under control of the first
`
`trigger signal, at least one path for
`
`discharging electrostatic charges to the ground pad; and
`
`the controllable voltage dividing unit is connected to the discharge unit and configured to
`
`share a part of voltage of the first trigger signal for the discharge unit.
`
`21
`
`

`

`14. The chip of claim 13, wherein the chip comprises at least a semiconductor memory.
`
`15. The chip of claim 14, wherein the semiconductor memory comprises at least a Dynamic
`
`Random Access Memory (DRAM).
`
`22
`
`

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