2022/10/25
`
`Espacenet- Bibliographic data
`
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`
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`
`Inventor(s):|YUH BERNHARD POGGE ROY[US] + (H. BERNHARD.
`POGGE,ROY. YU)
`
`Applicant(s):
`
`IBM [US] + (IBM)
`
`Classification:
`
`- international: #07127/44; HO1L21/88; NOTL29/60; HOTL21/768;
`HOWL21/98; HO1L23/48; HO1L23/485; HO1L25/068;
`(IPC1-7): HOIL2 1/44
`- cooperative: H01L.21/44 (US); HOILS 1/563 (EP); HOIL27/76898
`(EP); HO1L29/481(EP); HOIL24/84(EP);
`HOIL25/0687 (EP); HO1L25/80 (EP); HOIL2224/0407
`(EP) HOIL2224/0557 (EP): HO1L2224/0557 1 (EP):
`
`Application
`number:
`
`Priority
`number(s):
`
`HO1L2924/1461 (EP) more
`CN20028030033 20021220
`
`WO2002US4 1181 20021220
`
`AT456860 (T) AU2002368524 (AT) CN100383936 (CC)
`Also
`published as: EP1573799 (Ai) EP1573799 (Ad) EP1573799 (B1}
`
`https://worldwide.espacenet.com/publicationDetails/biblio? DB=~EPODOC&II=5&ND=3&adjacent=true&locale=en_EP&FT=D&date=20051214&CC...
`
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`Espacenet- Bibliographic data
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`

`raropeches
`European
`Patent Office
`
`Office européen des brevets
`
`(18)
`
`(12)
`
`EUROPEANPATENT SPECIFICATION
`
`(11)
`
`EP 1 573 799 B1
`
`(45) Date of publication and mention
`of the grant of the patent:
`27.01.2010 Bulletin 2010/04
`
`(21) Application number: 02808338.4
`
`(22) Date offiling: 20.12.2002
`
`(51) Int CL:
`HOTL 25/065 (2996.01)
`HOTL 21/98 2000.00)
`HO1L 21/768 (2006.01)
`
`HOTL 23/485 (2006.01)
`HOTL 21/60 (200001)
`
`(86) International application number:
`PCT/US2002/041181
`
`(87) International publication number:
`WO 2004/059720 (15.07.2004 Gazette 2004/29)
`
`(64) THREE-DIMENSIONAL DEVICE FABRICATION METHOD
`HERSTELLUNGSVERFAHREN EINER DREIDIMENSIONALEN VORRICHTUNG
`
`PROCEDE DE FABRICATION D’UN DISPOSITIF TRIDIMENSIONNEL
`
`
`(84) Designated Contracting States:
`AT BE BG CH CY CZ DE DK EE ES FI FR GB GR
`IE IT LI LU MC NL PT SE SISK TR
`
`(43) Date of publication of application:
`14.09.2005 Bulletin 2005/37
`
`(74) Representative: Ling, Christopher John
`IBM United Kingdom Limited
`Intellectual Property Department
`Hursley Park
`Wincherster
`
`Hampshire SO21 2JN (GB)
`
`(73) Proprietor: International Business Machines
`Corporation
`Armonk, NY 10504 (US)
`
`(56)
`
`(72) Inventors:
`¢ POGGE, H., Bernhard
`Hopewell Junction, NY 12533 (US)
`¢ YU, Roy
`Poughkeepsie, NY 12601 (US)
`
`Referencescited:
`JP-A- 60 140 850
`JP-A- 62 117 316
`US-A- 4 889 832
`US-A- 4 982 266
`US-A- 5 229 647
`US-A- 5 424 245
`US-A- 5 627 106
`US-A- 5 814 889
`US-A1- 2002 017 710
`US-B1- 6 489 217
`
`JP-A- 60 160 645
`US-A- 3 462 650
`US-A- 4 939 568
`US-A- 5 091 331
`US-A- 5 268 326
`US-A- 5 426 072
`US-A- 5 786 238
`US-A- 6 114 768
`US-B1- 6 444 560
`
`EP1573799B1
`
`
`
`Note: Within nine months of the publication of the mention of the grant of the European patent in the European Patent
`Bulletin, any person may give notice to the European Patent Office of opposition to that patent, in accordance with the
`Implementing Regulations. Notice of opposition shall not be deemed to have been filed until the opposition fee has been
`paid. (Art. 99(1) European Patent Convention).
`
`Printed by Jouve, 75001 PARIS (FR)
`
`

`

`Description
`
`Technical Field
`
`1
`
`EP 1 573 799 B1
`
`2
`
`Disclosure of Invention
`
`[0005] The present invention provides a method as
`claimed in claim 1.
`
`[0006] Thepresent invention addresses the above-de-
`scribed concerns by providing a method for fabricating a
`three-dimensional integrated device including a plurality
`of vertically stacked and interconnected wafers, in which
`the wafers may be reliably bonded together and the re-
`quirements for wafer flatness and highly precise align-
`ment between wafers may be relaxed. Preferably, in or-
`
`[0002] Microprocessor chips generally include a logic der to vertically connectafirst wafer and a second wafer,
`unit and cache memory.
`a via is formed in the first wafer extending from the front
`If both the logic unit and the memory devicesof a micro-
`surface, the via being characterized by a lateral dimen-
`sion at the front surface. Material is removed from the
`processor are arranged in a two-dimensional (2-D) pat-
`tern, limitations on the physical size of the chip (imposed
`by poor processyields for large-area chips) may lead to
`restrictions on the amount of cache memory. The per-
`formance of the microprocessor may therefore be se-
`verelylimited.
`[0003] To address the problem of providing adequate
`cache memory for microprocessors (and more generally
`the problem of 2-D real estate on a chip), a number of
`researchers are exploring methodsfor building three-di-
`mensional (3-D) integrated circuits. A typical 3-D fabri-
`cation processincludes building devices on wafers which
`are then thinned to less than 20 wm; providing vertical
`interconnections through the wafers; stacking the wafers
`so that vertical connections are established between wa-
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`first wafer at the back surface thereof, thinning the wafer
`to less than 20 pm. An opening is formed in the back
`surface of the first wafer, thereby exposing the via; the
`opening hasa lateral dimension greater than that of the
`via. A layer of conducting materialis formed in this open-
`ing. A stud and a layer of bonding material are formed
`on the front surface of the second wafer, the studs pro-
`jecting vertically therefrom. The stud is then aligned to
`the opening in the back surface of the first wafer; the
`wafers are bonded using the layer of bonding material,
`so that the stud makeselectrical contact with the via. In
`
`order to interconnect three wafers, the second waferis
`further provided with a via extending from the front sur-
`face of the wafer, and the second wafer is thinned by
`removing material from the second wafer at the back sur-
`face thereof. An opening is formed in the back surface
`of the second wafer, thereby exposing the via therein;
`this opening hasa lateral dimension greater than the lat-
`eral dimension of the via. A layer of conducting material
`is formed in this opening. The third wafer has a layer of
`bonding material and a stud formed on the front surface
`thereof; the stud is aligned to the opening in the back
`surface of the second wafer.
`
`The third wafer is then bonded to the second wafer using
`the layer of bonding material, so that the stud of the third
`wafer makes electrical contact with the via of the second
`
`wafer, with the stud of the second wafer, and with the via
`of the first wafer.
`
`Preferably, the vias in the respective wafers
`[0007]
`need not extend vertically from the front surface to the
`back surface of the wafers. A conducting body, provided
`in the wafer beneath the device region and extending
`laterally, may connectthe via with the metallized opening
`in the back surface. Accordingly, the conducting path
`through the wafer may be led underneath the devices
`thereof. The bonding layer is preferably a thermoplastic
`material, andin particular may be polyimide. This permits
`wafers to be bonded with less stringent requirements re-
`garding flatness and cleanliness.
`[0008] Additional openings may be formed in the back
`surface of the first wafer, to connect to additional studs
`on the front surface of the second wafer, where the ad-
`ditional openings and studs are insulated from the vias.
`
`[0001] Thisinvention relates tothe manufacture of very
`large-scale integrated semiconductor devices, and more
`particularly to methodsfor fabricating three-dimensianal,
`vertically interconnected chips.
`
`Background Art
`
`fers at different levels; and bonding the wafers with a
`suitable material. See, for example, J.-Q. Lu et al., "Fab-
`rication of via- chain test structures for 3D IC technology
`using dielectric glue bonding on 200 mm wafers," Mate-
`rials Research Society ULSI XVII Conference Proceed-
`ings 151 (2002); P. Rammetal., "Interchip via technology
`by using copper for vertical system integration,” Materials
`Research Society Advanced Metallization Conference
`159 (2002); and Rahmanet al., "Thermal analysis of
`three-dimensionalintegrated circuits," IEEE Internation-
`al
`Interconnect Technology Conference Proceedings
`157 (2001). Significant problems in the present state of
`the art of 3-D integration include (1) the needfor reliable
`wafer bonding; (2) stringent wafer cleanliness and flat-
`ness requirements; (3) the need for reliable, low-resist-
`anceinter-wafervertical connections; (4) stringent wafer-
`to-wafer lateral registration requirements; and (5) the
`needfor efficient heat conduction through the 3-D device.
`[0004] Aprocess for making 2-D chip-to-chip intercon-
`nects is described in "Process for making fine pitch con-
`nections between devices and structure made by the
`process," U.S. Pat. No. 6,444,560 assigned to Interna-
`tional Business Machines Corporation. As noted in this
`patent, chips having different functions and possibly of
`different materials may be connected through a wiring
`layer of polyimide using stud/via connections between
`the wiring layer and the respective chips.It is desirable
`to extend the techniques discussed in this patent to
`achieve 3-D chip-level and wafer-level integration.
`
`

`

`3
`
`EP 1 573 799 B1
`
`4
`
`These additional connections serve as vertical heat con-
`
`duction pathways between the wafers. The present in-
`vention therefore realizes 3-D vertical integration with
`both reliable electrical connections and improved heat
`conduction between wafers.
`
`Brief Description of Drawings
`
`[0009]
`
`ed to more or fewer than three levels. The 3-D, vertically
`integrated device may be constructed in two ways, as
`detailed below.
`
`(1) Top-down wafer stack process
`
`Figure 1A showsin cross-section a wafer 1 hav-
`[0011]
`ing devices and several levels of high-density intercon-
`nection wiring 11 (typically Cu) in a region 1d of the wafer
`near the front surface 1a thereof. Metallized vias 12 are
`
`10
`
`Figures 1A-11 are schematicillustrations of steps in
`a fabrication processfor a 3-D integrated device, in
`accordancewith a first embodimentof the invention.
`
`Figures 2A-2F are schematicillustrations of stepsin
`a fabrication processfor a 3-D integrated device, in
`accordancewith a second embodimentof the inven-
`tion.
`
`Figures 4A-4Cillustrate a fabrication processfor im-
`proving heat conduction in a 3-D integrated device,
`also in accordance with an embodimentof the inven-
`tion.
`
`15
`
`25
`
`formed in the wafer, extending below the region 1d of
`devices and lateral interconnects; these vias will become
`part of the vertical through-connections after wafer 1
`is
`thinned. Vias 12 are typically formed by etching holesin
`wafer 1, forming a layer of liner material on the sides and
`bottom of the holes, and filling the holes with metal (pref-
`erably copper). The depth of the vias 12 is less than the
`eventual thickness of wafer 1 after thinning; thus, if the
`wafer after thinning is about 10 wm thick, the vias are
`20
`
`Figure3illustrates a vertical interconnect between less than 10 pm deep. The diameter of the vias 121 must
`wafers extending laterally under a device region of
`be chosen to balance heat conduction and space con-
`the wafer, in accordance with an embodimentof the
`cerns. A diameter of approximately 1 wm consumes min-
`invention.
`imal space on the wafer surface while providing accept-
`able heat conduction through the wafer; a smaller via
`diameter may be used but may not be adequate for con-
`ducting heat through the vertical wafer stack.
`[0012]
`Forconvenienceofillustration, via 12 is shown
`extending straight downward with a uniform diameter into
`a region of the wafer below that of the devices. Size re-
`30
`
`Figure5illustrates a completed microprocessorde- quirements for the vias mayin practice be substantially
`vice including a logic unit and a 3-D stacked memory
`relaxed below region 1d. Other arrangements are possi-
`unit, the memoryunit being fabricated in accordance
`ble which involve the through-connections extending lat-
`with an embodimentof the invention, where the logic
`erally underneath the devices, as discussed in more de-
`tail below.
`and memory units are connected in a 2-D intercon-
`nection scheme using C4 technology on a multichip
`module (MCM).
`
`35
`
`In order to facilitate handling of the thinned wa-
`[0013]
`fer, a handling plate (typically of glass) 15 is attached to
`the front surface 1a of the wafer. The wafer 1 and plate
`
`Figure6illustrates a completed microprocessorde- 15 are bondedtogether using a layer 16 of a thermoplas-
`vice including a logic unit and a 3-D stacked memory
`tic bonding material, preferably polyimide.
`unit, the memory unit being fabricated in accordance
`With the handling plate 15 attached to the wafer 1, the
`with an embodimentof the invention, where the logic
`wafer is thinned by grinding or polishing the back side 1b
`and memory units are connected in a 2-D transfer
`(see Figure 1B). The resulting thickness of wafer 1 is less
`and join
`(T&J)
`interconnection scheme using
`than 20 wm, preferably about 10 wm. As shownin Figure
`stud/via connections.
`1B, the thinning processstops short of exposing the bot-
`tom of vias 12.
`
`40
`
`45
`
`Figure7illustrates a completed microprocessor de- [0014] Openings 13 are then etched in the back sur-
`
`vice including a logic unit and memory units, where
`face ib of the wafer, exposing the bottom of vials 12
`all the units are vertically integrated in accordance
`(Figure 1C). The metal in the via mayitself serve as an
`with an embodimentof the invention.
`etch stopfor this process; alternatively, an etch stop layer
`may be provided at another portion of the wafer (not pop-
`ulated by devices) to provide control for this process. It
`shouldbe noted that openings 13 have a greater diameter
`than that of vias 12. Although numerous arrangements
`of vias are possible (as discussed further below), the
`openings at the back surface 1b are generally larger than
`the vias at the front surface 1a.
`
`Best Mode for Carrying Out the Invention
`
`In accordancewith the present invention, a plu-
`[0010]
`rality of thinned wafers with devices formed thereon may
`be stacked and vertically interconnected. In the embod-
`iments described herein, a three-level stackis fabricated
`and connected;it will be appreciated that this is for illus-
`tration purposesonly, and that the process may be adapt-
`
`50
`
`55
`
`The interior surfaces 14 of opening 13 are then
`[0015]
`coated with metal (preferably by sputtering) to make con-
`
`

`

`5
`
`EP 1 573 799 B1
`
`6
`
`tact with the bottom end of the corresponding via 12, so
`that aconducting path is formed through wafer 1. Itshould
`be noted that opening 13 has a diameter greater(typically
`two times greater) than that of the corresponding via 12;
`this is to facilitate vertical connection with another wafer.
`
`Figure 1D shows a second wafer 2 which is to
`[0016]
`be vertically integrated with wafer 1. Wafer 2 has devices
`and interconnectwiring 21 formed thereon, similar to wa-
`fer 1. In addition, metallized vias 22 (typically filled with
`copper) extend downward into wafer 2; vias 22 have a
`lateral dimension 221 at surface 2a.. A layer of polyimide
`26 is deposited on the front surface 2a of wafer 2. Studs
`27 are formed on surface 2a, extending above the top
`surface of layer 26 a distance whichtypically is 5 wm or
`less. Studs 27 may be formed of Ni, Cu, Ni-plated Cu, W
`orsome other metal or combination of metals. A layer 28
`of low- melting-point alloy material is deposited on the
`surface of the stud; this facilitates formation of an elec-
`trical connection during the process of vertically joining
`wafers 1 and2. The alloy material is typically 90/10 Pb/Sn
`solder, 2 1m or less thick; alternative alloy materials in-
`clude Au/Sn and Sn/Ag. The alloy material may be sub-
`jected to a thermal reflow process so that layer 28 ac-
`quires a rounded shape, as shownin Figure 1D; this fa-
`cilitates alignmentof the studs on wafer 2 to correspond-
`ing openings in wafer 1. The studs extend electrical con-
`nections vertically upward from the devices of wafer 2,
`while the vias 22 extend electrical connectionsvertically
`downward.
`
`[0017] Wafer 1 (attached to handling plate 15) is then
`attached to wafer 2 using a bonding and lamination proc-
`ess. As shown in Figure 1E, studs 27 on wafer 2 are
`brought into registration with openings 13 on wafer 1,
`with the back surface 1b of wafer 1
`in contact with the
`
`front surface of polyimide layer 26. The lamination proc-
`ess is performed at a temperature and pressure sufficient
`to (1) ensure bonding between wafer 1 and layer 26 and
`(2) ensure electrical contact between stud 27 and metal
`14 (and thence to via 12). Depending on the materials
`used, the temperature may be in the range 200°C - 400°C
`and the pressure may bein the range 10 psi - 200 psi.
`As shownin Figure 1, the bonding and lamination proc-
`ess causes the solder 28 to flow so that solder either
`
`partially or completelyfills opening 13.
`[0018]
`It should be noted that the openings 13 have a
`greater diameter than the studs 27, and are thus able to
`accommodate imprecision in the lateral placementof wa-
`fer 2 relative to wafer 1. Furthermore, it should be noted
`that surfaces 1b and 2a are not directly in contact, but
`have layer 26 between them. Polyimide layer 26 has suf-
`ficient thickness to cover small surface particles, fill in
`minor surface defects, or accommodatedifferences in
`flatness of the two wafers. Accordingly,layer 26 plays an
`importantrole in ensuring a reliable mechanical bond be-
`tween the wafers, while
`the stud/via connection
`27-28-14-12 provides a reliable vertical electrical con-
`nection.
`
`[0019] Wafer 2 (now bonded to wafer 1) is then thinned
`
`to less than 20 pm, preferably about 10 pm. As shown
`in Figure 1F, openings 23 are formedin the back surface
`2b of wafer 2, exposing the bottom of vias 22. The interior
`surfaces of openings 23 are coated with metal. 24 (pref-
`erably by sputtering as with wafer 1), to provide electrical
`connection to another wafer 3.
`
`Figure 1G illustrates preparation of wafer 3 for
`[0020]
`bonding to wafers 1 and 2. Wafer 3 also has devices and
`interconnection wiring 31 near the front surface thereof.
`In order to make electrical contact with the back side of
`
`wafer 2, studs 37 are formed on the front side 3a of wafer
`3. Studs 37 have an alloy material 38 on the surface
`thereof, similar to studs 27 and alloy material 28 respec-
`tively on wafer 2. A polyimide layer 36 is also deposited
`on surface 3a, similar to layer 26. In thisillustration, wafer
`3 is the final wafer of the vertical stack to be bonded;
`accordingly, wafer 3 is not thinned (in order to provide
`mechanical strength for the stack) and does not require
`through-wafer vias.
`[0021]
`Figure 1H showsthe result of the bonding and
`lamination processfor wafer 3. Studs 37 are broughtinto
`electrical contact with via 22, as a result of alloy material
`38 filling opening 23 and bonding to metal layer 24. Poly-
`imide layer 36 is bonded to surface 2b of wafer 2, similarly
`to layer 26 between wafers 1 and 2. Since the unthinned
`wafer 3 provides mechanical strength to thinned wafers
`1 and 2, the handling plate 15 is no longer required and
`may be removedat this point. This may conveniently be
`done bylaser ablation; that is,
`if plate 15 is transparent
`to ablating radiation, a laser may be used to ablate the
`interface between plate 15 and layer 16, thereby detach-
`ing the plate.
`[0022]
`The vertically interconnected wafer stack 1-2-3
`may then have external connections attached, as shown
`in Figure 11. Figure 11 shows, for example, C4 technol-
`ogy used to connect the vertical stack to other compo-
`nents in a larger device. Openings 40 are formedin layer
`16 to expose the metallized vias 12 of wafer 1; metal
`pads 41 are then deposited in the openings. C4 solder
`bumps42 are then formed on these pads, using (for ex-
`ample) solder mask techniques known in the art. The
`completed vertically integrated device 100 is then ready
`to be bonded to C4 pads on a multichip module (MCM)
`or the like.
`
`It should be noted that the internal structure of
`[0023]
`wafers 1,2 and 3 has been illustrated only schematically;
`in fact, these wafers may be fabricated by a variety of
`methods and mayhavedifferent functions. For example,
`allthree wafers may have cache memory devices; wafers
`1 and 2 may have memory while wafer 3 has logic de-
`vices; one or more of the wafers may incorporate micro-
`electromechanical systems (MEMS); and so forth.
`[0024] Thepresent inventors have found that success-
`ful wafer-level vertical integration is ensured by (1) thin-
`ning wafers to about 10 pm, to minimize vertical heat-
`transfer problems in the vias; (2) using polyimide as a
`thermoplastic bonding material, to relax wafer flatness
`andcleanliness requirements; and (3) using stud/via con-
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`

`

`7
`
`EP 1 573 799 B1
`
`8
`
`nections where the backside via opening is substantially
`larger than the stud, to relax lateral registration require-
`ments.
`
`(2) Bottom-up wafer stack process
`
`Analternative process for bonding wafers in a
`[0025]
`vertical stackis illustrated in Figures 2A-2E; this process
`will be detailed for three wafers but, as noted above, may
`be adapted to more or fewer wafers. A wafer 1 is first
`prepared in accordance with the process shownin Fig-
`ures 1A-1C; this wafer thus is thinned to about 10um,
`has metallized vias 12 with openings 13 on the back sur-
`face, and has a handling plate 15 attached to the front
`surface with a polyimide layer 16.
`[0026]
`A second wafer 5, having lateral interconnect
`wiring 51, is then prepared as shownin Figure 2A. Wafer
`5 has both vias 52 and studs 57 with alloy material 58,
`similar to wafer 2 in the process described above (com-
`pare Figure 1D). A handling plate 55 is provided for wafer
`5; plate 55 is covered with a polyimide coating 56 which
`is patterned to accommodate studs 57. Wafer 5 is then
`bonded to handling plate 55, which permits the wafer to
`be thinned (Figure 2B). Openings 53 are formed in the
`backside 5b of the thinned wafer, andthe interior surfaces
`thereof are coated with a metal layer 54 as described
`previously.
`[0027]
`Since wafers 1 and5 each have respective han-
`dling plates 15 and 55, they may be prepared, bonded
`and thinned separately.
`[0028] Athird wafer 6, having lateral interconnect wir-
`ing 61, is prepared as shown in Figure 2C. This wafer
`(similarto wafer 3 as shownin Figure 1G) hasa polyimide
`layer 66 onits front surface and studs 67, with alloy ma-
`terial 68 on the surfaces thereof, for making vertical elec-
`trical connections to the other wafers. Studs 67 protrude
`from layer 66 a sufficient distance to make contact with
`the metal layer 54 on wafer 5 (thatis, about5 pm). Wafers
`5 and 6 are then bonded and laminated together, as
`shownin Figure 2D. Since wafer 6 is notthinned, handling
`plate 55 is not required after the bonding process and is
`therefore removed. At this point layer 56, on the front
`surface 5a of wafer 5, is reduced in thickness so as to
`expose about 5 wm in height of studs 57. Studs 57 are
`then ready for bonding to metal layer 14 of wafer 1. The
`result of this bonding process, wherein stacked wafers 5
`and 6 are joined to wafer 1, is shown in Figure 2E; alloy
`material 58 fills the opening 13 in thinned wafer 1, making
`electrical contact with metal layer 14 and thenceto via
`12. After wafers 5 and 6 are bondedto wafer 1, handling
`plate 15is nolongerrequired and may be removed, there-
`by exposing layer 16. Layer 16 may then have openings
`40 formed therein and metal pads 41 and C4 solder
`bumps 42 formed to connectto vias 12 (Figure 2F; com-
`pare Figure 11).
`[0029]
`It willl be appreciated that the above-described
`techniques for stacking a plurality of thinned chips, and
`incorporating vertical interconnects from chip to chip,
`
`greatly increases chip content and function without in-
`creasing its areal (two-dimensional) size. These proc-
`essesare particularly attractive for chips having the same
`content, since each of the thinned and stacked chipswill
`then have the samesize. This in turn makesthe overall
`
`processing for the device significantly simpler and more
`economical. It should be noted that these processesper-
`mit wafer-level chip-to-chip interconnection, thus making
`the process of creating 3-D chips significantly less ex-
`pensive when comparedto single-chip vertical place-
`ment, bonding and interconnection processes.
`In con-
`trast to previously described vertical
`interconnection
`schemes,
`the chip-to-chip interconnections
`in
`the
`present invention are not made along the sides of the
`chip, but are formed directly through the chip.
`[0030]
`|tis noteworthy that with the reduced thickness
`of the stacked wafer (about 10 wm), the interconnection
`length between chips (e.g. between cache memory units)
`is much smaller than in a 2-D arrangementof such chips.
`This gives the added benefit of improved device perform-
`ance, besides the savings of two-dimensional space.
`[0031]
`In Figures 1A-1l and 2A-2F,the vias are shown
`extending straight downward through the wafers and with
`a uniform diameter, for convenienceof illustration. It is
`not necessary for the vertical chip-to-chip interconnects
`to have a small diameter through the full thickness of the
`wafer, or even for the entire 10 y4m thickness of the
`thinned wafer. For example, as shownin Figure 3, wafer
`1 may be prepared with a large metal region 102 embed-
`ded therein. The vertical interconnect may then include
`a vertical wire 12 with a small diameter (less than 1 jm)
`to save space asit extends through the device area 1d
`of the wafer, and a much larger metal region 102 extend-
`ing laterally underneath the device area and connecting
`with the metallized interior surface of backside opening
`103. Opening 103 is thus separatedlaterally from via 12
`in accordance with the lateral extent of region 102. This
`arrangement minimizes the space needed for the vertical
`interconnect in the device area while at the same time
`
`reducing the resistance of the interconnect. In addition,
`it should be noted that this arrangement makesit possible
`to locate interconnect areas directly underneath device
`areas on the wafer (for example, interconnection to an-
`other wafer through opening 103 located directly under-
`neath devicesin region 1d). This in turn permits flexibility
`in the size and location of openings 103, and thus further
`relaxes the need for precise alignment between wafers
`(in this example, between wafers 1 and 2).
`[0032] The metallized vertical connections between
`wafers may be used for heat conduction as well as for
`electrical signals. For example, as shown in Figure 4A,
`an electrical pathwayis routedlaterally under the device
`region of wafer 1
`to provide additional space between
`electrical connection openings 13 on the backside 1b of
`the wafer. Additional openings 113 are formed in the wa-
`fer surface and have their interior surfaces 114 coated
`
`with metal, similar to openings 13 and metallization 14.
`(Openings 13, 113 may be formed in the same process
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`9
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`EP 1 573 799 B1
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`step; similarly for metallization 14, 114.) The additional
`openings 113 do not form part of an electrical connection,
`but serve to provide a pathway for heat conduction
`through the wafer stack. Additional studs 127, capped
`with low melting point alloy material 128, are formed on
`the front surface 2a of wafer 2, as shown in Figure 4B.
`When the wafers are bonded together in the above-de-
`scribed processes, studs 127 connect with the metal 114
`in openings 113, to form a metallized heat conduction
`pathway between wafers 1 and 2 (see Figure 4C). As
`shownin Figure 4C, studs 127 may or may not connect
`electrically with vias 22 or studs 27; no electrical signal
`is carried to the front surface of wafer 1.
`
`[0033] Although the heat conduction pathway in Fig-
`ures 4A-4C is shown as being formed between wafers 1
`and 2, it will be appreciated that this technique may be
`used to improve heat conduction between anyof the wa-
`fers in the stack in either of the above- described inte-
`
`It will be understood that units 100, 200, 401,
`[0037]
`402, 500 in Figures 5-7 need not be merely logic and/or
`memory devices, but may in fact be any of a wide variety
`of devices. Accordingly, different device technologies
`may easily be combined in a 3-D integrated device using
`the processof the presentinvention.
`
`Industrial Applicability
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`[0038] The present invention is generally applicable to
`semiconductor device structures where high areal den-
`sity of devices is required. The invention is particularly
`applicable to chips requiring large memory cache con-
`tents which cannotbe fabricated with presently available
`methods due toreticle size limitations or due tolimited
`
`processyields.
`
`Claims
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`gration processes (between wafers 2 and 3 shownin
`Figure 1H; between wafers 5 and 6 shownin Figure 2D;
`and so forth).
`1. A method for fabricating a three-dimensional inte-
`
`
`[0034] Figure5illustrates a device 400 having a ver- grated device including a plurality of vertically
`stacked and interconnected wafers,
`the method
`tically integrated stack (e.g. a cache memory unit) 100
`whichis laterally connected to a chip (e.g. a logic unit)
`comprising the stepsof:
`200, using C4 connections to a multichip module (MCM)
`
`300. The vertical memory stack and logic chip have C4 providingafirst wafer (1) having a front surface
`solder bumps 42 and 242 respectively which are bonded
`(1a) and a back surface (1b)the first wafer hav-
`to C4 pads 301 on the MCM. The MCM 300 maythen
`ing devices formed in a region (1d) adjacent to
`the front surface thereof:
`be integrated into a larger and more complex device.
`[0035] Acloser connection between the cache mem-
`forming a blind via (12) in the first wafer extend-
`ory and logic units may be realized by using stud/via con-
`ing from the front surface, the via having a lateral
`nections, as shown in Figure 6. The cache memory unit
`dimension (121) at the front surface;
`401 is prepared according to one of the processes de-
`removing material from the first wafer at the back
`scribed above, but with metallized vias 420 in polyimide
`surface (1b) thereof;
`layer 411 (compare Figures 1] and 2F). Similar vias are
`forming an opening (13) in the back surface of
`formedin polyimide layer 412 on logic unit 402. An insu-
`the first wafer, thereby exposing said via (12),
`lating layer 450 (of a low-k dielectric material, an oxide,
`the opening having a lateral dimension greater
`than said lateral dimension of the via;
`or polyimide), having interconnect wiring embedded
`therein, has studs 422 formed thereon to match the lo-
`forming a layer of conducting material (14) in
`cations of the vias. Layer 450 may be built up on a han-
`said opening making electrical contactwith said
`via;
`dling plate (not shown), with units 401 and 402 then
`broughtinto alignment with the studs 422; after a bonding
`providing a second wafer (2) having a front sur-
`process in which studs 422 are connected with metal
`face (2a) and a back surface (2b), the second
`pads 421 in the vias, the handling plate is removed from
`wafer having devices formed therein adjacent
`to the front surface thereof;
`surface 450b. The gap 403 between units 401 and 402
`maybe filled with a suitable material (e.g. polyimide) for
`forming a stud (27) on the front surface of the
`second wafer;
`increased mechanical stability. The combined device
`(now including memory unit 401, logic unit 402, and in-
`forming a layer of bonding material (26) on the
`terconnect layer 450) may then have C4 pads 451 and
`front surface (2a) of the second wafer, the studs
`C4 solder bumps 452 formed on surface 450b, to create
`projecting vertically there through;
`an external connection for the device.
`aligning the stud (27) to the opening (13) in the
`back surface of the first wafer; and
`bonding the second wafer to thefirst wafer using
`the layer of bonding material (26), so that the
`stud is broughtinto registration with said open-
`ing and makeselectrical contact with said layer
`of conducting material and said via.
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`in a device incorporating cache
`[0036] Alternatively,
`memory and a logic unit, both may be integrated in a
`vertical stack, as shown in Figure 7. Combined device
`500 includesa logic unit 510 integrated with cache mem-
`ory chips 501 and 502.
`In this arrangement,
`logic unit
`510 is atthe top of the stack, whereitis easiest to remove
`excess heat.
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`EP 1 573 799 B1
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`2. A method according to claim 1, further comprising
`the stepso