2022/10/25
`
`Espacenet- Bibliographic data
`
`
`
`tehmag|tda--aeQo@~gswe++aoo
`5%6&w2s==8tsaeaniheNo}tessafa"~4FEF¢€£29OoOooyog69©§§s§&@bbeoeZZz£6NNran“ey
`re@<=<£06ZzZDeeWiayfe=>TiOO>"peoh.:“az
`4G&~YYeweieeieiaic|NA—th:JFd“4>Oegagaahosst|oeee5meeSC]SE)Ee©—e
`bog|1&caleg)eal7Glog)+ae%If#88esauS=ythdeyoO-eex]|OFSIOoOSf<¢25SSSSSESS82gee:
`on%-@duYs)Ys)x.
` aeHiggaoFut|—N@ofSHCD2«©Baa5S6-sCaen=Nehee3FRazdgE2esA°Lo5#9gatasaSWSSeaZzOoSel<iOF=<0ZSNSGNS
`“E4aSan
`ennept>am
`
`wee:fs—ro=aec838&BB25§&conesasc=wo=©=2—oobdeeoa2EoE94aae&>@gSS25£5#5ey
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`
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`
`https://worldwide.espacenet.com/publicationDetails/biblio? DB:
`
`EPODOC&II
`
`O&ND
`
`3&adjacent=true&locale
`
`en_EP&FT=D&date=20210406&CC...
`
`1/1
`
`
`
`

`

`as) United States
`a2) Patent Application Publication (10) Pub. No.: US 2022/0189822 Al
`(43) Pub. Date: Jun. 16, 2022
`
`WANGetal.
`
`US 20220189822A1
`
`(54) WAFER BONDING METHOD AND BONDED
`WAFER
`
`(71) Applicant: Yangtze Memory Technologies Co.,
`Ltd., Wuhan (CN)
`
`(72)
`
`Inventors: Chao WANG, Wuhan (CN); Youdong
`JIANG, Wuhan (CN); Yulong
`ZHANG,Wuhan (CN); Zhiyong SUO,
`Wuhan (CN)
`
`(21) Appl. No.: 17/644,135
`
`(22) Filed:
`
`Dec. 14, 2021
`
`(30)
`
`Foreign Application Priority Data
`
`(CN) once 202011471584.2
`Dec. 14, 2020
`Publication Classification
`
`(51)
`
`Int. Ch
`HOIL 21/768
`HOIL 23/538
`HOIL 23/00
`
`(2006.01)
`(2006.01)
`(2006.01)
`
`(52) US. Cl
`CPC .. HOLL 21/76802 (2013.01); HOLL 21/76843
`(2013.01); HOLL 23/5386 (2013.01); HOIL
`2224/82896 (2013.01); HOIL 24/82 (2013.01);
`HOLL 23/5384 (2013.01); HOLL 21/76877
`(2013.01)
`
`(57)
`
`ABSTRACT
`
`A method of wafer bonding includes: forming a first hole in
`a first insulation layer disposed over a first substrate; per-
`forming a first deposition-self-etch process to deposit a first
`conductive material in the first hole to form a first conduc-
`
`tive plug; forming a second holein a secondinsulation layer
`disposed over a second substrate; performing a second
`deposition-self-etch process to deposit a second conductive
`material in the second hole to form a second conductive
`
`plug; and bondingthefirst conductive plug with the second
`conductive plug to form a first grain fusion layer between the
`first conductive plug and the second conductive plug.
`
`Forming a first conductive element in a first insulation layer disposed
`over a first substrate
`
`Forming a first connection layer covering the first conductive element
`form afirst grain fusion layer
`
`Bondingthe first connection layer with the second connection layerto
`
`Forming a second conductive element in a second insulation layer
`disposed over a second substrate
`
`Forming a second connection layer covering the second conductive
`element
`
`5100
`
`S110
`
`$120
`
`5130
`
`S140
`
`

`

`Patent Application Publication
`
`Jun. 16,2022 Sheet 1 of 8
`
`US 2022/0189822 Al
`
`S100
`Formingafirst conductive element in a first insulation layer disposed
`over a first substrate
`
`
`
`Forming a first connection layer covering the first conductive element
`
`?
`;
`:
`;
`?
`Forming a second conductive element in a second insulation layer
`disposed over a second substrate
`
`Forming a second connection layer covering the second conductive
`element
`
`Bondingthe first connection layer with the second connection layerto
`form a first grain fusion layer
`
`S110
`
`$120
`
`$130
`
`S140
`
`FIG. 1
`
`

`

`Patent Application Publication
`
`Jun. 16,2022 Sheet 2 of 8
`
`US 2022/0189822 Al
`
`Forming a first hole in a first insulation layer disposed over a first
`substrate
`
`
`
`——
`~~
`Performing a first deposition-self-etch process to deposit a first
`conductive material in the first hole to form a first conductive plug
`
`?
`?
`;
`?
`;
`Forming a second hole in a second insulation layer disposed overa
`second substrate
`
`
`
`
`
`Performing a second deposition-self-etch process to deposit a second
`
`
`conductive material in the second hole to form a second conductive plug
`
`Bondingthe first conductive plug with the second conductive plug to
`form a first grain fusion layer betweenthe first conductive plug and the
`
`second conductive plug
`
`FIG, 2
`
`S200
`
`S210
`
`$220
`
`$230
`
`S240
`
`

`

`
`
`

`

`Patent Application Publication
`
`Jun. 16,2022 Sheet 4 of 8
`
`US 2022/0189822 Al
`
`
`
`

`

`Patent Application Publication
`
`Jun. 16,2022 Sheet 5 of 8
`
`US 2022/0189822 Al
`
`
`
`FIG. 4
`
`

`

`Patent Application Publication
`
`Jun. 16,2022 Sheet 6 of 8
`
`US 2022/0189822 Al
`
`
`
`FIG. 5
`
`

`

`Patent Application Publication
`
`Jun. 16, 2022 Sheet 7 of 8
`
`US 2022/0189822 Al
`
`
`
`FIG. 6
`
`

`

`Patent Application Publication
`
`Jun. 16,2022 Sheet 8 of 8
`
`US 2022/0189822 Al
`
`
`
`

`

`US 2022/0189822 Al
`
`Jun. 16, 2022
`
`WAFER BONDING METHOD AND BONDED
`WAFER
`
`
`CROSS-REFERENCE TO RELATED
`APPLICATION
`
`[0001] This application claims priority to Chinese Patent
`Application No. 202011471584.2, filed on Dec. 14, 2020,
`the entire content of which is incorporated herein by refer-
`ence.
`
`covering the second conductive element; and a first grain
`fusion layer, including a crystal grain fusion of at least a
`portion of the first connection layer and atleast a portion of
`the second connection layer.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`TECHNICAL FIELD
`
`[0002] The present disclosure relates to the technicalfield
`ofintegrated circuits (ICs) and, moreparticularly, to a wafer
`bonding method and a bonded wafer.
`
`BACKGROUND
`
`In three-dimensional (3D) memorytechnology, a
`[0003]
`process of achieving interconnection through wafer-to-wa-
`fer bonding is used to increase density of the 3D memory.
`Specifically, a first metal pad on a surfaceofa first waferis
`connected to a second metal pad on a surface of a second
`wafer, such that the first wafer and the second wafer are
`bonded to form a bonded wafer.
`
`SUMMARY
`
`[0004] One aspect of the present disclosure provides a
`method of wafer bonding. The method includes: forming a
`first hole in a first insulation layer disposed over a first
`substrate; performing a first deposition-self-etch process to
`deposit a first conductive material in the first hole to form a
`first conductive plug; forming a second hole in a second
`insulation layer disposed over a second substrate; perform-
`ing a second deposition-self-etch process to deposit a second
`conductive material in the second hole to form a second
`
`
`
`To more clearly illustrate the technical solution in
`[0007]
`embodiments of the present disclosure, the accompanying
`drawings used in the description of the disclosed embodi-
`ments are briefly described hereinafter. The drawings
`described below are merely some embodiments of the
`present disclosure. Other drawings may be derived from
`such drawings by a person with ordinary skill in the art
`without creative efforts and may be encompassed in the
`present disclosure.
`[0008]
`FIG. 1 is a schematic flowchart of an exemplary
`wafer bonding method according to embodiments of the
`present disclosure;
`[0009]
`FIG. 2 is a schematic flowchart of another exem-
`plary wafer bonding method according to embodiments of
`the present disclosure;
`[0010]
`FIGS. 3A-3D are schematic diagramsillustrating
`an exemplary deposition-self-etch process according to
`embodiments of the present disclosure;
`[0011]
`FIG. 4 is a schematic diagram illustrating forming
`an exemplary grain fusion layer according to embodiments
`of the present disclosure;
`[0012]
`FIG. 5 isa schematic diagram illustrating forming
`another exemplary grain fusion layer according to embodi-
`ments of the present disclosure;
`[0013]
`FIG. 6is a schematic diagram illustrating an exem-
`plary bonded wafer according to embodimentsof the present
`disclosure; and
`[0014]
`FIG. 7 is a schematic diagram illustrating another
`conductive plug; and bondingthefirst conductive plug with
`exemplary bonded wafer according to embodimentsof the
`
`the second conductive plug to formafirst grain fusion layer present disclosure.
`
`betweenthefirst conductive plug and the second conductive
`.
`
`
`DETAIL
`
`plug.
`[0005] Another aspect of the present disclosure provides
`another method of wafer bonding. The method includes:
`[0015] Technical solutions in the embodiments of the
`orming a first conductive elementinafirst insulation layer
`present disclosure will be clearly described below with
`disposed overa first substrate; forming a first connection
`reference to the accompanying drawings. Although the
`ayer covering the first conductive element, wherein an
`accompanying drawings show exemplary implementation
`average grain size of the first connectionlayeris not greater
`methods of the present disclosure, it should be understood
`than an average grain size of the first conductive element;
`that the present disclosure can be implemented in various
`orming a second conductive elementin a second insulation
`forms and should not be limited by the embodiments set
`ayer disposed over a second substrate; forming a second
`forth herein. Onthe contrary, the embodiments are provided
`connection layer covering the second conductive element,
`to enable a more thorough understanding of the present
`wherein an average grain size ofthe second connection layer
`disclosure and to fully convey the scope of the present
`is not greater than an average grain size of the second
`disclosure to those skilled in theart.
`conductive element; and bondingthefirst connection layer
`[0016]
`In the following paragraphs, the present disclosure
`with the second connection layer to formafirst grain fusion
`ayer.
`will be described in more detail with examples and with
`reference to the accompanying drawings. Advantages and
`[0006] Another aspect of the present disclosure provides a
`features of the present disclosure will be apparent according
`bonding wafer. The bonded wafer includes: a first semicon-
`to the description andthe claims. It should be notedthat the
`ductor structure, includinga first substrate, a first insulation
`accompanying drawingsall adopt a simplified form and use
`ayer disposed over the first substrate, a first conductive
`imprecise proportions. For convenience and clarity,
`the
`element disposed in the first insulation layer, and a first
`drawingsare only used to assist in describing objectives of
`connection layer covering the first conductive element; a
`the embodiments of the present disclosure.
`second semiconductor structure,
`including a second sub-
`strate, a second insulation layer disposed over the second
`[0017]
`In the embodiments of the present disclosure, a
`sentence like “A and B are connected” includes situations
`substrate, a second conductive element disposed in the
`where A and B are connected with each other and are in
`second insulation layer, and a second connection layer
`
`D DESCRIPTION OF THE
`EMBODIMENTS
`
`
`
`
`
`

`

`US 2022/0189822 Al
`
`Jun. 16, 2022
`
`contact with each other or where A and B are connected
`through another component and without directly contacting
`with each other.
`
`Inthe embodiments ofthe present disclosure, terms
`[0018]
`such as “first” and “second” are used to distinguish similar
`objects and are not necessarily used to describe a specific
`sequence or order.
`[0019]
`In the embodiments of the present disclosure, a
`term “layer”refers to a material portion including a region
`having a thickness. A layer may extend over an entirety of
`a loweror upperstructure, or may have a range smaller than
`that of the lower or upper structure. In addition, the layer
`maybe a region of homogeneousor heterogeneous continu-
`ousstructure having a thickness smaller than a thickness of
`the continuous structure. For example, the layer may be
`disposed between a top surface and a bottom surface of the
`continuousstructure or may be disposed betweentwoplanes
`where the top surface and the bottom surface are located
`respectively. The layer may extend horizontally, vertically,
`and/or along an inclined surface. The layer may include a
`plurality of sub-layers.
`[0020]
`It will be appreciated that the described embodi-
`ments are some rather than all of the embodiments of the
`present disclosure. Other embodiments obtained by those
`having ordinary skills in the art on the basis of the described
`embodiments without inventive efforts should fall within the
`
`scope of the present disclosure.
`[0021] Embodiments of the present disclosure will be
`described in detail in connection with the drawings. Under
`circumstances of no conflict,
`the following embodiments
`and features in the embodiments may be combined with
`each other.
`
`[0022] A process of bonding wafers is critical to a yield
`rate of the bonded wafer. However, the existing technology
`for bonding the wafers does not provide sufficient grain
`fusion between two bonded wafers, thereby lowingreliabil-
`ity of the bonded wafer. Thus,
`it
`is urgent to solve the
`reliability problem of bonding wafers.
`[0023]
`FIG. 1 is a schematic flowchart of an exemplary
`wafer bonding method according to embodiments of the
`present disclosure. As shown in FIG. 1, the method includes
`the following processes.
`[0024] At S100, a first conductive element is formed in a
`first insulation layer disposed overa first substrate.
`[0025] At S110,a first connection layer is formed to cover
`the first conductive element. An average grain size of the
`first connection layer is not greater than an average grain
`size of the first conductive element.
`
`[0026] At S120, a second conductive elementis formed in
`a second insulation layer disposed over a second substrate.
`[0027] At S130, a second connection layer is formed to
`coverthe second conductive element. An average grain size
`of the second connectionlayer is not greater than an average
`grain size of the second conductive element.
`[0028] At S140, the first connection layer and the second
`connection layer are bonded to form a first grain fusion
`layer.
`In some embodiments,thefirst insulation layer and
`[0029]
`the second insulation layer are formed separately by a same
`method. For example, a chemical vapor deposition (CVD)
`method maybe used to form thefirst insulation layer over
`the first substrate and form the second insulation layer over
`the second substrate.
`
`Thefirst insulation layer and the second insulation
`[0030]
`layer may be made of a same material. For example,thefirst
`insulation layer and the second insulation layer may be made
`of silicon oxide or nitrogen-doped silicon carbide (NDC).
`[0031]
`In some embodiments, when the first insulation
`layer is formed,a first hole may be reserved for forming the
`first conductive element. At $100, the first hole may be
`deposited with metal to form the first conductive element.
`[0032]
`Similarly, when the second insulation layer is
`formed, a second hole may be reserved for forming the
`second conductive element. At S120, the second hole may
`be deposited with metal to form the second conductive
`element.
`
`[0033] A method of forming the first conductive element
`at $100 may be the sameas a method of forming the second
`conductive element at $120. For example, a physical vapor
`deposition (PVD) or a CVD method maybe used to form the
`first conductive element and the second conductive element.
`
`Thefirst conductive element and the second con-
`[0034]
`ductive element may be made of a same material. For
`example, the first conductive element and the second con-
`ductive element may be made of copper.
`[0035] A method of forming thefirst connection layer at
`5110 may be the same as a method of forming the second
`connection layer at $130. For example, a PVD method may
`be used to form the first connection layer and the second
`connection layer.
`[0036]
`Thefirst connection layer and the second connec-
`tion layer may be made of a same material. For example,the
`first connection layer and the second connection layer may
`be made of copper.
`[0037]
`It should be noted that although thefirst connection
`layer and the first conductive element may be made of a
`same material and the second connection layer and the
`second conductive element may be made of another same
`material, the first connection layer and the first conductive
`element may be formed by different methods and the second
`connection layer and the second conductive element may be
`formed by different methods, such that an average grain size
`of the first conductive element is greater than an average
`grain size ofthe first connection layer and an average grain
`size of the second conductive element is greater than an
`average grain size of the second connection layer.
`[0038]
`In some embodiments, grain sizes of the first
`connection layer and the second connection layer are
`between 20 nm and 100 nm. For example, the sizes of the
`first connection layer and the second connection layer are
`between 20 nm and 30 nm.
`
`[0039] The average grain size of the first connection layer
`may be the same as the average grain size of the second
`connection layer. Alternatively, the average grain size of the
`first connection layer may be slightly greater than the
`average grain size of the second connectionlayer. Alterna-
`tively, the average grain size of the first connection layer
`may beslightly smaller than the average grain size of the
`second connection layer. The present disclosure does not
`limit the average grain sizes thereof.
`[0040] At S140, the first connection layer and the second
`connection layer are bonded through a high-temperature
`bonding method or a high-temperature and high-pressure
`bonding method to form thefirst grain fusion layer, thereby
`achieving wafer bonding.
`[0041] For example, $140 may include: aligning the first
`connection layer with the second connection layer to make
`
`

`

`US 2022/0189822 Al
`
`Jun. 16, 2022
`
`
`
`the first connection layer contact the second connection
`ayer and to make the first insulation layer surrounding the
`first connection layer contact with the second insulation
`ayer surrounding the second connection layer; and heating
`the first connection layer and the second connection layer
`that contact with each otherto fuse the crystal grains ofthe
`first connection layer and the crystal grains of the second
`connection layer together at a contact interface or a bond
`interface and to form thefirst grain fusion layer.
`[0042] Due to fusion of the crystal grainsin the first grain
`usion layer, an average grain size of the first grain fusion
`ayer is greater than the average grain size of the first
`connectionlayer, and the average grain size ofthefirst grain
`usion layer is greater than the average grain size of the
`second connection layer.
`[0043]
`In some embodiments, the grain size of the first
`grain fusion layer is between 100 nm and 200 nm. For
`example, the grain size of the first grain fusion layer is
`between 90 nm and 110 nm. In some embodiments, the grain
`size of the first connection layer and the second connection
`layer is between 20 nm and 100 nm. For example, the grain
`size of the first connection layer and the second connection
`layer is between 20 nm and 30 nm.
`[0044]
`It should be noted that before the first connection
`layer and the second connection layer are bonded, a contact
`interface (also knownas a bondinterface) betweenthefirst
`connectionlayer and the second connectionlayer is coplanar
`with a contact interface betweenthefirst insulation layer and
`the second insulation layer. After the first connection layer
`and the second connection layer are bonded, the first con-
`nection layer and the second connection layer form an
`integral structure, and the contact interface or the bond
`interface between the first connection layer and the second
`connection layer no longer exists.
`[0045]
`Ina process of crystal grain fusion, crystal grains
`absorb energy from ambient environment to regenerate and
`fuse with adjacent crystal grains. For example, in the high-
`temperature bonding method, a temperature of a wafer
`bonding process maybe raised to provide more energy to
`boost the fusion of the crystal grains in the first connection
`layer and the second connection layer.
`[0046]
`In some embodiments, the first conductive element
`and the second conductive element are directly bonded to
`form the bonded wafer. Because the average grain size of the
`first conductive element and the second conductive element
`(e.g., >200 nm) are relatively large, fusion of the crystal
`grains at the contact interface between thefirst conductive
`element and the second conductive element maybe insuf-
`ficient, such that a bonding structure formed between the
`first conductive element and the second conductive element
`includes a crystal grain boundary. The crystal grain bound-
`ary basically coincides with the contact interface between
`the first conductive element and the second conductive
`
`element, deteriorates the mechanical andelectrical proper-
`ties of the bonding structure, and makes the bonding
`between the first conductive element and the second con-
`ductive elementless reliable.
`
`[0047] Because the average grain size of the first connec-
`tion layeris not greater than the average grain sizeofthefirst
`conductive element and the average grain size of the second
`connectionlayeris not greater than the average grain size of
`the second conductive element, a grain boundary energy of
`the crystal grains inthe first connection layer is higher than
`a grain boundary energy of the crystal grains in thefirst
`
`conductive element and a grain boundary energy of the
`crystal grains in the second connection layer is higher than
`a grain boundary energyof the crystal grains in the second
`conductive element. As such, a migration rate of the crystal
`grains at the bonding boundary between thefirst connection
`layer and the second connection layer is higher than a
`migration rate of the crystal grains at the bonding boundary
`between the first conductive element layer and the second
`conductive element. Thus, in the wafer bonding process, a
`probability of crystal grain fusion across the grain boundary
`is increased anda risk of delamination in a bondingarea is
`reduced.
`
`
`
`[0048] Therefore, compared with directly bondingthefirst
`conductive element and the second conductive element that
`
`haverelatively large average grain size (e.g., >200 nm) to
`formthe bonded wafer, the embodiments consistent with the
`present disclosure,
`through bonding the first connection
`layer and the second connection layer that have relatively
`small grain size (e.g., 20 nm to 30 nm), improveefficiency
`and quality of forming the first grain fusion layer, increase
`a bondingstrength of the bondinginterface, reduce a contact
`resistance of the bonding interface, and provide reliable
`mechanical and electrical properties of the bonded wafer.
`[0049]
`Further, compared with directly bonding thefirst
`conductive element and the second conductive element that
`haverelatively large grain size (e.g., >200 nm) to form the
`
`bonded wafer, the embodiments consistent with the present
`
`
`
`disclosure achieve a high efficiency of the crystal grain
`fusion through bonding the first connection layer and the
`second connection layerthat have relatively small grain size
`(e.g., 20 nm to 30 nm). Thus, the embodiments consistent
`with the present disclosure increase the crystal grain fusion
`at the bonding boundary betweenthe first connection layer
`and the second connection layer without increasing a ther-
`mal budget of the wafer bonding process.
`[0050]
`It should be understood that methods ofincreasing
`the fusion of the crystal grains by raising a temperature of
`the wafer bonding process or extending a time intervalof the
`wafer bonding process not only increase the thermal budget
`or a manufacturing cost of the wafer bonding process, but
`also provide limited improvementof the fusion of the crystal
`grains. The embodiments consistent with the present disclo-
`sure increase the fusion ofthe crystal grains andat the same
`time have minimal impact on the thermal budget and the
`manufacturing cost.
`[0051]
`In some embodiments, forming the first conductive
`element in the first insulation layer disposed over the first
`substrate (S100) includes: forming a first hole in the first
`insulation layer; depositing a first conductive material in the
`first hole to form the first conductive element that has a
`
`height smaller than a height ofthe first hole, and to form a
`first groove over the first conductive element in the first
`insulation layer.
`[0052]
`In some embodiments, forming thefirst connection
`layer covering the first conductive element (S110) includes:
`depositing a first connection material in the first groove to
`formthe first connection layer.
`[0053]
`In some embodiments, the first hole in the first
`insulation layer may be formed by a dry etching method.
`[0054]
`In a process of depositing the first conductive
`materialin thefirst hole, a deposition time may be controlled
`to control a height of the first conductive element, thereby
`ensuring the height of the first conductive element is not
`greater than the heightofthefirst hole. As such, a top surface
`
`

`

`US 2022/0189822 Al
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`Jun. 16, 2022
`
`depositing the first connection material in the third groove to
`formthe first connection layer.
`[0065]
`In some embodiments, at S100, the first electro-
`plating laver is planarized by a chemical-mechanical pol-
`ishing (CMP) process.
`[0066]
`In some embodiments, the first conductive element
`formed by planarizing thefirst electroplating layer forms a
`dish-shaped third groove on the top ofthefirst conductive
`element, such that the top surface of the first conductive
`element is lower than a top surface ofthe first insulation
`layer.
`In the embodiments of the present disclosure, the
`[0067]
`first connection layer is formed byfilling the third groove
`generated naturally in the process of forming the first
`conductive element, thereby improving the bonding quality
`while being compatible with the existing technology.
`[0068]
`In some embodiments, after the first hole is formed
`and before the first conductive element is formed, a first
`barrier layer is formed covering a sidewall and a bottom of
`the first hole. In this case, the first barrier layer is used to
`prevent particles of the first conductive element from dif-
`fusing into the first insulation layer.
`[0069]
`In some embodiments,thefirst barrier layer may be
`formed by a PVD process. The material of the first barrier
`layer is selected to work with the material of the first
`conductive element. For example, the first barrier layer is
`nade of a material
`including hafnium oxide, zirconium
`oxide, hafnium silicon oxide, lanthanum oxide, zirconium
`silicon,
`titanium oxide,
`titanium nitride,
`tantalum oxide,
`barium strontium titanium oxide, barium titantum oxide,
`strontiumtitanium oxide, aluminum oxide, or a combination
`hereof
`
`
`
`of the formed first conductive element is slightly lower than
`a top opening of the first hole, thereby forming thefirst
`groove.
`In some embodiments, formingthefirst conductive
`[0055]
`element in the first insulation layer disposed over the first
`substrate (S100) includes: forming thefirst hole in the first
`insulation layer, depositing the first conductive material in
`the first hole and on the first insulation layer to forma first
`seed layer; forming a first electroplating layer onthefirst
`seed layer; and planarizingthefirst electroplating layer until
`the first insulation layer is exposed.In this case, the first seed
`layer and the first electroplating layer remained inside the
`first hole form the first conductive element, and a top surface
`of the first conductive element includes a second groove
`having a concave surface facing toward thefirst substrate.
`[0056]
`In some embodiments, formingthefirst connection
`layer covering the first conductive element (S110) includes:
`depositing the first connection material in the second groove
`to form the first connection layer.
`[0057] For example, when thefirst conductive element is
`made of materials including copper, a Damascus process
`may be used to form the first conductive element
`that
`partially fills the first hole.
`[0058]
`In some embodiments, at S100, the first seed layer
`may be formed by a PVD process. In general, the first seed
`layeris thin. For example, a thicknessof thefirst seed layer
`ranges from 100 nmto 200 nm.Thefirst conductive material
`includes copper.
`[0059]
`In some embodiments, at S100, the first seed layer
`maybeused as an electrode to form thefirst electroplating
`layer by an electroplating process. In this case, an average
`grain size of the first electroplating layer is greater than an
`average grain size of the first seed layer.
`[0060] For example, whenthefirst seed layer andthefirst
`electroplating layer include copper, the average grain size of
`the first seed layer ranges from 20 nm to 30 nm, and the
`average grain size of the first electroplating layer ranges
`from 100 nm to 200 nm.
`
`
`
`[0070] For example, whenthe first conductive element is
`nade of materials including copper, the first barrier layer
`nay be made of materials including tantalum. In another
`example, when the first conductive element
`is made of
`naterials including copper,thefirst barrier layer may further
`include a double-layer structure including a tantalum sub-
`layer and a tantalum nitride sub-layer. In this case, the
`Insome embodiments, a ratio of a height ofthefirst
`[0061]
`antalum sub-layer is disposed between the tantalum nitride
`hole over a diameter of the first hole is greater than a
`sub-layer and the first conductive element.
`threshold. For example,the ratio is 100. In this case, the ratio
`[0071]
`Insome embodiments, after thefirst barrier layeris
`is called a high aspectratio.
`formed, the first seed layer is formed by a PVD processto
`[0062]
`In some embodiments, when the first hole has a
`coverthe first barrier layer.
`high aspect ratio, multiple pairsofthe first seed layer and the
`the first barrier layer is
`[0072]
`In some embodiments,
`first electroplating layer are formedto fill the first hole.
`formed to prevent
`the particles of the first conductive
`[0063]
`In some embodiments, formingthefirst conductive
`element from diffusing into thefirst insulation layer, thereby
`element in the first insulation layer disposed over the first
`ensuring desired performance of the bonded wafer.
`substrate at S100 includes: forming thefirst hole in the first
`
`[0073]
`In some embodiments, the first barrier layer has
`insulation layer; repeatedly performing a first deposition-
`sufficient adhesionto the first insulation layer and the first
`electroplating process to form thefirst seed layer andthefirst
`conductive element. Thus,the first barrier layer is formed to
`electroplating layer in the first hole until the first hole is
`enhance a mechanical adhesion between thefirst conductive
`filled, where the first deposition-electroplating process
`elementand thefirst insulation layer, thereby improving the
`includes depositing the first conductive material in the first
`mechanical performanceandreliability of the bonded wafer.
`hole and onthefirst insulation layer to form thefirst seed
`layer and forming the first electroplating layer on thefirst
`[0074]
`In some embodiments, a surface of the first con-
`seed layer; and planarizing the electroplating layer on the
`nection layer includesa first concave region.Afirst filling
`top ofthefirst hole until the first insulation layer is exposed,
`material is formed on the surface ofthe first connection layer
`where multiple pairs of the first seed layer and the first
`having the first concave region, where thefirst filling mate-
`electroplating layer remained inside the first hole form the
`rial protrudes from the surface ofthe first insulation layer.
`first conductive element, and a top surface of the first
`Thefirst filling material is planarized until at least a portion
`conductive element includes a third groove having a con-
`of the first connection layer is exposed, where an average
`cave surface facing toward the first substrate.
`grain size ofa firstfilling layer formed bythe remainingfirst
`[0064]
`In some embodiments, formingthefirst connection
`fillmg material is not greater than the average grain size of
`layer covering the first conductive element at $110 includes:
`the first conductive element after the planarization process.
`
`
`
`
`
`

`

`US 2022/0189822 Al
`
`Jun. 16, 2022
`
`Thefirst filling layer and the second connection layer are
`bonded together to form a second grain fusion layer.
`[0075] Whensurfaceflatness ofthe first connective plug is
`poor andthe first connection layer is thin (e.g., the thickness
`ofthe first connection layer is 100 nm), the top surface of the
`first connection layer includes the first concave region after
`the first connection layer is formed. Thefirst concave region
`degradesthe flatness of the first connection layer, causes a
`gap between the aligned first connection layer and the
`second connectionlayer, and reduces a contact area between
`the first connection layer and the second connection layer,
`thereby degrading the quality of the first grain fusion layer.
`[0076]
`Further, when the first concave region of the first
`connection layer is lower than the top surface of the first
`ins