2022/10/25
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`Espacenet- Bibliographic data
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`._~°7x~Hn$coh©"isw—6eoat9=”
`c"taanwo
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`https://worldwide.espacenet.com/publicationDetails/biblio? DB:
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`EPODOC&II
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`ionti
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`Details/bib|
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`io?DB=
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`

`
`
`43
`
`625A1
`
`US 202103
`
`as) United States
`a2) Patent Application Publication 0) Pub. No.: US 2021/0343625 Al
`
`(43) Pub. Date: Nov.4, 2021
`LIUetal.
`
`(54) METHOD FOR PACKAGING
`SEMICONDUCTOR, SEMICONDUCTOR
`PACKAGE STRUCTURE, AND PACKAGE
`
`(71) Applicant; CHANGXIN MEMORY
`TECHNOLOGIES, INC., Hefei (CN)
`
`(72)
`
`Inventors: Jie LIU, Hefei (CN); Zhan YING,
`Hefei (CN)
`
`(21) Appl. No.: 17/372,541
`
`(22) Filed:
`
`Jul. 12, 2021
`
`(52) US. Cl
`CPC .. HOLL 23/481 (2013.01); HOLL 2224/16221
`(2013.01); HOLL 21/78 (2013.01); HOLL 24/97
`(2013.01); HOLL 25/0657 (2013.01); HOIL
`24/16 (2013.01); HOIL 2924/3511 (2013.01);
`HOLL 24/94 (2013.01); HOLL 2225/06513
`(2013.01); HOIL 2225/06517 (2013.01); HOIL
`2225/06541 (2013.01); HOLL 2225/06548
`(2013.01); HOIL 2225/06586 (2013.01); HOIL
`2224/16148 (2013.01); HOIL 25/50 (2013.01)
`
`(57)
`
`ABSTRACT
`
`Related U.S. Application Data
`
`(63) Continuation of application No. PCT/CN2020/
`096255, filed on Jun. 16, 2020.
`
`(30)
`
`Foreign Application Priority Data
`
`Embodiments provide a method for packaging a semicon-
`ductor, a semiconductor package structure, and a package.
`The method includes: providing a substrate wafer having a
`first surface and a second surface arranged opposite to each
`other,
`the first surface having a plurality of grooves, a
`plurality of electrically conductive pillars being provided at
`a bottom of the groove, and the electrically conductivepillar
`penetrating through the bottom of the groove to the second
`surface; providing a plurality of semiconductor die stacks;
`placing the semiconductor die stack in the groove; and
`Int. Cl.
`covering a cover plate wafer on the first surface of the
`(2006.01)
`HOLL 23/48
`substrate wafer to seal up the groove so as to form a
`(2006.01)
`HOIL 25/00
`semiconductor package structure, a gap between the sub-
`(2006.01)
`HOLL 21/78
`strate wafer, the semiconductor die stack and the coverplate
`(2006.01)
`HOIL 23/00
`
`
`HOIL 25/065 wafer being notfilled withafiller.(2006.01)
`
`
`Oct. 16, 2019
`
`(CN) wees 201910982066.8
`
`Publication Classification
`
`(51)
`
`
`Provide 4 substrate wafer having a firs sur
`face and a second surface arranged
`opposite to cach other, the first surface b
`ra pluyality of sroeves, a chirality of
`
`electrically conductive pillars being providedat a bottomofthe groove, and the
`electrically conductive pillar penetrating through the groove w the second surface
`
`i
`
`
`p~Si0
`
`
`
`os
`
`
`Provide a plarabty of semiconductor die stacks
`
`i |
`
`
` ™ SH
`
`
`Piace (he sericouductor dic siack in the groove, an uppet sutface ol the
`semicondnctor die stack being lawer than or flush with an upper edge of the groove,
`and a bottomofthe semiconductor die stack being elecirically connectedto the
` electrically conductive pillar
`
`prt
`
`
`
`
`
`
`
`i Covera coverplate wafer on
`the groove so as to forma seraicondy
`
`substrate water, the semiconductor cic stack andthe cover plate waler being not
`filled with a filer
`
`
`Dice the semiconductor package structure along the gap between the grooves 16
`form a plurality of packages independent of each other
`
`
`
`
`

`

`Patent Application Publication
`
`Nov. 4,2021 Sheet 1 of 6
`
`US 2021/0343625 Al
`
`Provide a substrate water having a first surface and a second surface arranged
`
`opposite io cach other, the first surface having a plurality of groves, a phurality of
`electrically conductive pillars being provided at a botiomofthe groave, and the
`electrically conductive pillar penetrating through the groove io the second surface
`
`Provide a pluvahity of semiconductor die stacks
`
` e the seraiconductor die stack in the groove, an upper surface of the
`semiconductor die stack being lower than or flush with an upper edgeof the groove,
`and a bettom of the semiconductor die stack being electrically connected to the
`electrically conductive pillar
`
`Cover a cover plate wafer on the first surface ofthe substrate wafer to seal up
`the groove so as to form a semiconductor package stricture, a gap betweenthe
`substrate water, the semiconductor die stack and the cover plate wafer being not
`filled with a filler
`
`Dice the semiconductor package structure along the gap between the grooves to
`form a plurality of packages independent of cach other
`
`FIG I
`
`S12
`
`Ww pret Oo
`
`f-
`
`CA pene pe
`
`

`

`Patent Application Publication
`
`Nov. 4,2021 Sheet 2 of 6
`
`US 2021/0343625 Al
`
`200A
`
`200
`
`
`
`i
`
`ie
`
`2008
`
`200
`
`bo
`
`200e
`
`2008
`
`7
`202
`
`\
`204
`
`FIG 24
`
`
`
`200C
`
`202
`
`2008
`
`FIG 2B
`
`

`

`Patent Application Publication
`
`Nov. 4,2021 Sheet 3 of 6
`
`US 2021/0343625 Al
`
`200A
`
`
`2008
`
`FIG 2C
`
`200C
`
`209
`
`

`

`Patent Application Publication
`
`Nov. 4,2021 Sheet 4 of 6
`
`US 2021/0343625 Al
`
`200A 201
`
`
`
`210
`
`203
`
`200
`
`
`
`2008
`
`FIG 2E
`
`200A 904
`
`221
`
`307
`
`200
`
`200C
`
`202
`
`2008
`
`FG 2F
`
`

`

`Patent Application Publication
`
`Nov. 4,2021 Sheet 5 of 6
`
`US 2021/0343625 Al
`
`210
`
`200
`
`202
`
`FIG 2G
`
` 220
`
`31en
`
`300A 39
`/
`
`321
`{
`
`390
`{
`
`310
`/
`
`300
`i
`
`FIG 3
`
`

`

`Patent Application Publication
`
`Nov. 4,2021 Sheet 6 of 6
`
`US 2021/0343625 Al
`
`
`
`SS Sin
`
`AQUB
`
`FIG 4
`
`

`

`US 2021/0343625 Al
`
`Nov.4, 2021
`
`METHOD FOR PACKAGING
`SEMICONDUCTOR, SEMICONDUCTOR
`PACKAGE STRUCTURE, AND PACKAGE
`
`CROSS-REFERENCE TO RELATED
`APPLICATION
`
`
`
`
`
`[0001] This application is a continuation of PCT/CN2020/
`096255, filed on Jun. 16, 2020, which claims priority to
`Chinese Patent Application No. 201910982066.8,
`titled
`
`“METHOD FOR PACKAGING SEMICONDUCTOR,
`SEMICONDUCTOR PACKAGE STRUCTURE, AND
`PACKAGE?”andfiled on Oct. 16, 2019, the entire contents
`of which are incorporated herein
`byreference.
`
`FIELD OF THE INVENTION
`
`
`
`[0002] The present disclosurerelates to the field of semi-
`conductor package, and more particularly, to a method for
`packaging a semiconductor, a semiconductor packagestruc-
`ture, and a package.
`
`BACKGROUND OF THE INVENTION
`
`[0003] Also knownas a 3D orthree-dimensional packag-
`ing technology, a stacked packaging technology is one of
`current mainstream multi-chip packaging technologies,
`which can stack at least two semiconductor chips (also
`referred to as dies, i.e., blocks having full functions diced
`from a wafer). The stacked packaging technology is gener-
`ally employed to manufacture electronic components such
`as memorychips, logic chips, and processor chips. With the
`developmentofthe electronics industry, there are increasing
`requirements of the electronic components for high capacity,
`high function, high speed and small size. To meet
`the
`requirements, it is necessary to integrate more chips in a
`single package, which may increase a packageheight of the
`electronic components and reducereliability, thus having a
`negative effect on the performanceofthe package structure.
`[0004] Therefore, how to reduce the package height ofthe
`package and improve the reliability of the package has
`becomea technical problem urgently needing to be solved at
`present.
`
`
`
`
`
`
`
`SUMMARY OF THE INVENTION
`
`[0005] A technical problem to be solved bythe present
`disclosure is to provide a method for packaging a semicon-
`ductor, a semiconductor package structure, and a package.
`The present disclosure is characterized by a lower package
`height, a higher reliability, and a lower warpage.
`[0006]
`‘To solve the above problem, the present disclosure
`provides a method for packaging a semiconductor. The
`method includes followings steps. A substrate wafer is
`provided, which has a first surface and a second surface
`arranged opposite to each other. The first surface has a
`plurality of grooves, a plurality of electrically conductive
`pillars are provided at a bottom of the groove, and the
`electrically conductive pillar penetrates through the bottom
`of the groove to the second surface. A plurality of semicon-
`ductor die stacks is provided and placed in the groove. An
`upper surface of the semiconductor die stack is lower than
`or flush with an upper edge of the groove, and a bottom of
`the semiconductor die stack is electrically connected to the
`electrically conductive pillar. A cover plate wafer is covered
`on the first surface of the substrate wafer to seal up the
`groove so as to form a semiconductor package structure. A
`
`the semiconductor die
`gap between the substrate wafer,
`stack andthe cover plate waferare filled with air or vacuum.
`[0007]
`Further, the second surface of the substrate wafer
`has a plurality of electrically conductive blocks, and the
`electrically conductive blocks are electrically connected to
`the electrically conductive pillars.
`[0008]
`Further, the method of forming a groove on the
`substrate wafer includes: planarizing thefirst surface of the
`substrate wafer; and removing a part of the substrate wafer
`fromthe first surface until the electrically conductive pillar
`is exposed to form the groove.
`[0009]
`Further, the substrate wafer has dicing lanes, and
`the dicing lanes are used for alignment to form the groove.
`[0010]
`Further, the semiconductor die stack is formed by
`stacking a plurality of semiconductor dies electrically con-
`nected to each other, and the plurality of semiconductordies
`is electrically connectedto the electrically conductivepillars
`through the bottom of the semiconductor die stack.
`[0011]
`Further,
`the semiconductor dies are electrically
`connected to eachother through the electrically conductive
`pillar penetrating through each of the semiconductor dies
`and the electrically conductive block between the adjacent
`semiconductor dies.
`
`Further, the bottom of the semiconductordie stack
`[0012]
`is electrically connected to the electrically conductive pillar
`penetrating through the bottom of the groove through the
`electrically conductive block.
`[0013]
`Further, a surface of the cover plate wafer facing
`toward the substrate wafer has a plurality of electrically
`conductive pillars, and the electrically conductive pillar is
`electrically connected to the upper surface of the semicon-
`ductor die stack.
`
`Further, after the step of sealing up the plurality of
`[0014]
`grooves, the method also includes a dicing step: dicing the
`semiconductor package structure along gaps between the
`plurality of grooves to form a plurality of packages inde-
`pendent of each other.
`[0015] The present disclosure also provides a semicon-
`ductor package structure, which includes a substrate wafer
`having a first surface and a second surface arranged opposite
`to each other. Thefirst surface has a plurality of grooves, a
`plurality of electrically conductive pillars is provided at a
`bottom of the groove, and theelectrically conductive pillar
`penetrates through the bottom of the groove to the second
`surface. Moreover,
`the semiconductor package structure
`includesa plurality of semiconductor die stacks placed in the
`groove, wherein an upper surface of the semiconductordie
`stack is lower than orflush with an upper edge ofthe groove,
`and a bottom of the semiconductor die stack is electrically
`connectedto the electrically conductive pillar. Furthermore,
`the semiconductor package structure also includes a cover
`plate wafer coveredon thefirst surface of the substrate wafer
`to seal up the groove so as to form a groove. A gap between
`the substrate wafer, the semiconductor die stack and the
`cover plate waferare filled with air or vacuum.
`[0016]
`Further, the second surface of the substrate wafer
`has a plurality of electrically conductive blocks electrically
`connected to the electrically conductive pillars.
`[0017]
`Further, the semiconductor die stack is formed by
`stacking a plurality of semiconductor dies electrically con-
`nected to each other, and the semiconductor dies are elec-
`trically connected to the electrically conductive pillars
`through the bottom of the semiconductor die stack.
`
`

`

`US 2021/0343625 Al
`
`Nov.4, 2021
`
`FIG. 4 is a schematic structural diagram of a
`[0026]
`package according to an embodimentofthe present disclo-
`sure.
`
` .
`
`
`
`the semiconductor dies are electrically
`Further,
`[0018]
`connected to each other through the electrically conductive
`pillar penetrating through each of the semiconductor dies
`and the electrically conductive block between the adjacent
`semiconductor dies.
`
`Further, the bottom of the semiconductordie stack
`[0019]
`is electrically connected to the electrically conductive pillar
`penetrating through the bottom of the groove through the
`electrically conductive block.
`[0020]
`Further, a surface of the cover plate wafer facing
`toward the substrate wafer has a plurality of electrically
`conductivepillars electrically connected to the upper surface
`of the semiconductor die stack.
`
`[0021] The present disclosure also provides a package,
`which includes a substrate having a first surface and a
`second surface arranged opposite to each other. The first
`surface having a plurality of grooves, a pluralityof electri-
`cally conductive pillars are provided at a bottom of the
`groove, and the electrically conductive pillar penetrates
`through the bottom of the groove to the second surface.
`Moreover, the package includes at least one semiconductor
`die stack placed in the groove, wherein an upper surface of
`the semiconductor die stack is lower than or flush with an
`
`upperedge ofthe groove, and a bottom of the semiconductor
`die stack is electrically connected to the electrically con-
`ductive pillar. Furthermore,
`the package also includes a
`cover plate covered on the first surface of the substrate to
`seal up the groove. A gap betweenthe substrate, the semi-
`conductor die stack and the coverplate are filled with air or
`vacuum.
`
`
`
`DETAIL
` D DESCRIPTION OF THE
`
`EMBODIMENTS
`[0027] Embodiments of a method for packaging a semi-
`conductor, a semiconductor packagestructure and a package
`provided bythe present disclosure are described below in
`detail with reference to the accompanying drawings.
`[0028]
`FIG. 1 is a schematic diagram showingsteps of the
`method for packaging a semiconductor according to an
`embodiment of the present disclosure. With reference to
`FIG. 1, the method for packaging a semiconductor includes
`following steps. In Step S10, a substrate wafer is provided,
`and the substrate wafer has a first surface and a second
`surface arranged opposite to each other, wherein the first
`surface has a plurality of grooves, a plurality of electrically
`conductive pillars is provided at a bottom of the groove, and
`the electrically conductive pillar penetrates through the
`bottom of the groove to the second surface. In Step S11, a
`plurality of semiconductor die stacks is provided. In Step
`S12, the semiconductor die stack is placed in the groove,
`wherein an upper surface of the semiconductor die stack is
`lower than or flush with an upper edge of the groove, and a
`bottom of the semiconductor die stack is electrically con-
`nected to the electrically conductive pillar. In Step S13, a
`cover plate wafer is covered on the first surface of the
`substrate wafer to seal up the groove so as to form a
`semiconductor package structure. A gap between the sub-
`strate wafer, the semiconductor die stack and the coverplate
`[0022] Advantagesof the present disclosure are as below.
`wafer is not filled with a filler. In Step $14, the semicon-
`A groove is formed on the substrate wafer to accommodate
`ductor packagestructure is diced along the gap between the
`the semiconductor die stack, and the semiconductor die
`groovesto form a plurality of packages independentof each
`stack is sealed up by a cover plate wafer. In this way, the
`other.
`height of the semiconductor packagestructure can begreatly
`reduced while the same number of semiconductor dies is
`FIG. 2A-FIG 2G are schematic flow diagrams of
`[0029]
`the method for packaging a semiconductor according to an
`packaged, such that ultra-thin packaging can be achieved.
`embodimentofthe present disclosure.
`Furthermore, the gap betweenthe substrate wafer, the semi-
`[0030] Referring to Step S10 and FIG. 2C, a substrate
`conductor die stack and the cover plate wafer is not filled
`wafer 200 is provided, and the substrate wafer 200 hasa first
`with the filler. Instead, the groove is sealed up merely by
`surface 200A and a second surface 200B arranged opposite
`using the cover plate wafer, and then the semiconductor die
`to each other. The first surface 200A has a plurality of
`stack is sealed up. In this way, it can be solved the problem
`grooves 201, a plurality of electrically conductive pillars
`ofreliability and the problem of warpage caused by defor-
`202 are provided at a bottom of the groove 201, and the
`mation of the semiconductor package structure due to mis-
`electrically conductive pillar 202 penetrates through the
`match between an expansion coefficientofthe filler and an
`bottom of the groove 201 to the second surface 200B.
`expansion coefficient of the substrate wafer and mismatch
`[0031] An embodiment of forming the groove 201 is
`between an expansion coefficient of the semiconductor die
`described below by wayofillustration.
`stack and an expansion coefficient of the cover plate wafer.
`[0032] Referring to FIG. 2A, the substrate wafer 200 has
`Therefore, the semiconductor package structure formed by
`a first surface 200A and a second surface 200B arranged
`using the method for packaging a semiconductor provided
`opposite to each other. The first surface 200A is a back
`by the present disclosure hasabetter reliability and a lower
`warpage.
`surface of the substrate wafer 200, and the second surface
`200B is a front surface of the substrate wafer 200. Thatis,
`on the second surface 200B, the substrate wafer 200 has a
`functional layer 200C. Theelectrically conductive pillar 202
`extends from the second surface 200B into the substrate
`
`
`
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`
`
`
`FIG. 1 is a schematic diagram showing steps of a
`[0023]
`method for packaging a semiconductor according to an
`embodiment of the present disclosure;
`[0024]
`FIG. 2A-FIG. 2G are schematic flow diagrams of
`the method for packaging a semiconductor according to an
`embodiment of the present disclosure;
`[0025]
`FIG. 3 is a schematic structural diagram of a
`semiconductor package structure according to an embodi-
`mentof the present disclosure; and
`
`wafer 200, and the surface of the electrically conductive
`pillar 202 is exposed to the second surface 200B. The
`electrically conductivepillar 202 not onlycan playa role of
`conductingelectricity, but also can play a role of conducting
`heat.
`
`[0033] Referring to FIG. 2B, thefirst surface 200A ofthe
`substrate wafer 200 is planarized to facilitate subsequent
`processes. Further, the first surface 200A of the substrate
`
`

`

`US 2021/0343625 Al
`
`Nov.4, 2021
`
`
`
`wafer 200 may be planarized by using a chemical mechani-
`cal polishing method. In this step, a thickness of the sub-
`strate wafer 200 is reduced. It is to be noted that after this
`step is performed, a distance H from the first surface 200A
`ofthe substrate wafer 200 to the functional layer 200C of the
`
`second surface 200B is greater than or equal to a height of
`
`the semiconductor die stack 210 to provide sufficient opera-
`tion space for the subsequent processes.
`[0034] Referring to FIG. 2C, a part of the substrate wafer
`200 is removed from the first surface 200A until the elec-
`trically conductive pillar 202 is exposed to form the groove
`201. In this step, a photolithography and etching process
`may be employed to remove a part of the substrate wafer
`200, and the etching is not stopped until the electrically
`conductive pillar 202 is exposedat the bottom of the groove
`201. Further, when the etching is about to be stopped,
`etching conditions may be adjusted to ensure that an edge
`etching rate of the groove 201 is smaller than an etching rate
`of a middle part of the groove 201, such that a bottom corner
`of the groove 201 is shaped like an arc, which can enhance
`the stability of the side wall of the groove 201.
`[0035]
`Further, in this step, the substrate wafer 200 has a
`dicing lane 203. As shown in FIG. 2C, the groove 201 is
`formed when the dicing lane 203 passes through the gap
`between two adjacent grooves 201. The dicing lane 203 may
`serve as an alignment mark for forming the groove 201. In
`this way,
`the accuracy of forming the groove 201 is
`improved, andthere is no need to makeadditional alignment
`marks, such that process steps are saved, and production
`efficiency is improved.
`[0036] The above embodiment is an embodimentof form-
`ing the groove 201 onthefirst surface 200A ofthe substrate
`wafer 200. In other embodiments of the present disclosure,
`other methods may also be employed to form the groove 201
`on the first surface 200A of the substrate wafer 200.
`
`In this embodiment, the width of the dicing lane
`[0037]
`203 is equal to the distance between two grooves 201. In
`other embodimentsofthe present disclosure, the groove 201
`may occupya part of space ofthe dicing lane 203, such that
`the distance between the two adjacent grooves 201 is smaller
`than the width of the dicing lane 203, which makesit easier
`to place the semiconductor die stack 210 into the groove 201
`subsequently. Furthermore, a side surface of the semicon-
`ductor die stack 210 can be prevented from touching the
`sidewall of the groove 201, and thusit is avoidable to have
`a negative effect on the performance of the semiconductor
`die stack 210.
`
`Further, with continued reference to FIG. 2A, a
`[0038]
`plurality ofelectrically conductive blocks 204 is provided on
`the second surface 200B of the substrate wafer 200, and the
`electrically conductive block 204 is electrically connected to
`the electrically conductive pillar 202 to electrically connect
`the electrically conductive pillar 202 to an external device
`such as a printed circuit board. The electrically conductive
`block 204 maybe formed on the second surface 200B of the
`substrate wafer 200 before the groove 201 is formed.
`[0039] Referring to Step S11 and FIG. 2D,a plurality of
`semiconductordie stacks 210 is provided. The numberof the
`semiconductor die stacks 210 may be equal to that of the
`grooves 201, or the number of the semiconductordie stacks
`210 may be more than that of the grooves 201. In one
`embodiment, if the number of the semiconductordie stacks
`210 is equal to that of the grooves 201, in the subsequent
`processes, one semiconductordie stack 210 is placed in one
`
`groove 201. If the number of the semiconductor die stacks
`210 is more than that of the grooves 201, two or more
`semiconductor die stacks 210 may be placed in parallel in
`one groove 201.
`[0040] The semiconductor die stack 210 is formed by
`stacking a plurality of semiconductor dies 210A. In this
`embodiment, three semiconductor dies 210A are schemati-
`cally shown. The three semiconductor dies 210A are sequen-
`tially stacked to form the semiconductordie stack 210. In the
`semiconductor die stack 210, the semiconductor dies 210A
`are electrically connected to each other, such that an elec-
`trical signal of the semiconductor die 210A can be trans-
`mitted to an external structure. In this embodiment, the
`semiconductor dies 210A are electrically connected to each
`other throughthe electrically conductivepillar 211 penetrat-
`ing through each of the semiconductordies and theelectri-
`cally conductive block 212 between the adjacent semicon-
`ductor dies. The method of forming the electrically
`conductive pillar on the semiconductor die 210A includes
`but is not limited to a throughsilicon via (TSV) process well
`knownin theart.
`
`[0041] After this step is completed, a surface of the
`electrically conductive pillar is exposed at the bottom of the
`semiconductor die stack 210, and the surface of the electri-
`cally conductive pillar is also exposed at the top of the
`semiconductor die stack 210.
`
`the
`[0042] With reference to Step S12 and FIG. 2E,
`semiconductor die stack 210 is placed in the groove 201. In
`this step, one or more semiconductor die stacks 210 may be
`placed in one of the grooves 201. In this embodiment, one
`semiconductor die stack 210 is placed in one groove 201.
`[0043] The bottom of the semiconductor die stack 210 is
`electrically connected to the electrically conductive pillar
`202 penetrating through the bottom of the groove 201. That
`is,
`the electrically conductive pillar 211 exposed at the
`bottom of the semiconductor die stack 210 is electrically
`connected to the electrically conductive pillar 202 exposed
`at the bottom of the groove 201. In one embodiment, the
`electrically conductive pillar 211 and the electrically con-
`ductive pillar 202 maybeelectrically connected through the
`electrically conductive block 213.
`[0044] The upper surface of the semiconductor die stack
`210 is lower than orflush with the upper edge of the groove
`201 to facilitate subsequent processes. In this embodiment,
`the upper surface of the semiconductor die stack 210 is
`lower than the upper edge of the groove 201.
`[0045] With reference to Step $13 and FIG. 2F, a cover
`plate wafer 220 is covered on thefirst surface 200A of the
`substrate wafer 200 to seal up the groove 201 so as to form
`a semiconductor package structure. After this step is per-
`formed, interior space of the groove 201 is confined space.
`The cover plate wafer 220 and the substrate wafer 200 may
`be combined by a bonding process, such that the groove 201
`is sealed up.
`[0046] According to the method for packaging a semicon-
`ductor provided by the present disclosure, a groove is
`formed on the substrate wafer to accommodate the semi-
`conductor die stack, and the semiconductor die stack is
`sealed up by a cover plate wafer. In this way, the height of
`the semiconductor package structure can begreatly reduced
`while the same number of semiconductor dies is packaged,
`suchthat ultra-thin packaging can be achieved. Furthermore,
`the gap between the substrate wafer 200, the semiconductor
`die stack 210 and the cover plate wafer 220 is notfilled with
`
`

`

`US 2021/0343625 Al
`
`Nov.4, 2021
`
`the filler. Instead, the groove 201 is sealed up merely by
`using the cover plate wafer 220, and then the semiconductor
`die stack 210 is sealed up. In this way, it can be solved the
`problem ofreliability caused by deformation of the semi-
`conductor package structure due to mismatch between an
`expansion coefficient of the filler and an expansion coefii-
`cient of the substrate wafer and mismatch between an
`
`through the electrically conductive pillar 311 penetrating
`through each of the semiconductor dies 310A and the
`electrically conductive block 312 between the adjacent
`semiconductor dies 310A, and maybeelectrically connected
`to the electrically conductive pillar 302 through the bottom
`of the semiconductor die stack 310. The bottom of the
`
`semiconductor die stack 310 maybe electrically connected
`to the electrically conductive pillar 302 through theelectri-
`expansion coefficient of the semiconductor die stack and an
`cally conductive block 313.
`expansion coeflicient of the coverplate wafer. Therefore, the
`semiconductor package structure formed by using the
`[0052] The cover plate wafer 320 is covered the first
`method for packaging a semiconductor provided by the
`surface 300Aof the substrate wafer 300 to seal up the groove
`present disclosure has a good reliability.
`301. A gap between the substrate wafer 300, the semicon-
`[0047]
`Further, a surface of the cover plate wafer 220
`ductor die stack 310 and the cover plate wafer 320 is not
`facing toward the substrate wafer 200 has a plurality of
`filled withafiller. Further, a surface of the cover plate wafer
`electrically conductive pillars 221 electrically connected to
`320 facing toward the substrate wafer 300 hasa plurality of
`the upper surface of the semiconductor die stack 210. That
`electrically conductive pillars 321 electrically connected to
`is, the electrically conductivepillar 221 on the surface of the
`the uppersurface of the semiconductordie stack 310. In one
`cover plate wafer 220 is electrically connected to the elec-
`embodiment, the electrically conductive pillar 321 is elec-
`trically conductive pillar 211 exposed on the upper surface
`trically connected to the electrically conductive pillar 311
`of the semiconductor die stack 210. The cover plate wafer
`exposed onthe upper surface of the semiconductordie stack
`220 can provide heat conduction to the semiconductor die
`310. The coverplate wafer 300 can provide heat conduction
`stack 210 through theelectrically conductive pillar 221 and
`to the semiconductordie stack 310 through the electrically
`can further fix the semiconductordie stack 210. In addition,
`conductive pillar 321 and can further fix the semiconductor
`in the semiconductor packaging, other wafers may also be
`die stack 310. In addition, in the semiconductor packaging,
`stacked on the cover plate wafer 220, and the electrically
`other wafers mayalso be stacked on the cover plate wafer
`conductive pillar 221 may function as electrical connection.
`300, andthe electrically conductive pillar 321 may function
`as electrical connection.
`[0048] Alternatively, in this embodiment, after Step S13 is
`performed,the present disclosure also includesa dicing step.
`In the semiconductor package structure provided
`[0053]
`With reference to Step S14 and FIG. 2G the semiconductor
`by the present disclosure, a groove is formed onthe substrate
`package structure is diced along the gap between the
`wafer to accommodate the semiconductor die stack, and the
`grooves 201 to formaplurality of packages independent of
`groove is sealed up by the cover plate wafer. In this way, the
`each other. In one embodiment, the semiconductor package
`height of the semiconductor packagestructure can begreatly
`structure is diced along the dicing lane 203 between the
`reduced, such that ultra-thin packaging can be achieved.
`grooves 201 to formaplurality of packages independent of
`Furthermore, the gap between the substrate wafer, the semi-
`each other. The dicing method includes but is not limited to
`conductor die stack and the cover plate wafer is notfilled
`mechanical dicing, laser dicing and the like.
`with thefiller. Instead, the groove is sealed up merely by
`[0049] The present disclosure also provides a semicon-
`using the cover plate wafer, and then the semiconductor die
`ductor package structure formed by using the above-men-
`stack is sealed up. In this way, it can be solved the problem
`tioned method for packaging a semiconductor. FIG. 3 is a
`of reliability of the semiconductor package structure caused
`schematic structural diagram of the semiconductor package
`by mismatch between an expansion coefficient of the filler
`structure according to an embodimentof the presentdisclo-
`and an expansion coefficient of the substrate wafer and
`
`sure. With reference to FIG. 3, the semiconductor package
`mismatch between an expansion coefficient of the semicon-
`
`
`
`structure includes a substrate wafer 300, a plurality of
`ductor die stack and an expansion coefficient of the cover
`semiconductor die stacks 310, and a coverplate wafer 320.
`plate wafer. Therefore, the semiconductor packagestructure
`[0050] The substrate wafer 300 has a first surface 300A
`provided bythe present disclosure has goodreliability.
`and a second surface 300B arranged opposite to each other.
`[0054] The present disclosure also provides a package.
`The first surface 300A has a plurality of grooves 301, a
`FIG. 4 is a schematic structural diagram of the package
`plurality of electrically conductivepillars 302 are provided
`according to an embodimentof the present disclosure. With
`at a bottom of the groove 301, and the electrically conduc-
`reference to FIG. 4, the package is formed by dicing the
`tive pillar 302 penetrates through the bottom of the groove
`ab