2022/10/25
`
`Espacenet- Bibliographic data
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`https://worldwide.espacenet.com/publicationDetails/biblio? DB:
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`EPODOC&II
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`3&adjacent=true&locale
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`en_EP&FT=D&date=20210416&CC...
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`

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`Espacenet- Bibliographic data
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`

`

`as) United States
`a2) Patent Application Publication 0) Pub. No.: US 2021/0335757 Al
` LIU et al. (43) Pub. Date: Oct. 28, 2021
`
`
`
`US 20210335757A1
`
`(54) METHOD FOR PACKAGING
`SEMICONDUCTOR, SEMICONDUCTOR
`PACKAGE STRUCTURE, AND PACKAGE
`
`(71) Applicant; CHANGXIN MEMORY
`TECHNOLOGIES, INC., Hefei (CN)
`
`(72)
`
`Inventors: Jie LIU, Hefei (CN); Zhan YING,
`Hefei (CN)
`
`(21) Appl. No.: 17/372,530
`
`(22) Filed:
`
`Jul. 12, 2021
`
`Related U.S. Application Data
`
`(63) Continuation of application No. PCT/CN2020/
`096254, filed on Aug. 14, 2020.
`
`(30)
`
`Foreign Application Priority Data
`
`Oct. 16, 2019
`
`(CN)ee 201910982076.1
`
`Publication Classification
`
`(51)
`
`Int. Ch
`HOIL 25/065
`HOIL 23/00
`
`(2006.01)
`(2006.01)
`
`(2006.01)
`(2006.01)
`
`HOIL 21/78
`HOIL 25/00
`(52) US. Cl.
`CPC vases HOLL 25/0657 (2013.01); HOLL 23/562
`(2013.01); HOLE 21/78 (2013.01): HOIL
`2225/06586 (2013.01); HOLL 2225/06513
`(2013.01); HOIL 2225/0654] (2013.01): HOIL
`2225/06548 (2013.01); HOLE 25/50 (2013.01)
`
`(57)
`
`ABSTRACT
`
`Embodiments provide a method for packaging a semicon-
`ductor, a semiconductor package structure, and a package.
`The packaging method includes: providing a substrate wafer
`having a first surface and a second surface arranged opposite
`to each other, the first surface having a pluralityof grooves,
`a plurality of electrically conductive pillars being provided
`at a bottom of the groove, and the electrically conductive
`pillar penetrating through the bottom of the groove to the
`second surface; providing a plurality of semiconductor die
`stacks; placing the semiconductor die stack in the groove;
`and filling an insulating dielectric in a gap between a
`sidewall of the groove and the semiconductor die stack to
`formaninsulating dielectric layer covering an upper surface
`of the semiconductor die stack to seal up the semiconductor
`die stack so as to form the semiconductor packagestructure.
`
`400A
`
`
`
`

`

`Patent Application Publication
`
`Oct. 28,2021 Sheet 1 of 6
`
`US 2021/0335757 Al
`
`
`
`
`Provide a sibsivate wafer having a first surface and a second suriace arranged
`
`~S10
`:
`opposite to cach other, the first surface having a plurality of grooves, a plurality of
`
`electrically conductive pillars being provided at a bottom of the groove, and the
`
`
`
`
` electrically conductive pillar penetrating through the groove tc the second surface Tf pee.
`
` Provide a pintality af semiconductordie stacks
`
`pene
`
`
`
`Place the semiconductor die stack in the groove, ap upper surface of the
`
`
`semsconductordie stack being lower thanor flush with an upper edge af the groove,
`
` and a bottom of the semiconductor die stack being electrically comnected to the
`
`
`electncally conductive pillar
`
`.
`»
`3
`e
`.
`.
`.
`:
`sexmiconductor die stack to forra an insulating dielectnec layer covering an upper
`surface of the semiconductor die stack to seal up the semiconductordie stack so as to
`form a semiconductor package structure
`
`Ful an insulating dielectric ia pap betweona sidewall of the groove and the
`
`
`.
`in
`Loy
`a
`oe
`.
`-
`Cover an upper sutface of the insulating dielectric layer and the Brst surface of
`the substrate wafer with a cover plate water
`
`ie) yo No
`
`O19
`ia
`pia
`
`a
`
`tA
`S14
`
`Dice the semiconductor package structure along the gap between the grooves to
`
`S15
` form. a phirality of packages independent of each other
`
`FIG I
`
`

`

`Patent Application Publication
`
`Oct. 28,2021 Sheet 2 of 6
`
`US 2021/0335757 Al
`
`200A
`
`200
`
` q
`
`
`2008
`
`200
`
`pn
`Z00C
`
`200A
`
`:
`
`\
`4
`204
`
`FIG 2A
`
`200€
`
`202
`
`3008
`
`

`

`Patent Application Publication
`
`Oct. 28,2021 Sheet 3 of 6
`
`US 2021/0335757 Al
`
`2004
`
`201
`
`4
`
`‘)
`O49
`
`2008
`
`200€
`
`202
`
`FIG 2C
`
`FIG 2D
`
`

`

`Patent Application Publication
`
`Oct. 28,2021 Sheet 4 of 6
`
`US 2021/0335757 Al
`
`ye
`21 213
`
`é
`a
`200C
`
`2008
`
`“ \
`
`ANS
`202
`
`:
`
`230
`
`FIG 2E
`
`2008
`
`200
`
`200A 201
`
`
`2600
`
`°
`
`909
`
`2008
`
`FIG 2F
`
`

`

`Patent Application Publication
`
`Oct. 28,2021 Sheet 5 of 6
`
`US 2021/0335757 Al
`
`200A 924
`
`221
`
`299
`
`200 2000
`200A
`
`200C
`
`*
`
`HA
`
`on
`202
`
`FEG 2G
`
`2008
`
`FIG 2H
`
`

`

`Patent Application Publication
`
`
`
`US 2021/0335757 Al
`
`Oct. 28,2021 Sheet 6 of 6
`
`
`
`

`

`[0001] This application is a continuation of PCT/CN2020/
`096254, filed on Aug. 14, 2020, which claims priority to
`Chinese Patent Application No. 201910982076.1,
`titled
`
`“METHOD FOR PACKAGING SEMICONDUCTOR,
`SEMICONDUCTOR PACKAGE STRUCTURE, AND
`PACKAGE?”andfiled on Oct. 16, 2019, the entire contents
`of which are incorporated herein
`byreference.
`
`FIELD OF THE INVENTION
`
`
`
`
`
`
`
`US 2021/0335757 Al
`
`Oct. 28, 2021
`
`METHOD FOR PACKAGING
`SEMICONDUCTOR, SEMICONDUCTOR
`PACKAGE STRUCTURE, AND PACKAGE
`
`CROSS-REFERENCE TO RELATED
`APPLICATION
`
`electrically conductive pillar. An insulating dielectric is
`filled in a gap between a sidewall of the groove and the
`semiconductor die stack to form an insulating dielectric
`layer covering an upper surface of the semiconductor die
`stack to seal up the semiconductor die stack so as to form a
`semiconductor package structure.
`[0007]
`Further, the second surface of the substrate wafer
`has a plurality of electrically conductive blocks electrically
`connected to the electrically conductive pillars.
`[0008]
`Further, the method of forming a groove on the
`substrate wafer includes: planarizing thefirst surface of the
`substrate wafer; and removing a part of the substrate wafer
`fromthe first surface until the electrically conductive pillar
`is exposed to form the groove.
`[0009]
`Further, the substrate wafer has a dicing lane, and
`the dicing lane serves as an alignment mark for forming the
`groove.
`Further, each ofthe plurality of semiconductor die
`[0010]
`stacks is formed by stacking a plurality of semiconductor
`dies electrically connected to each other, and the bottom of
`the semiconductor die stack is electrically connected to the
`electrically conductive pillar through the semiconductordie.
`[0011]
`Further,
`the semiconductor dies are electrically
`connected to eachother through the electrically conductive
`pillar penetrating through each of the semiconductor dies
`and the electrically conductive block between the adjacent
`semiconductor dies.
`
`[0002] The present disclosurerelates to the field of semi-
`conductor package, and more particularly, to a method for
`packaging a semiconductor, a semiconductor packagestruc-
`ture, and a package.
`
`BACKGROUND OF THE INVENTION
`
`[0003] Also knownas a 3D orthree-dimensional packag-
`ing technology, a stacked packaging technology is one of
`current mainstream multi-chip packaging technologies,
`which can stack at least two semiconductor chips (also
`referred to as dies, i.e., blocks having full functions diced
`from a wafer). The stacked packaging technology is gener-
`ally employed to manufacture electronic components such
`as memorychips, logic chips, and processor chips. With the
`developmentofthe electronics industry, the electronic com-
`ponents are required for high capacity, high function, high
`speed and small size. To meet the above requirements, it is
`necessary to incorporate more chips in a single package,
`which may increase a package height of the electronic
`components. Furthermore, when a semiconductor package
`structure moves or vibrates, there maylikely exist slight
`translocation between the chips, which results in poorreli-
`ability of a package structure andhas a negative effect on the
`performance of the package structure.
`[0004] Therefore, how to reduce the package height ofthe
`package and improve the reliability of the package has
`becomea technical problem urgently needing to be solved at
`present.
`
`
`
`SUMMARY OF THE INVENTION
`
`
`
`the
`the
`
`
`
`Further, the bottom of the semiconductordie stack
`[0012]
`is electrically connected to the electrically conductive pillar
`penetrating through the bottom of the groove through the
`electrically conductive block.
`
`
`[0013]
`Further, a thermal expansion coefficient of
`substrate wafer is greater than or equal
`to that of
`insulating dielectric layer.
`[0014]
`Further, the substrate wafer is a silicon wafer, and
`the insulating dielectric layer is a silicon dioxide insulating
`dielectric layer.
`[0015]
`Further, the method for packaging a semiconductor
`also includes: covering an upper surface of the insulating
`dielectric layer and the first surface of the substrate wafer
`with a cover plate wafer.
`[0016]
`Further, a surface of the cover plate wafer facing
`toward the substrate wafer has a plurality of electrically
`conductive pillars, and the electrically conductive pillar is
`electrically connected to the upper surface of the semicon-
`ductor die stack through an electrically conductive structure
`in the insulating dielectric laver.
`[0005] A technical problem to be solved bythe present
`[0017]
`Further, after the step of sealing up the semicon-
`disclosure is to provide a method for packaging a semicon-
`ductor die stack, the method also includes a dicing step:
`ductor, a semiconductor package structure, and a package.
`dicing the semiconductor package structure along the gap
`The present disclosure is characterized by a lower package
`between the grooves to form a plurality of packages inde-
`height, a higher reliability, and a lower warpage.
`pendent of each other.
`[0006]
`‘To solve the above problem, the present disclosure
`[0018] The present disclosure also provides a semicon-
`provides a method for packaging a semiconductor. The
`method includes followings steps. There is provided a
`ductor package structure, which includes a substrate wafer
`substrate wafer, which hasafirst surface and a second
`having a first surface and a second surface arranged opposite
`surface arranged opposite to each other. Thefirst surface has
`to each other. Thefirst surface has a plurality of grooves, a
`a plurality of grooves, a plurality of electrically conductive
`plurality of electrically conductive pillars is provided at a
`pillars is provided at a bottom of the groove, and the
`bottom of the groove, and theelectrically conductive pillar
`electrically conductive pillar penetrates through the bottom
`penetrates through the bottom of the groove to the second
`of the groove to the second surface. A plurality of semicon-
`surface. Moreover,
`the semiconductor package structure
`ductor die stacks is provided and placed in the groove. An
`includesa plurality of semiconductor die stacks placed in the
`upper surface of the semiconductor die stack is lower than
`groove, wherein an upper surface of the semiconductordie
`or flush with an upper edge of the groove, and a bottom of
`stack is lower than orflush with an upper edge ofthe groove,
`the semiconductor die stack is electrically connected to the
`and a bottom of the semiconductor die stack is electrically
`
`

`

`US 2021/0335757 Al
`
`Oct. 28, 2021
`
`ultra-thin packaging can be achieved. In addition, the insu-
`lating dielectric layer fills the gap between the sidewall of
`the groove and the semiconductor die stack, and the insu-
`lating dielectric layer can fix the semiconductor die stack,
`suchthat translocation between the semiconductor dies may
`be prevented even though the semiconductor packagestruc-
`ture movesorvibrates, thereby preventing a poor connection
`between the semiconductor dies and a poor connection
`between the semiconductordie stack and the substrate wafer.
`
`In this way, the stability of the semiconductordie stack is
`improved, and the reliability of the semiconductor package
`structure is improved.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`
`
`FIG. 1 is a schematic diagram showingsteps of a
`[0029]
`method for packaging a semiconductor according to an
`embodimentofthe presentdisclosure;
`[0030]
`FIG. 2A-FIG 2H are schematic flow diagrams of
`the method for packaging a semiconductor according to an
`embodimentofthe presentdisclosure;
`[0031]
`FIG. 3 is a schematic structural diagram of a
`semiconductor package structure according to an embodi-
`mentof the present disclosure; and
`[0032]
`FIG. 4 is a schematic structural diagram of a
`package according to an embodiment ofthe present disclo-
`sure.
`
` .
`
`
`
`DETAIL
` D DESCRIPTION OF THE
`EMBODIMENTS
`
`
`
`[0033] Embodiments of a method for packaging a semi-
`conductor, a semiconductor packagestructure and a package
`provided bythe present disclosure are described below in
`detail with reference to the accompanying drawings.
`[0034]
`FIG. 1 isa schematic diagram showingsteps of the
`method for packaging a semiconductor according to an
`embodimentofthe present disclosure. Referring to FIG.1,
`the method for packaging a semiconductor includes follow-
`ing steps. In Step S10, a substrate waferis provided, and the
`substrate wafer has a first surface and a second surface
`arranged opposite to each other, wherein thefirst surface has
`a plurality of grooves, a plurality of electrically conductive
`pillars is provided at a bottom of the groove, and the
`electrically conductive pillar penetrates through the bottom
`of the groove to the second surface. In Step S11, a plurality
`of semiconductor die stacks is provided. In Step $12, the
`semiconductor die stack is placed in the groove, wherein an
`pper surface of the semiconductor die stack is lower than
`or flush with an upper edge of the groove, and a bottom of
`the semiconductor die stack is electrically connected to the
`electrically conductive pillar. In Step $13, an insulating
`dielectric is filled in a gap between a sidewall of the groove
`and the semiconductor die stack to form an insulating
`dielectric layer covering an upper surface of the semicon-
`ductor die stack to seal up the semiconductordie stack so as
`to form a semiconductor package structure. In Step S14, an
`pper surface of the insulating dielectric layer and the first
`surface of the substrate wafer are covered with a coverplate
`wafer. In Step S15, the semiconductor package structureis
`diced along the gap between the grooves to form a plurality
`of packages independent of each other.
`[0035]
`FIG. 2A-FIG 2H are schematic flow diagrams of
`the method for packaging a semiconductor according to an
`embodimentofthe present disclosure.
`
`
`
`connectedto the electrically conductive pillar. Furthermore,
`the semiconductor package structure also includes an insu-
`lating dielectric layerfilling a gap between a sidewall of the
`groove and the semiconductor die stack and covering an
`upper surface of the semiconductor die stack to seal up the
`semiconductor die stack.
`
`Further, the second surface of the substrate wafer
`[0019]
`has a plurality of electrically conductive blocks, and the
`electrically conductive blocks are electrically connected to
`the electrically conductivepillars.
`[0020]
`Further, each ofthe plurality of semiconductor die
`stacks is formed bystacking a plurality of semiconductor
`dies electrically connected to each other, and the semicon-
`ductor dies are electrically connected to the electrically
`conductive pillars through the bottom of the semiconductor
`die stack.
`
`the semiconductor dies are electrically
`Further,
`[0021]
`connected to each other through the electrically conductive
`pillar penetrating through each of the semiconductor dies
`and the electrically conductive block between the adjacent
`semiconductor dies.
`
`
`
`Further, the bottom of the semiconductordie stack
`[0022]
`is electrically connected to the electrically conductive pillar
`penetrating through the bottom of the groove through the
`electrically conductive block.
`[0023]
`Further, a thermal expansion coefficient of the
`substrate wafer is greater than or equal
`to that of the
`insulating dielectric layer.
`[0024]
`Further, the substrate wafer is a silicon wafer, and
`the insulating dielectric layer is a silicon dioxide insulating
`dielectric layer.
`[0025]
`Further, an upper surface ofthe insulating dielec-
`tric layer and the first surface of the substrate wafer are
`covered with a cover plate wafer.
`[0026]
`Further, a surface of the cover plate wafer facing
`toward the substrate wafer has a plurality of electrically
`conductive pillars, in the insulating dielectric layer there is
`provided with an electrically conductive structure, and the
`electrically conductive pillar is electrically connectedto the
`upper surface of the semiconductor die stack through the
`electrically conductive structure.
`[0027] The present disclosure also provides a package,
`which
`includes a substrate having a first surface and a
`second surface arranged opposite to each other. The first
`surface has at least one groove, a plurality of electrically
`conductivepillars is provided at a bottom of the groove, and
`the electrically conductive pillar penetrates through the
`bottom of the groove to the second surface. Moreover, the
`package includesat least one semiconductordie stack placed
`in the groove, wherein an upper surface of the semiconduc-
`tor die stack is lowerthan orflush with an upper edgeof the
`groove, and a bottom of the semiconductor die stack is
`electrically connected to the electrically conductive pillar.
`Furthermore, the packagealso includes an insulating dielec-
`tric layerfilling a gap between a sidewall of the groove and
`the semiconductor die stack and covering an upper surface
`of the semiconductordie stack to seal up the semiconductor
`die stack.
`
`[0028] Advantagesof the present disclosure are as below.
`A groove is formed on the substrate wafer to accommodate
`the semiconductor die stack, and is sealed up byan insu-
`lating dielectric layer. The height of the semiconductor
`package structure can be greatly reduced while the same
`number of semiconductor dies are packaged, such that
`
`

`

`US 2021/0335757 Al
`
`Oct. 28, 2021
`
`[0036] Referring to Step S10 and FIG. 2C, there is pro-
`other methods may also be employed to form the groove 201
`on the first surface 200A of the substrate wafer 200.
`vided a substrate wafer 200, which hasafirst surface 200A
`and a second surface 200B arranged opposite to each other.
`[0043]
`In this embodiment, the width of the dicing lane
`The first surface 200A has a plurality of grooves 201, a
`203 is equal to the distance between two grooves 201. In
`plurality of electrically conductive pillars 202 is provided at
`other embodiments ofthe present disclosure, the groove 201
`a bottom of the groove 201, and the electrically conductive
`may occupya part of space of the dicing lane 203, such that
`pillar 202 penetrates through the bottomof the groove 201
`the distance between the two adjacent grooves 201 is smaller
`to the second surface 200B.
`than the width of the dicing lane 203, which makesit easier
`to place the semiconductor die stack 210 into the groove 201
`subsequently. Furthermore, a side surface of the semicon-
`ductor die stack 210 can be prevented from touching the
`sidewall of the groove 201 to avoid having a negative effect
`on the performance of the semiconductordie stack 210.
`[0044]
`Further, with continued reference to FIG. 2A, a
`plurality of electrically conductive blocks 204 is provided on
`the second surface 200B ofthe substrate wafer 200, and the
`electrically conductive blocks 204 are electrically connected
`to the electrically conductive pillars 202 to electrically
`connect the electrically conductive pillars 202 to external
`devices such as printed circuit boards. The electrically
`conductive block 204 may be formed on the second surface
`200B of the substrate wafer 200 before the groove 201 is
`formed.
`
`[0037] An embodiment of forming the groove 201 is
`described below by wayofillustration.
`[0038] Referring to FIG. 2A, the substrate wafer 200 has
`a first surface 200A and a second surface 200B arranged
`opposite to each other. The first surface 200A is a back
`surface of the substrate wafer 200, and the second surface
`200B is a front surface of the substrate wafer 200. Thatis,
`on the second surface 200B, the substrate wafer 200 has a
`functional layer 200C. Theelectrically conductivepillar 202
`extends from the second surface 200B into the substrate
`wafer 200, and the surface of the electrically conductive
`pillar 202 is exposed to the second surface 200B. The
`electrically conductivepillar 202 not only canplaya role of
`conducting electricity, but also can play a role of conducting
`heat.
`
`[0039] Referring to FIG. 2B, thefirst surface 200A ofthe
`substrate wafer 200 is planarized to facilitate subsequent
`processes. Further, the first surface 200A of the substrate
`wafer 200 may be planarized by using a chemical mechani-
`cal polishing method. In this step, a thickness of the sub-
`strate wafer 200 is reduced. It is to be noted that after this
`
`
`
`step is performed, a distance H from the first surface 200A
`ofthe substrate wafer 200 to the functional layer 200C of the
`second surface 200B is greater than or equal to a height of
`
`the semiconductor die stack 210 to provide sufficient opera-
`tion space for the subsequent processes, and a width of the
`groove 201 needs to be greater than or equal to that of the
`semiconductor die stack 210. In one embodiment, the width
`of the groove 201 is slightly larger than that of the semi-
`conductor die stack 210, such that the semiconductor die
`stack 210 is placed in the groove 201.
`[0040] Referring to FIG. 2C, a part of the substrate wafer
`200 is removed from the first surface 200A until the elec-
`
`trically conductive pillar 202 is exposed to form the groove
`201. In this step, a photolithography and etching process
`may be employed to remove a part of the substrate wafer
`200, and the etching is not stopped until the electrically
`conductive pillar 202 is exposedat the bottom of the groove
`201. Further, when the etching is about to be stopped,
`etching conditions may be adjusted to ensure that an edge
`etching rate of the groove 201 is smaller than an etching rate
`of a middle part of the groove 201, such that a bottom corner
`of the groove 201 is shaped like an arc, which can enhance
`the stability of the sidewall of the groove 201.
`[0041]
`Further, in this step, the substrate wafer 200 has a
`dicing lane 203. As shown in FIG. 2C, the groove 201 is
`formed when the dicing lane 203 passes through the gap
`between two adjacent grooves 201. The dicing lane 203 may
`serve as an alignment mark for forming the groove 201. In
`this way,
`the accuracy of forming the groove 201 is
`improved, andthere is no need to makeadditional alignment
`marks, such that process steps are saved, and production
`efficiency is improved.
`[0042] The above embodiment is an embodimentof form-
`ing the groove 201 onthefirst surface 200A ofthe substrate
`wafer 200. In other embodiments of the present disclosure,
`
`[0045] Referring to Step S11 and FIG. 2D,a plurality of
`semiconductordie stacks 210 is provided. The numberofthe
`semiconductor die stacks 210 may be equal to that of the
`grooves 201, or the numberof the semiconductordie stacks
`210 may be more than that of the grooves 201. In one
`embodiment, if the number of the semiconductordie stacks
`210 is equal to that of the grooves 201, in the subsequent
`processes, one semiconductordie stack 210 is placed in one
`groove 201. If the number of the semiconductor die stacks
`210 is more than that of the grooves 201, two or more
`semiconductor die stacks 210 may be placed in parallel in
`one groove 201.
`[0046] The semiconductor die stack 210 is formed by
`stacking a plurality of semiconductor dies 210A. In this
`embodiment, three semiconductor dies 210A are schemati-
`cally shown. The three semiconductor dies 210A are sequen-
`tially stacked to form the semiconductordie stack 210. In the
`semiconductor die stack 210, the semiconductor dies 210A
`are electrically connected to each other, such that an elec-
`trical signal of the semiconductor die 210A can be trans-
`mitted to an external structure. In this embodiment, the
`semiconductor dies 210A are electrically connected to each
`other throughthe electrically conductivepillar 211 penetrat-
`ing through each of the semiconductordies and theelectri-
`cally conductive block 212 between the adjacent semicon-
`
`ductor dies. Each of the semiconductor dies 210A has an
`electrically conductive pillar 211 penetrating through the
`semiconductor die 210A, and the electrically conductive
`pillars 211 of the two semiconductor dies 210Aareelectri-
`cally connected by the electrically conductive block 212
`arranged therebetween. The method of forming the electri-
`cally conductive pillar on the semiconductor die 210A
`includes but is not limited to a through silicon via (TSV)
`process well knownin the art.
`[0047] After this step is completed, a surface of the
`electrically conductive pillar is exposed at the bottom of the
`semiconductor die stack 210, and the surface of the electri-
`cally conductive pillar is also exposed on the top of the
`semiconductor die stack 210.
`
`
`
`the
`[0048] With reference to Step S12 and FIG. 2E,
`semiconductor die stack 210 is placed in the groove 201. In
`
`

`

`US 2021/0335757 Al
`
`Oct. 28, 2021
`
`this step, one or more semiconductor die stacks 210 may be
`placed in one of the grooves 201. In this embodiment, one
`semiconductor die stack 210 is placed in one groove 201.
`[0049] The bottom of the semiconductor die stack 210 is
`electrically connected to the electrically conductive pillar
`202 penetrating through the bottom of the groove 201. That
`is,
`the electrically conductive pillar 211 exposed at
`the
`bottom of the semiconductor die stack 210 is electrically
`connected to the electrically conductive pillar 202 exposed
`at the bottom of the groove 201. In one embodiment, the
`electrically conductive pillar 211 and the electrically con-
`ductive pillar 202 maybeelectrically connected through the
`electrically conductive block 213.
`[0050] The upper surface of the semiconductordie stack
`210 is lower than orflush with the upper edge of the groove
`201 to facilitate subsequent processes. In this embodiment,
`the upper surface of the semiconductor die stack 210 is
`lower than the upper edge ofthe groove 201. In addition,to
`makeit easier to place the semiconductor die stack 210 into
`the groove 201, the width of the groove 201 is greater than
`or equal to that of the semiconductor die stack 210. In this
`case, after the semiconductor die stack 210 is placed in the
`groove 201, there is a gap between the side surface of the
`semiconductor die stack 210 and the sidewall of the groove
`201.
`
`[0051] With reference to Step $13 and FIG.2F, an insu-
`lating dielectric is filled in a gap betweenthe sidewall of the
`groove 210 and the semiconductor die stack 210 to form an
`insulating dielectric layer 230, and the insulating dielectric
`layer 230 covers an upper surface of the semiconductor die
`stack 210 to seal up the semiconductordie stack 210. In this
`way, the semiconductor package structure is formed.
`[0052] After this step is performed, the groove 201 is filled
`with the insulating dielectric layer 230, the semiconductor
`die stack 210 is sealed up, the plurality of semiconductor
`dies 210A ofthe semiconductordie stack 210 is fixed to each
`other, and the semiconductor die stack 210 is fixed with
`respect
`to the substrate wafer, such that
`translocation
`between the semiconductor dies and between the semicon-
`
`ductor die stack and the substrate wafer may be prevented
`even though the semiconductor package structure moves or
`vibrates, thereby preventing a poor connection between the
`semiconductor dies and a poor connection between the
`semiconductordie stack andthe substrate wafer. In this way,
`the stability of the semiconductor die stack is improved, and
`the reliability of the semiconductor package structure is
`improved.
`[0053]
`Furthermore, according to the method for packag-
`ing a semiconductor provided by the present disclosure, a
`groove is formed onthe substrate wafer to accommodate the
`semiconductor die stack, and the semiconductordie stack is
`sealed up by an insulating dielectric layer. In this way, the
`height of the semiconductor packagestructure can begreatly
`reduced while the same number of semiconductor dies are
`packaged, such that ultra-thin packaging can be achieved.
`[0054]
`In one embodiment, the thermal expansion coefii-
`cient of the substrate wafer 200 is greater than or equal to
`that of the insulating dielectric layer 230. The advantages of
`the present disclosure are as below. When the semiconductor
`package structure is heated, the deformation of the insulat-
`ing dielectric layer 230 is less thanthat of the substrate wafer
`200, such that the substrate wafer 200 may be prevented
`from being forcedly deform, suchthatit is avoidable to have
`adverse effects on the reliability and warpage of the semi-
`
`conductor packagestructure. Of course, the thermal expan-
`sion coeflicient of the substrate wafer 200 is not allowed to
`
`differ too much fromthe thermal expansion coefficient of the
`insulating dielectric layer 230, otherwise the insulating
`dielectric layer 230 maylikely be divorced from the sidewall
`of the groove 201 of the substrate wafer 200.
`In this
`embodiment, the substrate wafer 200 is a silicon wafer, and
`the insulating dielectric layer 230 is a silicon dioxide insu-
`lating dielectric layer.
`[0055] Alternatively, the method for packaging a semi-
`conductor also includes following steps. With reference to
`Step $14 and FIG. 2G an upper surface of the insulating
`dielectric layer 230 and the first surface of the substrate
`wafer 200 are covered with a cover plate wafer 220 to
`further seal up the semiconductor die stack 210. The cover
`plate wafer 220 and the substrate wafer 200 may be com-
`bined by a bonding process.
`[0056]
`Further, a surface of the cover plate wafer 220
`facing toward the substrate wafer 200 has a plurality of
`electrically conductive pillars 221, and in the insulating
`dielectric layer 230 there is also provided with an electri-
`cally conductive pillar 231. In this case,
`the electrically
`conductive pillar 221 in the cover plate wafer 220 may be
`electrically connected to the upper surface of the semicon-
`ductor die stack 210 through the electrically conductive
`pillar 231 in the insulating dielectric layer 230. That is, the
`electrically conductive pillar 221 on the surface of the cover
`plate wafer 220 is electrically connected to the electrically
`conductive pillar 211 exposed on the upper surface of the
`semiconductordie stack 210. The cover plate wafer 220 may
`provide heat conduction to the semiconductor die stack 210
`through the electrically conductive pillar 221, and may
`further fix the semiconductor die stack 210. In addition, in
`semiconductor packaging, other wafers may be stacked on
`the cover plate wafer 220, and the electrically conductive
`pillar 221 mayfunction as electrical connection. The step of
`arranging the electrically conductive pillar 231 in the insu-
`lating dielectric layer 230 may be performed beforethe step
`of covering the cover plate wafer 220.
`[0057] Alternatively, after Step S13 or Step S14 is per-
`formed,the present disclosure also includesa dicing step. In
`this embodiment, after Step S14 is performed, the present
`disclosure also includes a dicing step. With reference to Step
`S15 and FIG. 2H, the semiconductor package structure is
`diced along the gap between the grooves 201 to form a
`plurality of packages independent of each other. In one
`embodiment, the semiconductor package structure is diced
`along the dicing lane 203 between the grooves 201 to fo