www.uspto.gov
`
`UNITED STATES DEPARTMENT OF COMMERCE
`United States Patent and Trademark Office
`Address: COMMISSIONER FOR PATENTS
`P.O. Box 1450
`Alexandria, Virginia 22313-1450
`
`17/744,895
`
`05/16/2022
`
`Ronald Beebe
`
`206529-0009-03US
`
`9828
`
`Riverside Law LLP/JABIL Inc
`175 Strafford Avenue Suite 100
`Wayne, PA 19087
`
`KINKEAD, ARNOLD M
`
`ART UNIT
`
`2849
`
`PAPER NUMBER
`
`NOTIFICATION DATE
`
`DELIVERY MODE
`
`07/26/2024
`
`ELECTRONIC
`
`Please find below and/or attached an Office communication concerning this application or proceeding.
`
`The time period for reply, if any, is set in the attached communication.
`
`Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
`following e-mail address(es):
`dcoccia @riversidelaw.com
`dockets @riversidelaw.com
`
`PTOL-90A (Rev. 04/07)
`
`

`

`
`
`Disposition of Claims*
`1-19 is/are pending in the application.
`)
`Claim(s)
`5a) Of the above claim(s) _ is/are withdrawn from consideration.
`[} Claim(s)__ is/are allowed.
`Claim(s) 1-19 is/are rejected.
`(] Claim(s)__ is/are objectedto.
`C] Claim(s
`are subjectto restriction and/or election requirement
`)
`* If any claims have been determined allowable, you maybeeligible to benefit from the Patent Prosecution Highway program at a
`participating intellectual property office for the corresponding application. For more information, please see
`http:/Awww.uspto.gov/patents/init_events/pph/index.jsp or send an inquiry to PPHfeedback@uspto.gov.
`
`) ) ) )
`
`Application Papers
`10)2 The specification is objected to by the Examiner.
`11)M The drawing(s) filed on 05-16-22 is/are: a)(¥| accepted or b)[_) objected to by the Examiner.
`Applicant may not request that any objection to the drawing(s) be held in abeyance. See 37 CFR 1.85(a).
`Replacement drawing sheet(s) including the correction is required if the drawing(s) is objected to. See 37 CFR 1.121(d).
`
`Priority under 35 U.S.C. § 119
`12)7) Acknowledgment is made of a claim for foreign priority under 35 U.S.C. § 119(a)-(d)or (f).
`Certified copies:
`c)Z None ofthe:
`b)() Some**
`a)C All
`1.1.) Certified copies of the priority documents have been received.
`2.1) Certified copies of the priority documents have been received in Application No.
`3.1.) Copies of the certified copies of the priority documents have been receivedin this National Stage
`application from the International Bureau (PCT Rule 17.2(a)).
`*“ See the attached detailed Office action for a list of the certified copies not received.
`
`Attachment(s)
`
`1)
`
`Notice of References Cited (PTO-892)
`
`Information Disclosure Statement(s) (PTO/SB/08a and/or PTO/SB/08b)
`2)
`Paper No(s)/Mail Date
`05-10-24and11-15-22.
`U.S. Patent and Trademark Office
`
`3)
`
`4)
`
`(LJ Interview Summary (PTO-413)
`Paper No(s)/Mail Date
`(Qj Other:
`
`PTOL-326 (Rev. 11-13)
`
`Office Action Summary
`
`Part of Paper No./Mail Date 20240715
`
`Application No.
`Applicant(s)
`17/744,895
`Beebeetal.
`
`Office Action Summary Art Unit|AIA (FITF)StatusExaminer
`ARNOLD M KINKEAD
`2849
`Yes
`
`
`
`-- The MAILING DATEof this communication appears on the cover sheet with the correspondence address --
`Period for Reply
`
`A SHORTENED STATUTORYPERIOD FOR REPLYIS SET TO EXPIRE 3 MONTHS FROM THE MAILING
`DATE OF THIS COMMUNICATION.
`Extensionsof time may be available underthe provisions of 37 CFR 1.136(a). In no event, however, may a reply betimely filed after SIX (6) MONTHSfrom the mailing
`date of this communication.
`If NO period for reply is specified above, the maximum statutory period will apply and will expire SIX (6) MONTHSfrom the mailing date of this communication.
`-
`- Failure to reply within the set or extended period for reply will, by statute, cause the application to become ABANDONED (35 U.S.C. § 133).
`Any reply received by the Office later than three months after the mailing date of this communication, evenif timely filed, may reduce any earned patent term
`adjustment. See 37 CFR 1.704(b).
`
`Status
`
`1)C) Responsive to communication(s) filed on
`CA declaration(s)/affidavit(s) under 37 CFR 1.130(b) was/werefiledon
`
`2a)C) This action is FINAL. 2b)¥)This action is non-final.
`3) An election was madeby the applicant in responseto a restriction requirement set forth during the interview
`on
`; the restriction requirement and election have been incorporated into this action.
`4)() Since this application is in condition for allowance except for formal matters, prosecution as to the merits is
`closed in accordance with the practice under Exparte Quayle, 1935 C.D. 11, 453 O.G. 213.
`
`

`

`Application/Control Number: 17/744,895
`Art Unit: 2849
`
`Page 2
`
`DETAILED ACTION
`
`Notice of Pre-AlA or AIA Status
`
`The present application, filed on or after March 16, 2013, is being examined under the first
`
`inventor to file provisions of the AIA.
`
`Specification
`
`The disclosure is objected to because of the following informalities: Please update the related
`
`application info.
`
`RELATED APPLICATIONS
`
`[0001] This is a Continuation Application of U.S. Application No. 17/069,459,
`
`filed October 13, 2020, entitled: "Synchronous Buck Inverter," which is a Continuation
`Application of U.S. Application No. 15/724,8339,filed October 4, 2017, entitled: "Synchronous
`Buck Inverter," which is a Continuation Application of U.S. Application No. 15/251,487,filed
`
`August 30, 2016, entitled: "Wien Bridge Oscillator," which is a Continuation Application of U.S.
`Application No. 14/675,073, filed March 31, 2015, entitled: "Wien Bridge Oscillator," which
`claims priority to U.S. Provisional Patent Application No. 62/047443,titled "Synchronous Buck
`
`Inverter," filed September 8, 2014, the contents of which are incorporated by reference herein
`
`in their respective entireties herein.
`
`Appropriate correction is required.
`
`Double Patenting
`
`A rejection based on double patenting of the “same invention” typefinds its supportin
`
`the language of 35 U.S.C. 101 which states that “whoever invents or discovers any new and
`
`

`

`Application/Control Number: 17/744,895
`Art Unit: 2849
`
`Page 3
`
`useful process... may obtain a patent therefor...’
`
`” (Emphasis added). Thus, the term “same
`
`invention,” in this context, means an invention drawn to identical subject matter. See Millerv.
`
`Eagle Mfg. Co., 151 U.S. 186 (1894); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re
`
`Ockert, 245 F.2d 467, 114 USPQ 330 (CCPA 1957).
`
`A statutory type (35 U.S.C. 101) double patenting rejection can be overcome by
`
`canceling or amending the claims that are directed to the same invention so they are no longer
`
`coextensive in scope. The filing of a terminal disclaimer cannot overcome a double patenting
`
`rejection based upon 35 U.S.C. 101.
`
`Claims 1-19 of the current application ‘895 is/are rejected under 35 U.S.C. 101 as claiming the
`
`same invention as that of claims 1-19 of prior U.S. Patent No. 11.336.204. This is a statutory
`
`double patenting rejection.
`
`17/744895
`
`11,336,204
`
`low frequency switching circuit.
`
`1. An inverter, comprising: a high frequency
`
`switching control circuit operatively coupled
`
`to a DC power input; a synchronous-buck
`
`circuit, operatively coupled to the high
`
`frequency switching control circuit and
`
`comprising a plurality of switches controlled
`
`by the high frequency switching control
`
`circuit to cyclically invert the DC power input;
`
`and a low frequency switching circuit for
`
`providing an oscillated output and
`
`operatively coupled to the synchronous buck
`
`circuit to provide zero voltage switching and
`
`zero current switching by driving an output
`
`capacitor circuit to discharge on each zero
`
`crossing of the low frequency switching
`
`circuit.
`
`1. An inverter, comprising: a high
`frequency switching control circuit
`operatively coupled to a DC power input;
`a synchronous-buckcircuit, operatively
`coupled to the high frequency switching
`control circuit and comprising a plurality
`of switches controlled by the high
`frequency switching control circuit to
`cyclically invert the DC power input; and a
`low frequency switching circuit for
`providing an oscillated output and
`operatively coupled to the synchronous
`buckcircuit to provide zero voltage
`switching and zero current switching by
`driving an output capacitor circuit to
`discharge on each zero crossing of the
`
`

`

`Application/Control Number: 17/744,895
`Art Unit: 2849
`
`
`Page 4
`
`2. The inverter according to claim 1, wherein
`
`the high frequency switching control circuit
`
`comprises a controller and a sensing circuit.
`
`2. The inverter according to claim 1,
`wherein the high frequency switching
`control circuit comprises a controller and
`a sensing circuit.
`
`3. The inverter according to claim 2, wherein
`
`the controller comprises a current-mode
`
`PWM controller.
`
`3. The inverter according to claim 2,
`wherein the controller comprises a
`current-mode PWM controller.
`
`4. The inverter according to claim 2, wherein
`
`the sensing circuit comprises at least one of a
`
`peak current sense and an output voltage
`sense.
`
`4. The inverter according to claim 2,
`wherein the sensing circuit comprisesat
`least one of a peak current sense and an
`output voltage sense.
`
`5. The inverter according to claim 1, wherein
`
`the plurality of switches for the synchronous-
`
`buck circuit comprise field effect transistors
`
`(FETs).
`
`5. The inverter according to claim 1,
`wherein the plurality of switches for the
`synchronous-buckcircuit comprisefield
`effect transistors (FETs).
`
`6. The inverter according to claim 1, wherein
`
`the high frequency switching control circuit is
`
`configured to provide a low frequency sine
`
`waveto effect switching control on the
`
`synchronous-buck circuit.
`
`6. The inverter according to claim 1,
`wherein the high frequency switching
`control circuit is configured to provide a
`low frequency sine waveto effect
`switching control on the synchronous-
`buck circuit.
`
`7. The inverter according to claim 1, wherein
`
`the synchronous buck circuit comprises a
`
`plurality of drive circuits, each operatively
`
`coupled to a respective one of the plurality of
`
`switches.
`
`7. The inverter according to claim 1,
`wherein the synchronous buckcircuit
`comprises a plurality of drive circuits,
`each operatively coupled to a respective
`one of the plurality of switches.
`
`8. The inverter according to claim 1, wherein
`
`one of the plurality of switches for the
`
`synchronous-buck circuit is configured to be
`
`8. The inverter according to claim 1,
`wherein one ofthe plurality of switches
`for the synchronous-buckcircuit is
`
`

`

`Application/Control Number: 17/744,895
`Art Unit: 2849
`
`
`Page 5
`
`active on a high frequency PWM for a
`
`positive half wave of the high frequency
`
`switching control circuit, and another of the
`
`plurality of switches for the synchronous-
`
`buck circuit is active on a high frequency
`
`PWM complementfor the positive half wave
`
`of the high frequency switching control
`
`circuit.
`
`9. The inverter according to claim 1, wherein
`
`one of the plurality of switches for the
`
`synchronous-buck circuit is configured to be
`
`active on a high frequency PWM for a
`
`negative half wave of the high frequency
`
`switching control circuit, and another of the
`
`plurality of switches for the synchronous-
`
`buck circuit is active on a high frequency
`
`PWM complementfor the negative half wave
`
`of the high frequency switching control
`
`circuit.
`
`10. The inverter according to claim 1, further
`
`comprising a dither circuit operatively
`
`coupled to the high frequency switching
`
`control circuit, wherein the dither circuit is
`
`configured to cause a frequency changein
`
`the switching control circuit.
`
`11. The inverter according to claim 10,
`
`wherein the dithering circuit is configured to
`
`apply a waveform to the high frequency
`
`switching control circuit to cause the
`
`frequency change.
`
`12. The inverter according to claim 11,
`
`wherein the dithering circuit is configured to
`
`apply a triangular waveform to the high
`
`frequency switching control circuit to cause
`
`the frequency change.
`
`configured to be active on a high
`frequency PWM for a positive half wave
`of the high frequency switching control
`circuit, and another of the plurality of
`switches for the synchronous-buckcircuit
`is active on a high frequency PWM
`complement for the positive half wave of
`the high frequency switching control
`circuit.
`
`9. The inverter according to claim 1,
`wherein one ofthe plurality of switches
`for the synchronous-buckcircuit is
`configured to be active on a high
`frequency PWM for a negative half wave
`of the high frequency switching control
`circuit, and another of the plurality of
`switches for the synchronous-buckcircuit
`is active on a high frequency PWM
`complement for the negative half waveof
`the high frequency switching control
`circuit.
`
`10. The inverter according to claim 1,
`further comprising a dither circuit
`operatively coupled to the high frequency
`switching control circuit, wherein the
`dither circuit is configured to cause a
`frequency change in the switching control
`circuit.
`
`11. The inverter according to claim 10,
`wherein the dithering circuit is configured
`to apply a waveform to the high frequency
`switching control circuit to cause the
`frequency change.
`
`12. The inverter according to claim 11,
`wherein the dithering circuit is configured
`to apply a triangular waveform to the high
`
`

`

`Application/Control Number: 17/744,895
`Art Unit: 2849
`
`
`Page 6
`
`13. The inverter according to claim 10,
`
`wherein the dither circuit is configured to
`
`cause the frequency changein the switching
`
`control circuit by reducing a switching
`
`frequency at a zero crossing.
`
`14. The inverter according to claim 1,
`
`wherein each of the plurality of switches for
`
`the synchronous buck circuit comprises one
`
`of Silicon Carbide switches and Gallium
`
`Nitride switches.
`
`15. The inverter of claim 1, wherein the
`
`output capacitor circuit comprises a
`
`discharge capacitor operatively coupled to
`
`the oscillated output, the low frequency
`
`switching circuit and the synchronous buck
`
`circuit.
`
`16. The inverter according to claim 1,
`
`wherein the high frequency switching control
`
`circuit is configured to provide a high
`
`frequency sine waveto effect switching
`
`control on the synchronous-buck circuit.
`
`17. The inverter according to claim 15,
`
`wherein the synchronous buck circuit
`
`comprises a plurality of drive circuits.
`
`18. The inverter according to claim 1,
`
`wherein the low frequency switchingcircuit
`
`comprises a plurality of drive circuits.
`
`19. The inverter according to claim 1,
`
`wherein one aspect of the low frequency
`
`switching circuit is configured to be always
`
`on for one half wave of the high frequency
`
`switching control circuit, and another aspect
`
`of the low frequency switching circuit is
`
`frequency switching control circuit to
`cause the frequency change.
`
`13. The inverter according to claim 10,
`wherein the dither circuit is configured to
`cause the frequency change in the
`switching control circuit by reducing a
`switching frequency at a zero crossing.
`
`14. The inverter according to claim 1,
`wherein each ofthe plurality of switches
`for the synchronous buckcircuit
`comprises one of Silicon Carbide
`switches and Gallium Nitride switches.
`
`15. The inverter of claim 1, wherein the
`output capacitor circuit comprises a
`discharge capacitor operatively coupled
`to the oscillated output, the low frequency
`switching circuit and the synchronous
`buck circuit.
`
`16. The inverter according to claim 1,
`wherein the high frequency switching
`control circuit is configured to provide a
`high frequency sine waveto effect
`switching control on the synchronous-
`buck circuit.
`
`7. The inverter according to claim 15,
`wherein the synchronous buckcircuit
`comprisesa plurality of drive circuits.
`
`18. The inverter according to claim 1,
`wherein the low frequency switching
`circuit comprises a plurality of drive
`circuits.
`
`19. The inverter according to claim 1,
`wherein one aspectof the low frequency
`switching circuit is configured to be
`always on for one half wave of the high
`frequency switching control circuit, and
`another aspectof the low frequenc
`
`

`

`Application/Control Number: 17/744,895
`Art Unit: 2849
`
`
`Page 7
`
`frequency switching circuit.
`
`half wave of the low frequency switching
`circuit.
`
`
`
`The nonstatutory double patenting rejection is based on a judicially created doctrine
`
`grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or
`
`improper timewise extension of the “right to exclude” granted by a patent and to prevent
`
`possible harassment by multiple assignees. A nonstatutory double patenting rejection is
`
`appropriate where the conflicting claims are not identical, but at least one examined
`
`application claim is not patentably distinct from the reference claim(s) because the examined
`
`application claim is either anticipated by, or would have been obvious over, the reference
`
`claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman,
`
`11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed.
`
`Cir. 1985); In re Van Ornum,686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d
`
`438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
`
`A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be
`
`used to overcome an actual or provisional rejection based on nonstatutory double patenting
`
`

`

`Application/Control Number: 17/744,895
`Art Unit: 2849
`
`Page 8
`
`provided the reference application or patent either is shown to be commonly owned with the
`
`examined application, or claims an invention made as a result of activities undertaken within
`
`the scope of a joint research agreement. See MPEP § 717.02 for applications subject to
`
`examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159.
`
`See MPEP § 2146 etseq. for applications not subject to examination under the first inventor to
`
`file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR
`
`1.321(b).
`
`The USPTO Internet website contains terminal disclaimer forms which may be used.
`
`Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which
`
`the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or
`
`PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may befilled out completely
`
`online using web-screens. An eTerminal Disclaimer that meetsall requirements is auto-
`
`processed and approved immediately upon submission. For more information about eTerminal
`
`Disclaimers, refer to ¥
`
`Claims 1-8,9, 10-14, 15-19 (current application ‘895)are rejected on the ground of non-
`
`statutory double patenting as being unpatentable over claims 1,2,3,4,5,6,7 and 9,10, 13-17,
`
`18, 19 and 20 of U.S. Patent No. 9,660, 580. Although the claims at issue are not identical, they
`
`are not patentably distinct from each other because:
`
`The claim(s)( INDEP cls 1) being presented nowin the application is merely broader in scope
`
`with regards the power inverter/method (in patent cls(1,18 and 20)of operation having an
`
`input for DC and out for AC; the main elements such as high frequency switching control circuit,
`
`

`

`Application/Control Number: 17/744,895
`Art Unit: 2849
`
`Page 9
`
`synchronous buck circuit and low frequency switching circuit with plurality of switches to allow
`
`for zero voltage switching and zero current switching where a discharge capacitor is
`
`implemented is provided for in both sets of claims. The dependent claims 2-19 of the
`
`application track the dependent claims 2-7, 9,10, 13-17 and 19.
`
`17/744,895
`
`US Pat 9,660, 580
`
`1, wherein the high frequency switching
`
`1. A powerinverter, comprising: an input
`for receiving DC power; an output for
`providing AC power to a load; a high
`frequency switching control circuit,
`operatively coupledto the input; a
`synchronous-buckcircuit, operatively
`coupled to the high frequency switching
`control circuit and the output, the
`synchronous buckcircuit comprising a
`plurality of switches and configured to
`invert every half cycle of the signal
`provided by the high frequency switching
`control circuit; a low frequency switching
`circuit, operatively coupled to the
`synchronous buckcircuit and the output,
`the low frequency switching circuit
`comprising a plurality of switches and
`configured to operate as at least one of a
`zero voltage switching and a zero current
`switching drive; a capacitive circuit
`comprising a discharge capacitor, the
`capacitive circuit operatively coupled to
`the output, the low frequency switching
`circuit and the synchronous buckcircuit,
`the capacitive circuit being configured to
`discharge the discharge capacitor to zero
`on at least one zero crossing of low
`frequency switching circuit.
`
`2. The power inverter according to claim
`
`1. An inverter, comprising: a high frequency
`
`switching control circuit operatively coupled
`
`to a DC power input; a synchronous-buck
`
`circuit, operatively coupled to the high
`
`frequency switching control circuit and
`
`comprising a plurality of switches controlled
`
`by the high frequency switching control
`
`circuit to cyclically invert the DC power input;
`
`and a low frequency switchingcircuit for
`
`providing an oscillated output and
`
`operatively coupled to the synchronous buck
`
`circuit to provide zero voltage switching and
`
`zero current switching by driving an output
`
`capacitor circuit to discharge on each zero
`
`crossing of the low frequency switching
`
`circuit.
`
`2. The inverter according to claim 1, wherein
`
`the high frequency switching control circuit
`
`comprises a controller and a sensing circuit.
`
`

`

`Application/Control Number: 17/744,895
`Art Unit: 2849
`
`
`Page 10
`
`control circuit comprises a controller and
`a sensing circuit.
`
`3. The inverter according to claim 2, wherein
`
`the controller comprises a current-mode
`
`PWM controller.
`
`3. The power inverter according to claim
`2, wherein the controller comprises a
`current-mode PWM cortroller.
`
`4. The inverter according to claim 2, wherein
`
`the sensing circuit comprises at least one of a
`
`peak current sense and an output voltage
`sense.
`
`5. The inverter according to claim 1, wherein
`
`the plurality of switches for the synchronous-
`
`buck circuit comprise field effect transistors
`
`(FETs).
`
`6. The inverter according to claim 1, wherein
`
`the high frequency switching control circuit is
`
`configured to provide a low frequency sine
`
`waveto effect switching control on the
`
`synchronous-buck circuit.
`
`7. The inverter according to claim 1, wherein
`
`the synchronous buck circuit comprises a
`
`plurality of drive circuits, each operatively
`
`coupled to a respective one of the plurality of
`
`switches.
`
`8. The inverter according to claim 1, wherein
`
`one of the plurality of switches for the
`
`synchronous-buck circuit is configured to be
`
`active on a high frequency PWM for a
`
`positive half wave of the high frequency
`
`switching control circuit, and another of the
`
`plurality of switches for the synchronous-
`
`buck circuit is active on a high frequency
`
`4. The power inverter according to claim
`2, wherein the sensing circuit comprises
`at least one of a peak current sense and
`an output voltage sense.
`
`5. The power inverter according to claim
`1, wherein the plurality of switches for the
`synchronous-buckcircuit and the low
`frequency switching circuit comprise field
`effect transistors (FETs).
`
`6. The power inverter according to claim
`1, wherein the high frequency switching
`control circuit is configured to provide a
`low frequency sine waveto effect
`switching control on the synchronous-
`buck circuit.
`
`7. The power inverter according to claim
`1, wherein the synchronous buckcircuit
`comprises a plurality of drive circuits,
`each operatively coupled to a respective
`one of the plurality of switches.
`
`8. The power inverter according to claim
`1, wherein the low frequency switching
`circuit comprises a plurality of drive
`circuits, each operatively coupled to a
`respective one of the plurality of switches.
`
`

`

`Application/Control Number: 17/744,895
`Art Unit: 2849
`
`
`Page 11
`
`PWM complementfor the positive half wave
`
`of the high frequency switching control
`
`circuit.
`
`9. The inverter according to claim 1, wherein
`
`one of the plurality of switches for the
`
`synchronous-buck circuit is configured to be
`
`active on a high frequency PWM for a
`
`negative half wave of the high frequency
`
`switching control circuit, and another of the
`
`plurality of switches for the synchronous-
`
`buck circuit is active on a high frequency
`
`PWM complementfor the negative half wave
`
`of the high frequency switching control
`
`circuit.
`
`10. The inverter according to claim 1, further
`
`comprising a dither circuit operatively
`
`coupled to the high frequency switching
`
`control circuit, wherein the dither circuit is
`
`configured to cause a frequency changein
`
`the switching control circuit.
`
`11. The inverter according to claim 10,
`
`wherein the dithering circuit is configured to
`
`apply a waveform to the high frequency
`
`switching control circuit to cause the
`
`frequency change.
`
`12. The inverter according to claim 11,
`
`wherein the dithering circuit is configured to
`
`9. The power inverter according to claim
`1, wherein one of the plurality of switches
`for the synchronous-buckcircuit is
`configured to be active on a high
`frequency PWM for a positive half wave
`of the high frequency switching control
`circuit, as another of the plurality of
`switches for the synchronous-buckcircuit
`is active on a high frequency PWM
`complimentfor the positive half wave of
`the high frequency switching control
`circuit.
`
`10. The power inverter according to claim
`1, wherein one of the plurality of switches
`for the synchronous-buckcircuit is
`configured to be active on a high
`frequency PWM for a negative half wave
`of the high frequency switching control
`circuit, as another of the plurality of
`switches for the synchronous-buckcircuit
`is active on a high frequency PWM
`complimentfor the negative half wave of
`the high frequency switching control
`circuit.
`
`11. The power inverter according to claim
`1, wherein one of the plurality of switches
`for the low frequency switching circuit is
`configured to be on for a positive half
`waveof the high frequency switching
`control circuit, as another of the plurality
`of switches for the low frequency
`switching circuit is off for the positive half
`waveof the low frequency switching
`circuit.
`
`

`

`Application/Control Number: 17/744,895
`Art Unit: 2849
`
`
`Page 12
`
`apply a triangular waveform to the high
`
`frequency switching control circuit to cause
`
`the frequency change.
`
`13. The inverter according to claim 10,
`
`wherein the dither circuit is configured to
`
`cause the frequency changein the switching
`
`control circuit by reducing a switching
`
`frequency at a zero crossing.
`
`14. The inverter according to claim 1,
`
`wherein each of the plurality of switches for
`
`the synchronous buck circuit comprises one
`
`of Silicon Carbide switches and Gallium
`
`Nitride switches.
`
`15. The inverter of claim 1, wherein the
`
`output capacitor circuit comprises a
`
`discharge capacitor operatively coupled to
`
`the oscillated output, the low frequency
`
`switching circuit and the synchronous buck
`
`circuit.
`
`16. The inverter according to claim 1,
`
`wherein the high frequency switching control
`
`circuit is configured to provide a high
`
`frequency sine waveto effect switching
`
`control on the synchronous-buck circuit.
`
`17. The inverter according to claim 15,
`
`wherein the synchronous buck circuit
`
`comprises a plurality of drive circuits.
`
`12. The power inverter according to claim
`1, wherein one of the plurality of switches
`for the low frequency switching circuit is
`configured to be on for a negative half
`waveof the high frequency switching
`control circuit, as another of the plurality
`of switches for the low frequency
`switching circuit is off for the negative half
`waveof the low frequency switching
`circuit.
`
`13. The power inverter according to claim
`1, further comprising a dither circuit
`operatively coupled to the high frequency
`switching control circuit, wherein the
`dither circuit is configured to cause a
`frequency change in the switching control
`circuit.
`
`14. The power inverter according to claim
`13, wherein the dithering circuit is
`configured to apply a waveform to the
`high frequency switching control circuit to
`cause the frequency change.
`
`15. The power inverter according to claim
`14, wherein the dithering circuit is
`configured to apply a triangular waveform
`to the high frequency switching control
`circuit to cause the frequency change.
`
`16. The power inverter according to claim
`13, wherein the dither circuit is configured
`to cause the frequency change in the
`switching control circuit by reducing a
`switching frequencyat a zero crossing.
`
`

`

`Application/Control Number: 17/744,895
`Art Unit: 2849
`
`
`Page 13
`
`18. The inverter according to claim 1,
`
`wherein the low frequency switchingcircuit
`
`comprises a plurality of drive circuits.
`
`19. The inverter according to claim 1,
`
`wherein one aspect of the low frequency
`
`switching circuit is configured to be always
`
`on for one half wave of the high frequency
`
`switching control circuit, and another aspect
`
`of the low frequency switching circuit is
`
`always off for the one half wave of the low
`
`frequency switching circuit.
`
`17. The power inverter according to claim
`1, wherein each of the plurality of
`switches for the synchronous buckcircuit
`comprisesone of Silicon Carbide
`switches and Gallium Nitride switches.
`
`18. A method for operating a power
`inverter, comprising: receiving DC power
`at an input; providing a signal from a high
`frequency switching control circuit,
`operatively coupled to the input; inverting
`every half cycle of the signal provided by
`the high frequency switching control
`circuit via a synchronous-buckcircuit
`comprising a plurality of switches;
`performing at least one of zero voltage
`switching and zero current switching viaa
`low frequency switching circuit comprising
`a plurality of switches and operatively
`coupled to the synchronous buckcircuit;
`and discharging a discharge capacitor,
`operatively coupled to an output for
`providing AC power to a load, to zero on
`at least one zero crossing of low
`frequency switching circuit.
`
`19. The method of claim 18, further
`comprising dithering, by a dithering
`circuit, the signal provided by the high
`frequency switching control circuit to
`reduce a switching frequencyon the at
`least one frequencycrossing.
`
`20. A power device, comprising: an input
`for receiving electrical power; an output
`for providing electrical power to a load; a
`high frequency switching control circuit,
`operatively coupledto the input; a
`synchronous-buckcircuit, operatively
`coupled to the high frequency switching
`control circuit and the output, the
`synchronous buckcircuit comprising a
`plurality of switches and configured to
`invert on half-cycles of the signal
`provided by the high frequency switching
`control circuit; a low frequency switching
`
`

`

`Application/Control Number: 17/744,895
`Art Unit: 2849
`
`
`Page 14
`
`circuit, operatively coupled to the
`synchronous buckcircuit and the output,
`the low frequency switching circuit
`comprising a plurality of switches and
`configured to operate as at least one of a
`zero voltage switching and a zero current
`switching drive; a capacitive circuit
`comprising a discharge capacitor, the
`capacitive circuit operatively coupled to
`the output, the low frequency switching
`circuit and the synchronous buckcircuit,
`the capacitive circuit being configured to
`discharge the discharge capacitor to zero
`on at least some zero crossings of low
`frequency switching circuit.
`
`
`
`The DC input and AC outputis a typical application for these inverters and thus a simple matter
`
`of design consideration based on input and output loading requirements.
`
`In light of the above it would have been obvious to one of ordinary skill in the art before the
`
`effective filing date of the claimed invention to have recognized that the claims now presented
`
`in the application are part of the claims patented as noted above and are thus a simple matter
`
`of design consideration based on input and output loading requirements for DC input and AC
`
`output.
`
`Claims 1-15, 17-19 (current application ‘895)are rejected on the ground of non-statutory
`
`double patenting as being unpatentable over claims 1-16, 18-20 of U.S. Patent No. 10,840,824.
`
`

`

`Application/Control Number: 17/744,895
`Art Unit: 2849
`
`Page 15
`
`Although the claims at issue are not identical, they are not patentably distinct from each other
`
`because the claims are merely broader in scope with regards explicitly describing the DC input
`
`and AC output loading.
`
`The claim(s)( INDEP cls 1) being presented now in the application is merely broader in scope
`
`with regards the power inverter (in patent cls(1 and 15) having an input for DC and output for
`
`AC; the main elements such as high frequency switching control circuit, synchronous buck
`
`circuit and low frequency switching circuit with plurality of switches to allow for zero volt