ATTY. DKT. 63219-JBL-0096-US-D
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`SYNCHRONOUS BUCK INVERTER
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`RELATED APPLICATIONS
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`[0001]
`
`This is a Continuation Application of U.S. Application No. 17/069,459,
`
`filed October 13, 2020, entitled: “Synchronous Buck Inverter,” which is a Continuation
`
`Application of U.S. Application No. 15/724,839, filed October 4, 2017, entitled:
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`“Synchronous Buck Inverter,” which is a Continuation Application of U.S. Application
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`No. 15/251,487, filed August 30, 2016, entitled: “Wien Bridge Oscillator,” which is a
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`Continuation Application of U.S. Application No. 14/675,073, filed March 31, 2015,
`
`entitled: “Wien Bridge Oscillator,” which claimspriority to U.S. Provisional Patent
`
`Application No. 62/047443, titled “Synchronous Buck Inverter,” filed September8, 2014,
`
`the contents of which are incorporated by reference herein in their respective entireties
`
`herein.
`
`FIELD OF THE DISCLOSURE
`
`[0002]
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`The present disclosure is directed to oscillators and power conversion.
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`Morespecifically, the present disclosure relates to Wien bridge oscillators, such as for
`
`providing or simulating a pure sine waveforusein electrical applications, such as power
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`applications, and to multi-stage switching for inverters, such as mayutilize zero-cross
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`discharge to reduce distortion and increase efficiency.
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`BACKGROUND
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`[0003 ]
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`Certain power converters are configured to convert direct current (DC) to
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`alternating current (AC). Such DC-AC converters are commonlyreferred to as inverters.
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`Inverters have many industrial and commercial uses including, for example, converting DC
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`powerfrom a battery or photovoltaic source into AC power for a load. Inverters may also
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`be used to supply AC powerto an electric utility grid. A grid-tied inverter is a power
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`inverter that converts direct current (DC)electricity into alternating current (AC) with an
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`ability to synchronize to interface with a utility line. The applications for such an inverter
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`include converting DC sources, such as solar panels or small wind turbines, into AC for
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`tying with the grid. Photovoltaics (PV) in, for example, the aforementioned solar panels
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`generate electrical power by converting solar radiation into direct current electricity using
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`semiconductors that exhibit the photovoltaic effect.
`
`[0004]
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`Certain inverters are commonly configured to operate without a
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`transformer. Examples of such inverters are disclosed in Salmi,et al., “Transformerless
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`Microinverter for Photovoltaic Systems”, pp. 639-650, vol. 3, issue 4, Int’] Journal of
`
`Energy and Environment (2012); Reddyet al., “Analysis and Modeling of Transformerless
`
`Photovoltaic Inverter Systems”, pp. 2932-2938, vol. 3, issue 5, Int’] Journal of Modern
`
`Engineering Research (2013); and Dreheret al., “Comparison of H-Bridge Single-Phase
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`Transformerless PV String Inverters”, 10th IEEE/IASInt’! Conference on Industry
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`Applications, pp.1-8 (Nov. 2012).
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`[0005]
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`Photovoltaic (PV) power supplied to a utility grid is increasing in popularity
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`as the world’s power demandsare increasing. Solid-state inverters have been shownto be
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`an important technology for coupling PV systemsinto the grid. Integration of PV power
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`generation systems in the grid plays an important role in supplying electric power in an
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`environmentally-friendly manner. A commonly-configured grid-connected PV system
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`comprises of a PV panel, and a DC/AC Inverter that is operatively connected to the grid.
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`This configuration is used for power generation in places or sites accessed bythe electric
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`utility grid. Depending on the application and requirements, a PV system can either be a
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`stand-alone or hybrid system. Generally the PV system comprises of a PV generator
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`whichis a set of series-parallel electrically interconnected solar panels. PV panels are
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`commonly rated in terms of a nominal peak powerof the panelat standard test conditions
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`(STC). A PV generator providesthe total installed power, which is the sum of nominal
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`peak powerof each solar panel present in the PV installation. This PV generatoris
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`connected to an inverter which is, in turn, connected to an AC/DC load and/orgrid.
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`[0006]
`
`Inverters are important components to grid-connected PV systems andtheir
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`major role is to convert DC powerinto AC power. Furthermore, inverter interfacing PV
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`module(s) with the grid ensures that the PV module(s) is operated at the maximum power
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`point (MPPT). Based on the photovoltaic arrays’ output voltage, output power level and
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`applications, the photovoltaic grid-connected system may adopt different topologies. The
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`grid-connected inverter may be designed for peak power and mayobey conditionsrelated
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`to issues like power quality, detection of islanding operation, grounding, MPPTand long-
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`life. Inverter maximum poweris typically referred to the total installed power of the PV
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`ATTY. DKT. 63219-JBL-0096-US-D
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`generator, and should optimize the energy injected to grid. Inverter PV topologies may
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`include centralized inverters, string inverters, multi-string inverter and moduleinverters.
`
`[0007]
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`Although the foregoing discussion focuses particularly on PV systems,
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`those skilled in the art will appreciate that issues that arise in PV systems similarly arise in
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`other contexts that require power conversion/inversion, oscillation, and the like. Such
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`contexts include, but are not limited to, sine wave generating inverters, micro-inverters,
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`powersupplies, and powerdistribution systems.
`
`[0008]
`
`By way of example, conventional oscillator circuits are designed so that
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`they will start oscillating ("start up") and that their respective amplitude will be controlled.
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`For a linear circuit to oscillate, it must meet the “Barkhausen conditions,” that is, the loop
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`gain must be one and the phase aroundthe loop must be an integer multiple of 360
`
`degrees. In practice, the loop gain isinitially larger than unity. Random noiseis present in
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`all circuits, and some of that noise will be near the desired frequency. A loop gain greater
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`than one allows the amplitude of frequency to increase exponentially each time around the
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`loop. With a loop gain greater than one, the oscillator will start. However, with a loop
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`gain of greater than one, significant harmonic distortion is introduced, and the frequency
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`stability of the oscillator may be affected.
`
`[0009]
`
`A Wienbridge oscillator is a type of electronic oscillator that generates sine
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`waves undera large range of frequencies. The Wien bridge oscillator is typically based on
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`a bridge circuit comprising comprises four resistors and two capacitors (see FIG. 1). In
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`use, the oscillator can operate as a positive gain amplifier combined with a bandpass filter
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`ATTY. DKT. 63219-JBL-0096-US-D
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`that provides positive feedback. In certain applications, such as powerapplications, Wien
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`bridge oscillators may be used as inputs for circuit control and/or voltage reference(e.g.,
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`for power inverters). However, the quality of the sine wave produced by conventional
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`Wien bridgeoscillators is often subject to noise and distortion, and is not able to
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`effectively simulate or approximate a true (or “pure’’) sine wave.
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`SUMMARY
`
`[0010]
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`Accordingly, an improved inverter topologyis disclosed using high
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`frequency switching control to generate a low frequency sine wave. The main switching
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`may berealized using a synchronous-buck topology that is configured to invert every half
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`cycle of a lower frequency. The inverting process maycreate a positive and negative
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`transition true sine wave. The low frequency switching stage may be configured to operate
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`as a true zero voltage switching (ZVS) and zero current switching (ZCS) drive.
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`[0011]
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`The disclosed inverter may be further configured with an output capacitor,
`
`wherein the charge on the output capacitor may be discharged to zero upon every zero
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`crossing of the low frequency switching stage. The benefit of this topology, as compared
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`to a traditional synchronous buckinverter, is that the discharge of energy from the output
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`storage capacitor every half cycle creates very low distortion. That is, during this
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`discharge of energy, the zero crossing distortion in the low frequency sine waveis greatly
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`reduced.
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`[0012]
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`Comparisons will be made throughoutto a full-bridge topology, currently
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`deployed in a majority of grid-tied inverters presently, to the presently disclosed exemplary
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`embodiments to demonstrate advantageous improvements in efficiency, load variation and
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`total harmonic distortion.
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`[0013]
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`Further, in someillustrative embodiments, an oscillator circuit is disclosed,
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`comprising a Wien bridge oscillator circuit, a full-waverectifier circuit, coupled to an
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`output of the Wien bridge oscillator circuit, an integrator circuit, coupled to an output of
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`the full-waverectifier circuit, and a multiplier circuit, comprising a first input coupled to
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`the output of the Wien bridge oscillator circuit, and a second input, coupled to an output of
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`the integrator, the multiple signal configured to provide a signal to an input of the Wien
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`bridge oscillator circuit.
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`[0014]
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`In someillustrative embodiments, the oscillator circuit may further
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`comprise a RC circuit, coupled between the output of the full-waverectifier circuit and the
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`integrator circuit. In someillustrative embodiments, the multiplier circuit comprises an
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`XY multiplier, and the XY multiplier is coupled to an inverting amplifier input of the Wien
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`bridge oscillator circuit. Additionally, in some illustrative embodiments, the multiplier
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`circuit is configured to execute a transfer function on voltage received at the first input and
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`the second input, while the full waverectifier is configured to execute a different transfer
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`function on the voltage received at an input.
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`[0015]
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`In someillustrative embodiments, the multiplier circuit may be configured
`
`to dynamically control gain in the Wien bridgeoscillator circuit. An output of the
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`integrator circuit is coupled to a synchronous buck circuit. The integrator circuit may be
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`configured to provide a sinusoidal reference signal to the synchronous buckcircuit.
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`BRIEF DESCRIPTION OF THE FIGURES
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`[0016]
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`The present disclosure will become more fully understood from the detailed
`
`description given herein below and the accompanying drawings whichare given by way of
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`illustration only, and which thus do notlimit the present disclosure, and wherein:
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`[0017]
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`FIG. 1A illustrates an exemplary full bridge inverter topology that is known
`
`in the art;
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`[0018]
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`FIG. 1B illustrates a switching sequence for switches S1-S4 of FIG. 1A
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`undera positive half wave and negative half wave condition;
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`[0019]
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`FIGs. 2A-2Eillustrate waveforms exemplifying typical operational
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`conditions for the example of FIG. 1A;
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`[0020]
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`FIG. 3A illustrates an exemplary synchronous buckinverter topology under
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`one exemplary embodiment, where the inverter comprises a high-frequency switching
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`portion, a synchronous buck portion and a low frequency switching stage coupled to a
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`discharge capacitor configured to be coupled to a load;
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`[0021]
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`FIG. 3B illustrates a switching sequence for switches A-D ofthe
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`embodiment of FIG. 3A under positive half wave and negative half wave conditions;
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`[0022]
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`FIG. 3C provides anotherillustration of a synchronous buck inverter under
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`another embodiment;
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`[0023]
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`FIG. 4 illustrates a switch sequence diagram that includes four switching
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`sections over the course of an exemplary sine wave for switches A-D of the embodiments
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`of FIG. 3A and 3C;
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`[0024]
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`FIGs. 4A-B illustrate an exemplary switching transitions of switches A-D of
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`the embodiment of FIG. 3A during a first switching section (at peak of positive sine wave)
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`of FIG. 4;
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`[0025]
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`FIG 4C schematically illustrates a synchronous current flow through a load
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`and a switching configuration for switches A-D for time period (a) of FIG. 4B under one
`
`exemplary embodiment;
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`[0026]
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`FIG 4D schematically illustrates a buck current flow through a load and a
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`switching configuration for switches A-D for time period (b) of FIG. 4B under one
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`exemplary embodiment;
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`[0027]
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`FIGs. 4E-F illustrate an exemplary switching transitions of switches A-D of
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`the embodimentof FIG. 3A during a second switching section (at positive-negative zero
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`crossing transition of sine wave) of FIG. 4;
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`[0028]
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`FIG 4G schematically illustrates a buck/synchronous current flow through a
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`load and a switching configuration for switches A-D for time period (a) of FIG. 4F under
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`one exemplary embodiment;
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`[0029]
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`FIG 4H schematically illustrates a synchronous/buckcurrent flow through a
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`load and a switching configuration for switches A-D for time period (b) of FIG. 4F under
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`one exemplary embodiment;
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`[0030]
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`FIGs. 4]-J illustrate an exemplary switching transitions of switches A-D of
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`the embodimentof FIG. 3A during a third switching section (at peak negative of sine
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`wave) of FIG. 4;
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`[0031]
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`FIG 4K schematically illustrates a synchronous current flow through a load
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`and a switching configuration for switches A-D for time period (a) of FIG. 4J under one
`
`exemplary embodiment;
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`[0032]
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`FIG 4L schematically illustrates a buck current flow through a load and a
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`switching configuration for switches A-D for time period (b) of FIG. 4J under one
`
`exemplary embodiment;
`
`[0033]
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`FIGs. 4M-Nillustrate an exemplary switching transitions of switches A-D
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`of the embodimentof FIG. 3A during a fourth switching section (at negative-positive zero
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`crossing transition of sine wave) of FIG. 4;
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`[0034]
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`FIG 40 schematically illustrates a synchronous/buck current flow through a
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`load and a switching configuration for switches A-D for time period (a) of FIG. 4N under
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`one exemplary embodiment;
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`[0035]
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`FIG 4P schematically illustrates a buck/synchronous current flow through a
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`load and a switching configuration for switches A-D for time period (b) of FIG. 4N under
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`one exemplary embodiment;
`
`[0036]
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`FIGs. 5A-B illustrate an exemplary gate drive waveform and current
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`waveform for a positive signal condition for switches A and B forthe first switching
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`section illustrated in the exemplary embodiments of FIG. 4A-D above;
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`[0037]
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`FIGs. 6A-B illustrate an exemplary gate drive waveform and current
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`waveform for a zero crossing condition for switches A and B for the second switching
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`section illustrated in the exemplary embodiments of FIG. 4E-G above;
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`[0038]
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`FIGs. 7A-B illustrate an exemplary gate drive waveform and current
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`waveform for a negative signal condition for switches A and B for the third switching
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`section illustrated in the exemplary embodiments of FIG. 4]-L above;
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`[0039]
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`FIGs. 8A-B illustrate an exemplary gate drive waveform and current
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`waveform for a zero crossing signal condition for switches A and B for the fourth
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`switching section illustrated in the exemplary embodiments of FIG. 4M-P above;
`
`[0040]
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`FIGs. 9A-E illustrate waveforms exemplifying operational conditions for
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`the embodiment of FIG. 3A;
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`[0041]
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`FIG. 10A illustrates an exemplary waveform for the synchronous-buck
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`inverter of FIG. 3A and FIG. 4 showing improved voltage and current distortion;
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`10
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`[0042]
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`FIG. 10B illustrates an exemplary gate drive waveform for switches C and
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`D for the synchronous-buckinverter of FIG. 3A and FIG. 4;
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`[0043]
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`FIG. 11 illustrates a conventional Wien bridge oscillator configured to
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`provide a sine waveoutput;
`
`[0044]
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`FIG. 12 illustrates a RC phase shift network model of the Wien bridge
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`oscillator of FIG. 11;
`
`[0045]
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`FIG. 13A illustrates a simulated waveform for a oscillator voltage gain for
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`the Wien bridge oscillator of FIG. 11;
`
`[0046]
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`FIG. 13B illustrates a simulated waveform for a oscillator phase shift for the
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`Wien bridgeoscillator of FIG. 11;
`
`[0047]
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`FIG. 14 illustrates a detailed configuration for a conventional Wien bridge
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`oscillator for providing a sine wave output;
`
`[0048]
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`FIG. 15 shows a simulated output waveform for the Wien bridge circuit of
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`FIGs. 14 or FIG. 11, illustrating an at least partially saturated state;
`
`[0049]
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`FIG. 16 shows a magnification of the simulated output waveform of FIG.
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`15 for the Wien bridge circuit of FIGs. 14 or FIG. 11, illustrating an at least partially
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`saturated state;
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`11
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`[0050]
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`FIG. 17 shows a Wienbridge oscillator circuit under an exemplary
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`embodiment comprising a Wien bridge oscillator, an XY multiplier circuit, a full-wave
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`rectifier circuit, an R-C filter, and an integrator;
`
`[0051]
`
`FIG. 18 shows anillustrative full-waverectifier circuit for use in the
`
`embodiment of FIG. 17 under an embodiment;
`
`[0052]
`
`FIG. 19 shows a simulated output waveform for the Wien bridge circuit of
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`FIG. 18, illustrating a reduction or elimination of saturation under an embodiment;
`
`[0053]
`
`FIG. 20 shows a simulated output waveform of the Wien bridge circuit of
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`FIG. 18, illustrating the output voltage of the full-wave rectifier together with a sinusoidal
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`output voltage of the Wien bridge rectifier under an embodiment;
`
`[0054]
`
`FIG. 21 shows a simulated output waveform of the Wien bridge circuit of
`
`FIG. 18, illustrating the output voltage of the full-wave rectifier together with reference
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`voltage of an averaged full-wave rectifier and averaged value of the full-wave output
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`voltage under an embodiment;
`
`[0055]
`
`FIG, 22A illustrates an exemplary synchronous buck inverter topology
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`underoneillustrative embodiment, where the inverter comprises a high-frequency
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`switching portion, a synchronous buck portion and a low frequency switching stage
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`coupled to a discharge capacitor configured to be coupled to a load, where the synchronous
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`buck inverter topology is configured to receive a voltage reference input from the Wien
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`bridge oscillator of FIG. 17;
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`12
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`[0056]
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`FIG. 22Billustrates a switching sequence for switches A-D ofthe
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`embodimentof FIG. 12A underpositive half wave and negative half wave conditions;
`
`[0057]
`
`FIG. 22C provides anotherillustration of a synchronous buck inverter under
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`another embodiment where the synchronous buck inverter is configured to receive a
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`voltage reference input from the Wien bridge oscillator of FIG. 17;
`
`[0058]
`
`FIG. 23A shows a simplified circuit for operating synchronous high
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`frequency switches to cause current to flow across an inductor underanillustrative
`
`embodiment;
`
`[0059]
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`FIG. 23B illustrates a simulated waveform ofa rectified sinusoid produced
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`by the simplified circuit of FIG. 13A under an embodiment;
`
`[0060]
`
`FIG. 24A shows a simplified circuit comprising low frequency switches
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`addedto the circuit of FIG. 23A.
`
`[0061]
`
`FIG. 24B illustrates a simulated waveform of a rectified sinusoid in which a
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`portion of the rectified sinusoid is to be inverted using the simplified circuit of FIG. 24A;
`
`[0062]
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`FIG. 24C illustrates a simulated waveform of a rectified sinusoid in which a
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`portion of the rectified sinusoid is inverted using the simplified circuit of FIG. 24A.
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`13
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`DETAILED DESCRIPTION
`
`[0063]
`
`The figures and descriptions provided herein may have been simplified to
`
`illustrate aspects that are relevant for a clear understanding of the herein described devices,
`
`systems, and methods, while eliminating, for the purpose of clarity, other aspects that may
`
`be found in typical similar devices, systems, and methods. Those of ordinary skill may
`
`thus recognize that other elements and/or operations may be desirable and/or necessary to
`
`implement the devices, systems, and methods described herein. But because such elements
`
`and operations are knownin theart, and because they do notfacilitate a better
`
`understanding of the present disclosure, a discussion of such elements and operations may
`
`not be provided herein. However, the present disclosure is deemed to inherently include
`
`all such elements, variations, and modifications to the described aspects that would be
`
`knownto those of ordinary skill in the art.
`
`[0064]
`
`Exemplary embodiments are provided throughoutso that this disclosure is
`
`sufficiently thorough and fully conveys the scope of the disclosed embodiments to those
`
`whoareskilled in the art. Numerous specific details are set forth, such as examples of
`
`specific components, devices, and methods, to provide this thorough understanding of
`
`embodiments of the present disclosure. Nevertheless, it will be apparent to those skilled in
`
`the art that specific disclosed details need not be employed, and that exemplary
`
`embodiments may be embodiedin different forms. As such, the exemplary embodiments
`
`should not be construed to limit the scope of the disclosure. In some exemplary
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`14
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`embodiments, well-known processes, well-known device structures, and well-known
`
`technologies may not be described in detail.
`
`[0065]
`
`The terminology used herein is for the purpose of describing particular
`
`exemplary embodiments only and is not intended to be limiting. As used herein, the
`
`singular forms
`
`Woot
`"a",
`
`"an" and "the" may be intended to includethe plural formsas well,
`
`unless the context clearly indicates otherwise. The terms "comprises,"
`
`"comprising,"
`
`Won
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`"including," and "having," are inclusive and therefore specify the presence of stated
`
`features, integers, steps, operations, elements, and/or components, but do not preclude the
`
`presence or addition of one or more otherfeatures, integers, steps, operations, elements,
`
`components, and/or groups thereof. The steps, processes, and operations described herein
`
`are not to be construed as necessarily requiring their respective performancein the
`
`particular order discussed orillustrated, unless specifically identified as a preferred order
`
`of performance. It is also to be understood that additional or alternative steps may be
`
`employed.
`
`[0066]
`
`Woot
`Whenan elementor layer is referred to as being "on",
`
`"engaged to”,
`
`"connected to” or "coupled to" another elementor layer, it may be directly on, engaged,
`
`connected or coupled to the other elementor layer, or intervening elements or layers may
`
`be present. In contrast, when an elementis referred to as being "directly on,” "directly
`
`engaged to”, "directly connected to" or "directly coupled to” another elementor layer,
`
`there may be no intervening elements or layers present. Other words usedto describe the
`
`relationship between elements should be interpreted in a like fashion (e.g., "between"
`
`versus "directly between,"
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`"adjacent" versus "directly adjacent,” etc.). As used herein, the
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`Won
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`ATTY. DKT. 63219-JBL-0096-US-D
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`term "and/or" includes any and all combinations of one or more of the associated listed
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`items.
`
`[0067]
`
`Although the termsfirst, second, third, etc. may be used herein to describe
`
`various elements, components, regions, layers and/or sections, these elements,
`
`components, regions, layers and/or sections should not be limited by these terms. These
`
`terms may beonly usedto distinguish one element, component, region, layer or section
`
`from another element, component, region, layer or section. Terms suchas"first,"
`
`“second,” and other numerical terms when used herein do not imply a sequenceor order
`
`unless clearly indicated by the context. Thus, a first element, component, region, layer or
`
`section discussed below could be termed a second element, component, region, layer or
`
`section without departing from the teachings of the exemplary embodiments.
`
`[0068]
`
`Turning now to FIG. 1A, a conventional inverter is illustrated and will be
`
`used for reference for the embodiments discussed throughout, such as in connection with
`
`the discussion of FIGs. 3A-10B. It should be understood bythose skilled in the art that the
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`specific configuration in FIG. 1A is merely used forillustrative purposes and is not
`
`intended to limit the present disclosure.
`
`[0069]
`
`The inverter of FIG. 1A is configured as a full-bridge inverter topology and
`
`comprises of four switches, two output inductors and an output storage capacitor. In this
`
`case, L2 may be the same as L1 andthe total common-modevoltage Vem is ’Vpc.
`
`Conventionally, the full-bridge uses one of two control strategies. For the bipolar PWM
`
`control strategy, one group of diagonal switches operates at a switching frequency
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`complementary to the other group of switches. As a result, the inverter output voltage has
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`only two levels which results in high current ripple across the output inductors. An
`
`exemplary switching sequencefor the circuit of FIG. 1A is shown where, for a sine wave
`
`input, switches S; and S4 are closed, while switches S2 and S3 are open onthe positive half
`
`waveof the input. Conversely, switches S$; and S4 are open, while switches S2 and S3 are
`
`closed on the negative half wave of the input.
`
`[0070]
`
`The major drawback of employing the full-bridge with, for example, bipolar
`
`PWMisthe high powerlosses due to two factors. Thefirst factor is the internal reactive
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`powerflow inside the inverter, and the second is the double switching frequency required
`
`to obtain the same inductor current ripple frequency. The second control strategy that may
`
`be applied to the full-bridge of FIG. 1A is the unipolar PWM. In such modulation, the
`
`inverter output voltage has three levels, which decreases significantly the current ripple
`
`across the inductors. With this modulation, the inverter has high efficiency dueto the
`
`absenceof the internal reactive power flow. However, with this control strategy, the
`
`inverter generates high leakage currentlevel.
`
`[0071]
`
`Accordingly, other topologies have endeavored to combine the advantages
`
`of the bipolar PWM (low leakage current level) and those of the unipolar PWM (High
`
`efficiency, low current ripple and three level inverter output voltages). These endeavors
`
`have been undertaken by adding extra switchesto the full-bridge topology. These extra
`
`switches disconnect the PV array from the grid during the freewheeling periods.
`
`Nevertheless, these and like circuits such as thatillustrated in FIG. 1A carry excessive
`
`harmonic distortions in the signal, and thus operate at a reduced efficiency.
`
`17
`
`

`

`ATTY. DKT. 63219-JBL-0096-US-D
`
`[0072]
`
`FIG. 2A is an exemplary simulated waveform for the circuit of FIG. 1A,
`
`operating under a -0.7 power factor (PF) load, utilizing 100Q in series with a 26.54 uF
`
`capacitor. As can be determined from the voltage (V) and current (I) waveforms, voltage
`
`distortion is approximately 24%, while current distortion is approximately 34.1%. As will
`
`be appreciated by those skilled in the art, the distortion is particularly acute around the zero
`
`crossing phases. Asthe resistance is reduced to 20.63Q in series with a 130.3 UF
`
`capacitor, the total harmonic distortion increases to a point that it could not be measured,
`
`as illustrated in FIG. 2B.
`
`[0073]
`
`In FIG. 2C, utilizing a unity powerfactor load of 1kQ for the circuit of FIG.
`
`1A,the total harmonic distortion measured for the voltage (V) in the simulated waveform
`
`is 26.9%, and 25.1% for the current (I). Utilizing a unity power factor with a reduced load
`
`of 100Q for the circuit of FIG. 1A, the total harmonic distortion measured for the voltage
`
`(V) is 2.79%, and 3.41% for the current (1), with a total power of 585.6W asillustrated in
`
`the simulated waveform of FIG. 2D. In FIG. 2E, utilizing a unity powerfactor load of
`
`28.2Q at approximately 2kW,total harmonic distortion measured for the voltage (V) was
`
`1.52%, and 1.71% for the current (1), with an efficiency of 98.2%.
`
`[0074]
`
`Buck converters, and particularly synchronous buck converters, may
`
`advantageously be configured for inverter applications to provide less noisy and more
`
`efficient power output. The use of conventional buck converters for inverters is known in
`
`the art, and examples of such applications may be found in U.S. Pat. No. 8,488,350 to
`
`Sigamani, titled “DC-AC Inverters’, issued July 16, 2013, and U.S. Pat. No. 7,872,887 to
`
`Nishioet al., titled “DC-AC Inverter Powering a Single Phase Commercial Power
`
`18
`
`

`

`ATTY. DKT. 63219-JBL-0096-US-D
`
`System’, issued Jan. 18, 2011, both of which are incorporated by reference in their entirety
`
`herein. While the aforementioned configurations provide some improvement over
`
`conventional inverter topologies, further improvements mayberealized utilizing
`
`configurations disclosed herein.
`
`[0075]
`
`Turning now to FIG. 3A, synchronous buck inverter topology 300 is
`
`disclosed in an exemplary embodiment. Inverter 300 comprises a DC source 301 and a
`
`house supply 302 for providing positive and negative voltages to high frequency switches
`
`A-B and low frequency switches C-D, as shown. In an embodiment, switches A-D are
`
`comprised of high frequency switches, such asfield effect transistors (FETs). It should be
`
`understood by those skilled in the art that other switches or suitable switching mechanisms
`
`may be employed, depending onthe specific application of the inverter. Inverter 300 may
`
`comprise a high frequency switching control (1) comprising controller 303 and sensing
`
`circuit 304.
`
`[0076]
`
`In an embodiment, controller may comprise a current-mode PWM
`
`controller (see FIG. 3C) and sensing circuit 304 comprises a peak current sense and an
`
`output voltage sense (see refs. 304A-B of FIG. 3C). Controller 303 may be operatively
`
`coupled to a gate of each of switches A-D, while sensing circuit 304 may be coupled to a
`
`load line as is shownillustratively in FIG. 3A. Alternatively, controller may be a
`
`microprocessor running firmware to control switches A-D.
`
`[0077]
`
`Controller 303 may be configured to provide a low frequency sine wave (or
`
`other suitable signal) to effect switching control on the synchronous-buckportion of
`
`19
`
`

`

`ATTY. DKT. 63219-JBL-0096-US-D
`
`inverter 300. Main switching mayberealized using synchronous-buck switching portion
`
`(2), comprising switches A andB, to invert every half cycle of the frequency ofthe signal
`
`provided by controller 303. The inverting process thus creates a positive and negative
`
`transition of the sine wave signal. Low frequency switching stage (3) comprises switches
`
`C and D and maybeconfigured to operate as zero voltage switching (ZVS) and zero
`
`current switching (ZCS) drives
`
`[0078]
`
`Notably, using the configuration of FIG. 3A, the charge on output capacitor
`
`305 is discharged to zero on every zero crossing of low frequency switching stage (3).
`
`Compared to a conventional synchronous buck, the configuration of FIG. 3A
`
`advantageously discharges energy every half cycle. During this discharge of energy, the
`
`zero crossing distortion in the low frequency sine waveis greatly reduced.
`
`[0079]
`
`Turning now to FIG. 3B, an exemplary switching sequenceisillustrated
`
`wherein switches A and B of the synchronous-buck switching portion (2) simultaneously
`
`and alternately provide high frequency PWM (x) and high frequency PWM complement
`
`(x’) for each positive half wave and negative half wave. Switches C and D for the low
`
`frequency switching stage (3) are configured such that switch C is OFF for each positive
`
`half wave and ON for each negative half wave, while switch D is ON for each positive half
`
`wave and OFF for each negative half wave.
`
`[0080]
`
`FIG. 3C is another exemplary embodiment of a synchronous buck inverter,
`
`similar to inverter 300, wherein high voltage regulator house supply 302 receives input
`
`power (+HV,-HV) from a source (e.g., 301) and produces output voltage +V for each of
`
`20
`
`

`

`ATTY. DKT. 63219-JBL-0096-US-D
`
`the switch drives (A-D Drive) and voltage +VL for current-mode PWMcontroller 303,
`
`peak current sense 304A and output voltage sense 304B. Controller 303 may provide low
`
`frequency signals (e.g., sine wave) via low frequency oscillator 310. Controller 303 as
`
`illustrated in the embodiment of FIG. 3C may comprise a high frequency (HF) switching
`
`portion and low frequency (LF) switching portion, wherein HF switching portion
`
`activates/deactivates switches associated with A DRIVE and B DRIVEof synchronous-
`
`buck/buck-synchronous stage 311 (see section (2) of FIG. 3A). LF switching portion may
`
`activate/deactivate switches associated with C DRIVE and D DRIVE ofinverter stage 312
`
`(see section (3) of FIG. 3A).
`
`[0081]
`
`Turning now to FIG. 4, an exemplary switch sequence diagram for the
`
`embodiment of FIG. 3A is provided for one cycle of controller output (Output) illustrated
`
`as a sine wavein the figure. As can be seen, high frequency outputs for switches A and B
`
`(Agate, Beate) are shown together with low frequency outputs for switches C and D (Cgate,
`
`Dgate), together

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