GRTD60-3413 8
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`ABSTRACT
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`PATENT
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`A flash eentreiier for managing at ieast one MLC irrihweiatiie memory meduie and at
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`ieast one SLC hen—voiatiie memery meduie. The flash centrelier is adapted to determine if a
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`range of addresses iisted by an entry and m apped to said at ieast ene MLC rten—veiatiie memory
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`medule fails a data integrity test. in the event (if such a failure, the controller remaps said entry t0
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`an equivalent range of addresses of said at ieast one SLC nert—veia‘riie mem ery meduie The f} ash
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`centreiier is timber adapted to determine which of the hieeks in the MLC and SLC nen-veiatiie
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`mehtery meduies are accessed most frequently and allocating these hieeks that receive frequent
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`writes to the SLC henwvciatiie irterhery meduie and these hieeks that receive infrequent writes to
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`the REC nonnveiatiie memmy module.
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`16
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