UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`
`UNITED STATES DEPARTMENT OF COMMERCE
`United States Patent and Trademark Office
`Address: COMMISSIONER FOR PATENTS
`PO. Box 1450
`Alexandria, Virginia 2231371450
`www.uspto.gov
`
`16/006,299
`
`06/12/2018
`
`GR. MOHAN RAO
`
`GRTD60—34l38
`
`6732
`
`MUNCK WILSON MANDALA L.L.P
`
`P 0 Drawer 800889
`DALLAS, TX 75380
`
`REIDLINGER. RONALD LANCE
`
`ART UNIT
`
`2824
`
`PAPER NUMBER
`
`NOTIFICATION DATE
`
`DELIVERY MODE
`
`12/13/2019
`
`ELECTRONIC
`
`Please find below and/or attached an Office communication concerning this application or proceeding.
`
`The time period for reply, if any, is set in the attached communication.
`
`Notice of the Office communication was sent electronically on above—indicated "Notification Date" to the
`
`following e—mail address(es):
`
`IPdocketing @ munekwilson.eom
`admin @ dalpat.com
`eoffieeaetion @ appeoll.eom
`
`PTOL-90A (Rev. 04/07)
`
`

`

`0/7709 A0170” Summary
`
`Application No.
`16/006,299
`Examiner
`R LANCE REIDLINGER
`
`Applicant(s)
`RAO, GR. MOHAN
`Art Unit
`AIA (FITF) Status
`2824
`No
`
`- The MAILING DA TE of this communication appears on the cover sheet wit/7 the correspondence address -
`Period for Reply
`
`A SHORTENED STATUTORY PERIOD FOR REPLY IS SET TO EXPIRE g MONTHS FROM THE MAILING
`DATE OF THIS COMMUNICATION.
`Extensions of time may be available under the provisions of 37 CFR 1.136(a). In no event, however, may a reply be timely filed after SIX (6) MONTHS from the mailing
`date of this communication.
`|f NO period for reply is specified above, the maximum statutory period will apply and will expire SIX (6) MONTHS from the mailing date of this communication.
`-
`- Failure to reply within the set or extended period for reply will, by statute, cause the application to become ABANDONED (35 U.S.C. § 133).
`Any reply received by the Office later than three months after the mailing date of this communication, even if timely filed, may reduce any earned patent term
`adjustment. See 37 CFR 1.704(b).
`
`Status
`
`1). Responsive to communication(s) filed on 26 June 2019.
`El A declaration(s)/affidavit(s) under 37 CFR 1.130(b) was/were filed on
`
`2a). This action is FINAL.
`
`2b) D This action is non-final.
`
`3)[:] An election was made by the applicant in response to a restriction requirement set forth during the interview
`on
`; the restriction requirement and election have been incorporated into this action.
`
`4):] Since this application is in condition for allowance except for formal matters, prosecution as to the merits is
`closed in accordance with the practice under Expade Quay/e, 1935 CD. 11, 453 O.G. 213.
`
`Disposition of Claims*
`
`5)
`
`Claim(s) fl is/are pending in the application.
`
`5a) Of the above Claim(s)
`
`is/are withdrawn from consideration.
`
`
`
`[:1 Claim(ss)
`
`is/are allowed.
`
`8)
`Claim(s 1_—21Is/are rejected
`
`D Claim(ss_) is/are objected to.
`
`) ) ) )
`
`S)
`are subject to restriction and/or election requirement
`[:1 Claim(s
`* If any claims have been determined aflowable. you may be eligible to benefit from the Patent Prosecution Highway program at a
`
`participating intellectual property office for the corresponding application. For more information, please see
`
`http://www.uspto.gov/patents/init events/pph/index.jsp or send an inquiry to PPeredback@uspto.gov.
`
`Application Papers
`
`10)|:l The specification is objected to by the Examiner.
`
`11). The drawing(s) filed on 12 June 2018 is/are: a). accepted or b)D objected to by the Examiner.
`Applicant may not request that any objection to the drawing(s) be held in abeyance. See 37 CFR 1.85(a).
`Replacement drawing sheet(s) including the correction is required if the drawing(s) is objected to. See 37 CFR 1.121 (d).
`
`Priority under 35 U.S.C. § 119
`
`12)D Acknowledgment is made of a claim for foreign priority under 35 U.S.C. § 119(a)-(d) or (f).
`Certified copies:
`
`a)I:i All
`
`b)C] Some**
`
`c)C] None of the:
`
`1.[:] Certified copies of the priority documents have been received.
`
`2C] Certified copies of the priority documents have been received in Application No.
`
`SD Copies of the certified copies of the priority documents have been received in this National Stage
`application from the International Bureau (PCT Rule 17.2(a)).
`
`** See the attached detailed Office action for a list of the certified copies not received.
`
`Attachment(s)
`
`1)
`
`Notice of References Cited (PTO-892)
`
`2) C] Information Disclosure Statement(s) (PTO/SB/08a and/or PTO/SB/08b)
`Paper No(s)/Mail Date_
`U.S. Patent and Trademark Office
`
`3) E] Interview Summary (PTO-413)
`Paper No(s)/Mail Date
`4) CI Other-
`
`PTOL-326 (Rev. 11-13)
`
`Office Action Summary
`
`Part of Paper No./Mai| Date 20191204
`
`

`

`Application/Control Number: 16/006,299
`Art Unit: 2824
`
`Page 2
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`DETAILED ACTION
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`1.
`
`2.
`
`Claims 1-21 are pending.
`
`Claims 1 and 19 are independent.
`
`3.
`
`The present application is being examined under the pre-AIA first to invent provisions.
`
`Notice of Pre-AIA or AIA Status
`
`Claim Rejections - 35 USC § 112(0)
`
`4.
`
`The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
`
`(a) IN GENERAL—The specification shall contain a written description of the invention, and
`of the manner and process of making and using it, in such full, clear, concise, and exact terms as to
`enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to
`make and use the same, and shall set forth the best mode contemplated by the inventor orjoint
`inventor of carrying out the invention.
`
`The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
`
`The specification shall contain a written description of the invention, and of the manner and
`process of making and using it, in such full, clear, concise, and exact terms as to enable any person
`skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the
`same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
`
`5.
`
`Claims 2, 5, 6 and 15-18 and 20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA),
`
`first paragraph, as failing to comply with the written description requirement. The claim(s) contains
`
`subject matter which was not described in the specification in such a way as to reasonably convey to
`
`one skilled in the relevant art that the inventor or a joint inventor, or for pre-AIA the inventor(s), at the
`
`time the application was filed, had possession of the claimed invention.
`
`Regarding claims 2 and 20, there is no support for the memory elements being software.
`
`Regarding claims 5 and 6, there is no support for the memory in the MLC nonvolatile memory
`
`nonvolatile memory elements being phase-change or magnetic random access memory.
`
`Regarding claims 15-18, there is no support for the MLC being anything other than two bits.
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`

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`Application/Control Number: 16/006,299
`Art Unit: 2824
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`Page 3
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`Claim Rejections - 35 USC § 112(b)
`
`6.
`
`The following is a quotation of 35 U.S.C. 112(b):
`
`(b) CONCLUSION—The specification shall conclude with one or more claims particularly pointing out
`and distinctly claiming the subject matter which the inventor or a joint inventor regards as the
`invention.
`
`The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph:
`
`The specification shall conclude with one or more claims particularly pointing out and distinctly
`claiming the subject matter which the applicant regards as his invention.
`
`7.
`
`Claims 2, 15 and 19-21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second
`
`paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject
`
`matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
`
`Regarding claims 2 and 20, it is unclear what is meant by a memory element being a software
`
`module.
`
`Regarding claim 15, it is unclear what is meant by a MLC having only one bit. An MLC must have
`
`at least two bits or it is an SLC.
`
`Regarding claim 19, the following limitations establish conflicting antecedent basis,
`
`”at least one controller to operate memory elements and associated memory space”
`
`”at least one controller to maintain an address table in one or more of the memory elements"
`
`It’s unclear whether this is the same controller or a different one and to which each instance of
`
`the controller is referring.
`
`Regarding claims 20 and 21, they are indefinite for depending on an indefinite claim.
`
`Claim Rejections - 35 USC § 103
`
`8.
`
`In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102
`
`and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory
`
`

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`Application/Control Number: 16/006,299
`Art Unit: 2824
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`Page 4
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`basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and
`
`the rationale supporting the rejection, would be the same under either status.
`
`9.
`
`The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness
`
`rejections set forth in this Office action:
`
`(a) A patent may not be obtained though the invention is not identically disclosed or described as set
`forth in section 102, if the differences between the subject matter sought to be patented and the
`prior art are such that the subject matter as a whole would have been obvious at the time the
`invention was made to a person having ordinary skill in the art to which said subject matter pertains.
`Patentability shall not be negatived by the manner in which the invention was made.
`
`10.
`
`The factual inquiries set forth in Graham v. John Deere C0,, 383 U.S. 1, 148 USPQ 459 (1966),
`
`that are applied for establishing a background for determining obviousness under pre-AIA 35 U.S.C.
`
`103(a) are summarized as follows:
`
`1. Determining the scope and contents of the prior art.
`
`2. Ascertaining the differences between the prior art and the claims at issue.
`
`3. Resolving the level of ordinary skill in the pertinent art.
`
`4. Considering objective evidence present in the application indicating obviousness or
`
`nonobviousness.
`
`11.
`
`Claims 1-4 and 7-17 are rejected under pre-AIA 35 U.S.C. 103(3) as being unpatentable over
`
`Gorobets et al. (U.S. Patent Application Publication No. 2010/0172179, on record in parent application
`
`13/455,267) in view of Goodson et al. ("Design Tradeoffs in a Flash Translation Layer," on record in
`
`parent application 13/455,267) and Oribe et al. (US 2009/0172267 A1).
`
`Regarding claim 1, Gorobets et al. teach,
`
`A system for storing data (e.g. Fig. 20) comprising:
`
`memory space containing volatile memory space (Fig. 15, 102 Cache (RAM), see e.g.1] [0135]
`
`”volatile RAM are employed as cache as. .
`
`. in a controller cache 102”) and nonvolatile memory space
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`(Fig. 15, MLC Memory, including Main Memory and Binary Cache), wherein the nonvolatile memory
`
`

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`Art Unit: 2824
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`Page 5
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`space includes both multilevel cell (M LC) space (Fig. 15, 202 Main Memory of MLC Memory) and single
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`level cell (SLC) space (Fig. 15, 204 Binary Cache of MLC Memory);
`
`at least one controller (Fig. 8 Memory Manager No. 300; see also Fig. 15 Controller) to operate
`
`memory elements and associated memory space (Flash Memory No. 200);
`
`at least one MLC nonvolatile memory element (Fig. 20 Main Portion MLC No. 2003; this is a
`
`primary characteristic of flash EEPROM of which this device is, see e.g. 1] [0008]);
`
`at least one SLC nonvolatile memory element (Fig. 20 Binary Portion No. 2001; again, this is a
`
`primary characteristic of flash EEPROM of which this device is, see e.g. 1] [0008]);
`
`at least one random access volatile memory element (see Fig. 15, 102 Cache (RAM));
`
`wherein the at least one controller (Fig. 8 Memory Manager No. 300; see also Fig. 15 Controller)
`
`maintains an address table in one or more of the memory elements (see 1] [0096]);
`
`the controller controlling access of the MLC and SLC nonvolatile memory elements and the
`
`random access volatile memory elements for storage of data therein (see 1] [0092]);
`
`wherein the address table maps logical and physical addresses (memory manager in the
`
`controller maps logical addresses to physical addresses, see 1] [0096]) adaptable to the system, wherein
`
`the mapping is performed as necessitated by the system to maximize lifetime, and wherein the mapping
`
`maps blocks, pages, or bytes of data in either volatile or nonvolatile, or both, memories (see 1] [0152-
`
`154], explaining the use of spare block pool management to increase lifetime of the memory device;
`
`mapping would be necessary to remap any logical address pointing to a retired block so that it points to
`
`a replacement block, or new physical address).
`
`Gorobets et al. explain address translation layers for flash memory, but do not describe the
`
`specific term ”an FTL flash translation layer.”
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`

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`Art Unit: 2824
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`Page 6
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`Nevertheless, Goodson et al. document the purpose and motivation for using FTL for a flash
`
`memory device (see Title, ”Design Tradeoffs in a Flash Translation Layer,” and §§ 1-2, which explain the
`
`purpose of flash translation layers).
`
`It would have been obvious to one of ordinary skill in the art at the time of the invention to
`
`apply the teachings of Goodson et al. to the teachings of Gorobets et al. such that an FTL (as explained
`
`by Goodson et al.) is used with the flash device taught by Gorobets et al. for the purpose of allowing the
`
`files system of the flash memory device to maintain the block interface of the disk without sacrificing
`
`the tighter integration and control over how the flash is managed and because it hides the complexity of
`
`the flash by providing a logical block interface for the flash device.
`
`Further, Gorobets et al. fail to explicitly teach the data integrity test and remapping in response
`
`to a failure of the test. Gorobets et al. clearly hints at such a test as it discusses errors and the need to
`
`relocate due to errors (see e.g. 111] [0164]), but Gorobets et al. fail to teach that the errors are detected
`
`with an integrity test.
`
`Oribe et al. teach in Fig. 7 using a data integrity test (i.e. bit error greater than threshold, see e.g.
`
`SP10, 12 and 14) to mark a block for refresh. See 1] [0060]. Oribe et al. further teach that in a refresh
`
`the data is moved to a new block and the address management table is updated. See Fig.8 and 111]
`
`[0061 and 0056].
`
`Using a data integrity test can put a high priority in moving data from bad blocks prior to them
`
`completely failing and losing the data. Thus it would have been obvious to one of ordinary skill in the art
`
`prior to the effective filing date to use the data integrity test to ensure that the data is saved.
`
`Regarding claims 2 and 9, Gorobets et al. explain that flash memory is most commonly provided
`
`in the form of a memory card (i.e., module or standalone unit as claimed) or a flash drive (i.e., module or
`
`standalone unit or hard drive, as claimed) (see background 1] [0015]). Because Gorobets et al.
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`embodiments involve flash memory, the provisions of being a hardware module, a standalone device or
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`a hard disk drive, as claimed, are met.
`
`Regarding claim 3, Gorobets et al. teach at least one of the volatile or nonvolatile memories are
`
`embedded in the at least one controller (see Fig. 15 volatile Cache (RAM) 102 is embedded within
`
`Controller).
`
`Regarding claim 4, Gorobets et al. teach the MLC and SLC nonvolatile memory elements (Figs. 15
`
`MLC Memory) is flash memory because the device is a flash memory device (see 1] [0135]; see also, Fig.
`
`15, which labels the memory device as a ”Flash Memory Device”).
`
`Regarding claims 7 and 8, although Gorobets et al. teach the volatile memory (Fig. 15 Cache
`
`(RAM) 102), they are silent with respect to the specific type of volatile memory—whether DRAM or
`
`SRAM as claimed. Gorobets et al. does not mention or show any aspects of the type of volatile memory
`
`employed.
`
`OFFICIAL NOTICE is taken that DRAM and SRAM are volatile memory types that have been
`
`frequently used as volatile memory in computer systems, and these two types of volatile memory are
`
`obvious variants and their tradeoffs are well-documented in the prior art. For example, although SRAM
`
`is faster than DRAM, SRAM requires more components per cell because typical prior art CMOS SRAM
`
`cell involve six transistors (6T-SRAM), whereas the counterpart typical DRAM cell requires one transistor
`
`and one capacitor (1T1C). DRAM, however, has been well-established in the industry as a main memory
`
`for computing systems. The real estate required per cell is smaller than that for SRAM, meaning more
`
`storage capacity at cheaper cost. The tradeoff is that DRAM must include refresh circuitry to account for
`
`decay rate of the capacitors. Although SRAM is typically used for cache memory, DRAM is often
`
`employed as well.
`
`Therefore, it would have obvious to one of ordinary skill in the art before the invention use
`
`DRAM or SRAM for the volatile memory as claimed because of the reasons discussed above.
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`

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`Application/Control Number: 16/006,299
`Art Unit: 2824
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`Page 8
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`Regarding claim 10, Gorobets et al. teach remapping from the MLC to SLC and SLC to MLC, see 1]
`
`[0157]. As discussed above in the rejection of claim 1, it would have been obvious to remap in response
`
`to a failure of the data integrity test.
`
`Regarding claim 11, Gorobets et al. teach remapping from the MLC to SLC and SLC to MLC, see
`
`1] [0157]. Thus the given one could be either SLC or MLC.
`
`Regarding claim 12, Gorobets et al. teach SLC has better endurance. See 1] [0165].
`
`Regarding claims 13 and 14, Gorobets et al. teach both read and write access operations, see 1]
`
`[0009]. Oribe et al. further teach both write and read would happen prior to refresh, see e.g. SP2 or SP5
`
`of Fig. 6
`
`Regarding claims 15-17, Gorobets et al. teach that he MLC can be 1, 2 or 3 bits per cell (see 111]
`
`[0158] & [0070]).
`
`12.
`
`Claim 5 is rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Gorobets et al.
`
`in view of Goodson et al. and Oribe et al., as applied to claim 1, and further in view of De Ambroggi et
`
`al. (U.S. Patent Application Publication No. 2009/0268513, on record in parent application
`
`13/455,267) and Kund et al. (U.S. Patent Application Publication No. 2010/0058018, on record in
`
`parent application 13/455,267).
`
`Gorobets et al. fail to teach that the memory could be anything other than flash EEPROM or
`
`other types of charge trapping memory see e.g. 1] [0010] describing the various types of memory.
`
`De Ambroggi et al. teach that one type of resistive memory (RRAM), Phase Change (PCRAM or
`
`PCM) can be configured to be partially SLC and partially MLC.
`
`Kund et al. teach generally that ”Emerging memory technologies such as resistive memory (e.g.,
`
`resistive random access memories such as phase change random access memory (PCRAM), conductive
`
`bridge random access memory (CBRAM), and magnetic random access memory (MRAM) offer certain
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`advantages over DRAM, Flash and other conventional types of memory devices in terms of switching
`
`speeds, size, power consumption, and non-volatility.” 1] [0016].
`
`Accordingly it would have been obvious to one of ordinary skill in the art at the time of the
`
`invention to replace the flash EEPROM taught by Gorobets et al. with the PCM taught by De Ambroggi et
`
`al. in view of the PCM advantages over flash EEPROM taught by Kund et al. because the emerging
`
`memories (such as PCRAM) offer switching speed, size, power-consumption, and non-volatility
`
`advantages over flash memory.
`
`13.
`
`Claim 6 is rejected under pre-AIA 35 U.S.C. 103(3) as being unpatentable over Gorobets et al.
`
`in view of Goodson et al. and Oribe et al., as applied to claim 1, in further view of Chen et al. (U.S.
`
`Patent Application Publication No. 2009/0307418, on record in parent application 13/455,267) and
`
`Kund et al.
`
`Gorobets et al. fail to teach that the memory could be anything other than flash EEPROM or
`
`other types of charge trapping memory see e.g. 1] [0010] describing the various types of memory.
`
`Chen et al. teach that MRAM could be used as SLC in conjunction with some other memory type
`
`being used as MLC to create a hybrid density memory. See e.g.1] [0031].
`
`Kund et al. teach generally that ”Emerging memory technologies such as resistive memory (e.g.,
`
`resistive random access memories such as phase change random access memory (PCRAM), conductive
`
`bridge random access memory (CBRAM), and magnetic random access memory (MRAM)) offer certain
`
`advantages over DRAM, Flash and other conventional types of memory devices in terms of switching
`
`speeds, size, power consumption, and non-volatility.” 1] [0016].
`
`Accordingly it would have been obvious to one of ordinary skill in the art at the time of the
`
`invention to replace the SLC flash EEPROM taught by Gorobets et al. with the SLC MRAM in view of the
`
`MRAM advantages over flash EEPROM taught by Kund et al. because the emerging memories (such as
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`MRAM) offer switching speed, size, power-consumption, and non-volatility advantages over flash
`
`memory.
`
`14.
`
`Claim 18 is rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Gorobets et al.
`
`in view of Goodson et al. and Oribe et al., as applied to claims 1 and 16, and further in view of Lasser
`
`(US 2008/0181000 A1).
`
`Gorobets et al. fail to teach 4 bit MLC. Lasser teaches that it was known to have one two three
`
`or four bits in a cell with the latter having the largest capacity. See 1] [0009]. Accordingly it would have
`
`been obvious to one of ordinary skill in the art prior to the effective filing date to use 4 bit MLC to
`
`increase capacity.
`
`15.
`
`Claims 19-21 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Gorobets
`
`et al. in view of Oribe et al.
`
`Regarding claim 19, Gorobets et al. teach,
`
`A system for storing data (e.g. Fig. 20) comprising:
`
`memory space containing volatile memory space (Fig. 15 Cache (RAM)) and nonvolatile memory
`
`space (Fig. 15, MLC Memory, including Main Memory and Binary Cache), wherein the nonvolatile
`
`memory space includes both multilevel cell (MLC) (Figs. 15, 20 Main Memory of MLC Memory) space
`
`(Figs. 15, 20 Main Memory of MLC Memory) and single level cell (SLC) space (Figs. 15, 20 Binary Cache of
`
`MLC Memory);
`
`at least one controller (Fig. 8 Memory Manager No. 300; see also Fig. 15 Controller) to operate
`
`memory elements and associated memory space (Flash Memory No. 200);
`
`at least one MLC nonvolatile memory element (Fig. 20 Main Portion MLC No. 2003; this is a
`
`primary characteristic of flash EEPROM of which this device is, see e.g.1] [0008]);
`
`at least one SLC nonvolatile memory element (Fig. 20 Binary Portion No. 2001; again, this is a
`
`primary characteristic of flash EEPROM of which this device is, see e.g.1] [0008]);
`
`

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`at least one random access volatile memory element (see Fig. 15 Cache (RAM));
`
`the controller controlling access of the MLC and SLC nonvolatile memory elements and the
`
`random access volatile memory elements for storage of data therein (see 1] [0092]);
`
`wherein the at least one controller (Fig. 8 Memory Manager No. 300; see also Fig. 15 Controller)
`
`of both maintain an address table in one or more of the memory elements (see 1] [0096]); and
`
`wherein the address table maps logical and physical addresses (memory manager in the
`
`controller maps logical addresses to physical addresses, see 1] [0096]) adaptable to the system, wherein
`
`the mapping is performed as necessitated by the system to maximize lifetime, and wherein the mapping
`
`maps blocks, pages, or bytes of data in either volatile or nonvolatile, or both, memories (see 1] [0152-
`
`154], explaining the use of spare block pool management to increase lifetime of the memory device;
`
`mapping would be necessary to remap any logical address pointing to a retired block so that it points to
`
`a replacement block, or new physical address).
`
`at least one controller to maintain an address table in one or more of the memory elements (see
`
`1] [0096]);
`
`the controller controlling access of the MLC and SLC nonvolatile memory elements and the
`
`random access volatile memory elements for storage of data therein(see 1] [0092]);
`
`wherein the address table maps logical and physical addresses (memory manager in the
`
`controller maps logical addresses to physical addresses, see 1] [0096]) adaptable to the system, wherein
`
`the mapping is performed as necessitated by the system to maximize lifetime, and wherein the mapping
`
`maps blocks, pages, or bytes of data in either volatile or nonvolatile, or both, memories memories (see 1]
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`[0152-154], explaining the use of spare block pool management to increase lifetime of the memory
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`device; mapping would be necessary to remap any logical address pointing to a retired block so that it
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`points to a replacement block, or new physical address).
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`Gorobets et al. fail to teach,
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`Application/Control Number: 16/006,299
`Art Unit: 2824
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`Page 12
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`the controller performing a data integrity test on stored data in a given one of the MLC and SLC
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`nonvolatile memory elements after any access operation is performed thereon;
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`wherein a failure of the data integrity test performed by the controller results in a remapping of
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`the address space to a different physical range of addresses from those determined to have failed the
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`data integrity test to achieve enhanced endurance.
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`Oribe et al. teach in Fig. 7 using a data integrity test (i.e. bit error greater than threshold, see e.g.
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`SP10, 12 and 14) to mark a block for refresh. See 1] [0060]. Oribe et al. further teach that in a refresh
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`the data is moved to a new block and the address management table is updated See Fig.8 and 111] [0061
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`and 0056].
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`Using a data integrity test can put a high priority in moving data from bad blocks prior to them
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`completely failing and losing the data. Thus it would have been obvious to one of ordinary skill in the art
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`prior to the effective filing date to use the data integrity test to ensure that the data is saved.
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`Regarding claim 20, Gorobets et al. explain that flash memory is most commonly provided in the
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`form of a memory card (i.e., module or standalone unit as claimed) or a flash drive (i.e., module or
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`standalone unit or hard drive, as claimed) (see background 1] [0015]). Because Gorobets et al.
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`embodiments involve flash memory, the provisions of being a hardware module or a standalone device,
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`as claimed, are met.
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`Regarding claim 21, Gorobets et al. teach at least one of the volatile or nonvolatile memory
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`elements are embedded in the at least one controller. (See Fig. 15 Cache RAM is in the controller)
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`Response to Arguments
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`16.
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`Applicant's arguments filed 26 June 2019 have been fully considered but they are not
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`persuasive. Applicant’s initial arguments appear to be directed towards the intended purpose of the
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`limitations rather than the limitations themselves. Furthermore, Gorobets et al. does remap to improve
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`endurance. See e.g.1] [0155]. Applicant’s second argument that Gorobets et al. and the other
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`Application/Control Number: 16/006,299
`Art Unit: 2824
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`Page 13
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`references fail to teach an integrity check is not directed towards the Oribe et al. reference and is moot
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`in light of the new grounds for rejection.
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`Conclusion
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`17.
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`Applicant's amendment necessitated the new ground(s) of rejection presented in this Office
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`action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the
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`extension of time policy as set forth in 37 CFR 1.136(a).
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`A shortened statutory period for reply to this final action is set to expire THREE MONTHS from
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`the mailing date of this action.
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`In the event a first reply is filed within TWO MONTHS of the mailing date
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`of this final action and the advisory action is not mailed until after the end of the THREE-MONTH
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`shortened statutory period, then the shortened statutory period will expire on the date the advisory
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`action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing
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`date of the advisory action.
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`In no event, however, will the statutory period for reply expire later than
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`SIX MONTHS from the date of this final action.
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`18.
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`Any inquiry concerning this communication or earlier communications from the examiner
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`should be directed to R LANCE REIDLINGER whose telephone number is (571)270-7353. The examiner
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`can normally be reached on M-F 1:00pm - 10:00pm.
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`Examiner interviews are available via telephone, in-person, and video conferencing using a
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`USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use
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`the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
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`If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor,
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`Rich T Elms can be reached on 571.272.1869. The fax phone number for the organization where this
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`application or proceeding is assigned is 571-273-8300.
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`Information regarding the status of an application may be obtained from the Patent Application
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`Information Retrieval (PAIR) system. Status information for published applications may be obtained
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`

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`Application/Control Number: 16/006,299
`Art Unit: 2824
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`Page 14
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`from either Private PAIR or Public PAIR. Status information for unpublished applications is available
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`through Private PAIR only. For more information about the PAIR system, see http://pair-
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`direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic
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`Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR
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`CANADA) or 571-272-1000.
`
`/R.L.R./
`Examiner, Art Unit 2824
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`/J. H. Hur/
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`Primary Patent Examiner, Art Unit 2824
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`