100
`
`\
`
`Read Design, Power
`Intent and a list of
`
`
`
`
`
`
`abstract models (of
`design sub-modules)
`
`Select next SOC module (or entire SOC)
`skipping up-to—date modules
`
`
`
`
`
`Read required abstract models (of sub—
`modules) and power verify the selected
`
`module
`
`
`
`Generate abstract power
`model for selected
`
`module (if required)
`
`
`
`Fix power verification issues in the
`selected module
`
`FIGURE 1
`
`

`

`200
`N
`
`202
`
`210 \ VddB
`-
`
`220\
`P I
`
`(©
`
`FIGURE2
`
`300
`
`\
`
`
`
`FIGURE 3
`
`

`

`400
`
`\ F
`
`IGURE 4
`
`

`

`500
`
`\
`
`START
`
`S510
`
`Read Module
`
`Design, Power Intent
`
`
`and abstract models
`
`
`
`
`
`Capture Interface supplies
`
`S520
`
`
`
`$530
`
`Identify “related supplies”
`
`' Establish PSTs
`
`Model isolation logic
`
`Model level shifters
`
`
`
`
`
`
`
`
`54
`
`O
`
`8550
`
`8560
`
`
`8570
`
`3580
`
`
`3590
`
`Model feed—through, floating ports
`
`Model Power switches
`
`FIGURE 5
`
`

`

`670
`
`680
`
`IIIIIIIIIIIIIIIIIIIIIIIIIIII
`
`lllllllllllllllllllllllllllllllllllllllllllllllllllllllll
`
`Hierarchical
`Power
`Verification
`
`System
`
`CPU
`
`Input
`Device
`
`1p.mD
`
`m.
`
`650
`
`FIGURE 6
`
`Verification
`
`Power
`
`Storage Medium
`
`
`

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