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`A hierarchical power verification system and method creates abstract models of power
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`behavior of modules that it successfully verifies. The abstract models simplify the module
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`definition by omitting internal module details but provide sufficient information for power
`
`verification of higher level modules that incorporate this abstracted module. Design blocks are
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`replaced with these abstract power models,
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`resulting in reduced run-time and memory
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`requirements. The power models can include power switches inside the block, related supplies of
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`logic ports, supply power states, system power states, power management devices such as isolation
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`logic and level shifters, feed-through and floating ports. The power model may be expressed either
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`in UPF or as a combination of liberty model and UPF. After replacing modules with abstracted
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`models the HPVS can quickly verify an entire SoC with a small memory footprint. When a user
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`modifies a module, the HPVS need only verify the changed module and related modules at higher
`
`levels of module hierarchy.
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`35
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`22524/41614/FW/10311251.1
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