What is claimed is:
`
`Claims
`
`l.
`
`A method implemented by a computer system comprising a power verification tool, the
`
`method for verifying a power behavior of a module in a circuit design, the method comprising:
`
`reading the hierarchical circuit design and a power intent file of the hierarchical circuit
`
`design, wherein the hierarchical circuit design specifies that the module includes
`
`one or more sub-modules and the power intent file specifies a power architecture
`
`of power/voltage domains, power supplies and corresponding power devices of
`
`the circuit design,
`
`for each sub-module, determining whether a corresponding up-to-date abstracted power
`
`model eXists, wherein the abstracted power model describes a power behavior of
`
`the sub-module while omitting internal logic of the sub-module, the abstracted
`
`power model created as a result of an earlier power verification of the sub-
`
`module,
`
`verifying the power behavior of the module by (a) using the up-to-date abstracted power
`
`models for those sub-modules with up-to-date abstracted power models, and (b)
`
`verifying the power behavior of those sub-modules without up-to-date abstracted
`
`power models,
`
`creating abstracted power models for those sub-modules that were power verified, the
`
`abstracted power models created by performing in any order one or more of: (l)
`
`capturing interface supplies, (2) creating power domains, (3) identifying related
`
`supplies, (4) establishing power state tables, (5) modeling isolation logic, (6)
`
`modeling level shifters, (7) modeling feed-through floating ports, and (8)
`
`modeling power switches, and
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`
`
`Claims
`
`l.
`
`A method implemented by a computer system comprising a power verification tool, the
`
`method for verifying a power behavior of a module in a circuit design, the method comprising:
`
`reading the hierarchical circuit design and a power intent file of the hierarchical circuit
`
`design, wherein the hierarchical circuit design specifies that the module includes
`
`one or more sub-modules and the power intent file specifies a power architecture
`
`of power/voltage domains, power supplies and corresponding power devices of
`
`the circuit design,
`
`for each sub-module, determining whether a corresponding up-to-date abstracted power
`
`model eXists, wherein the abstracted power model describes a power behavior of
`
`the sub-module while omitting internal logic of the sub-module, the abstracted
`
`power model created as a result of an earlier power verification of the sub-
`
`module,
`
`verifying the power behavior of the module by (a) using the up-to-date abstracted power
`
`models for those sub-modules with up-to-date abstracted power models, and (b)
`
`verifying the power behavior of those sub-modules without up-to-date abstracted
`
`power models,
`
`creating abstracted power models for those sub-modules that were power verified, the
`
`abstracted power models created by performing in any order one or more of: (l)
`
`capturing interface supplies, (2) creating power domains, (3) identifying related
`
`supplies, (4) establishing power state tables, (5) modeling isolation logic, (6)
`
`modeling level shifters, (7) modeling feed-through floating ports, and (8)
`
`modeling power switches, and
`
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`22524/41614/FW/10311251.1
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`
`
`making the created abstracted power models for sub-modules available for later power
`
`verification of modules that contain the sub-modules.
`
`The computer-implemented method of claim 1 wherein:
`
`creating the abstracted power models for the sub-modules comprises capturing interface
`
`supplies; and
`
`capturing interface supplies is performed by identifying supply ports; generating port
`
`states for the supply ports; generating voltage maps for the port states, and
`
`creating supply nets for the supply ports.
`
`The computer-implemented method of claim 1 wherein:
`
`creating abstracted power models for the sub-modules comprises creating power
`
`domains; and
`
`creating power domains includes specifying a top domain and specifying key supply nets
`
`for the top domain.
`
`The computer-implemented method of claim 1 wherein:
`
`creating abstracted power models for the sub-modules comprises identifying related
`
`supplies; and
`
`identifying related supplies is performed by a depth f1rst traversal from a top level
`
`interface port; skipping all nested domain boundary ports that do not have a level
`
`shifter strategy specified; if the destination is a leaf cell; setting the related supply
`
`as that powering the leaf cell; and if the destination is a nested domain boundary
`
`port having a level shifter strategy; setting the related supplies as those supplying
`
`that boundary port’s level shifter on input and output sides.
`
`28
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`22524/41614/FW/10311251.1
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`
`
`5.
`
`The computer-implemented method of claim 1 wherein:
`
`creating abstracted power models for the sub-modules comprises establishing power state
`
`tables; and
`
`establishing power state tables contains only supplies generated during an identification
`
`of related supplies.
`
`6.
`
`The computer-implemented method of claim 5 wherein the power state tables are merged
`
`for each sub-module that is a complete module.
`
`7.
`
`The computer-implemented method of claim 1 wherein:
`
`creating abstracted power models for the sub-modules comprises modeling isolation
`
`logic; and
`
`modeling isolation logic entails specifying isolation strategies, attributes at the logic port
`
`for isolation present at top level logic ports, or both; for isolation present at nested
`
`domain boundary ports, modeling performed by: a depth first traversal from a top-
`
`level logic port, skipping every nested domain boundary port that has neither level
`
`shifter nor isolation strategy specified; if a nested domain boundary port is found
`
`with a level shifter strategy, then moving onto a next logic port; and if a nested
`
`domain boundary port is found with isolation strategy specified, then setting an
`
`isolated attribute for that port to true.
`
`8.
`
`The computer-implemented method of claim 1 wherein:
`
`creating abstracted power models for the sub-modules comprises modeling level shifters;
`
`and
`
`modeling level shifters is performed for each top level logic port having a level strategy
`
`specified.
`
`29
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`22524/41614/FW/10311251.1
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`
`
`9.
`
`The computer-implemented method of claim 1 wherein:
`
`creating abstracted power models for the sub-modules comprises modeling feed-through
`
`and floating ports; and
`
`modeling feed-through and floating ports is performed by a backward depth first
`
`traversal, skipping nested domain boundary ports that have neither level shifter
`
`nor isolation strategy specified; if a destination is not an interface port; then doing
`
`nothing; if a destination is an interface input port with level shifter or isolation
`
`strategy specified on any port in the traversal path; then doing nothing; otherwise
`
`set interface input port attribute function as feedthrough; and if a port is not
`
`connected to a net; then creating a corresponding pin and setting related supplies
`
`to the primary supply of its power domain.
`
`10.
`
`The computer-implemented method of claim 1 wherein:
`
`creating abstracted power models for the sub-modules comprises modeling power
`
`switches; and
`
`modeling power switches includes specifying input supply port; output supply port and
`
`switch control port; together with specifying the port states of the output supply
`
`port; and is done only when an interface port has a related supply which is the
`
`output of a power switch.
`
`11.
`
`The computer-implemented method of claim 1 wherein the abstracted power models are
`
`represented in any one or more of: (a) liberty files with auxiliary attributes; including power state
`
`tables; being specified in a power specif1cation language; or (b) a full power-specification-
`
`language based file.
`
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`
`
`12.
`
`The computer-implemented method of claim 1 wherein the abstracted power models are
`
`expressed as any one or more of:
`
`(a) UPP, or (b) a combination ofliberty model and UPF.
`
`13.
`
`The computer-implemented method of claim 1 wherein the module is a top-level module
`
`in the hierarchical design.
`
`14.
`
`The computer-implemented method of claim 1 wherein the method is repeated for all
`
`modules in the hierarchical design that are without a corresponding up-to-date abstracted power
`
`model.
`
`15.
`
`The computer-implemented method of claim 14 wherein, after the method is completed
`
`for all such modules, up-to-date abstracted power models exist for all modules in the hierarchical
`
`design.
`
`16.
`
`The computer-implemented method of claim 1 further comprising:
`
`displaying on a display of the computer system, any errors identified by the power
`
`verification, and using an input deVice to facilitate correction of at least one of the
`
`hierarchical circuit design and the power intent file.
`
`17.
`
`The computer-implemented method of claim 1 further comprising:
`
`receiVing a user input that identifies the module to be power verified.
`
`18.
`
`The computer-implemented method of claim 1 wherein:
`
`receiVing a user input that identifies modules for which the corresponding abstracted
`
`power models are created.
`
`19.
`
`A non-transitory computer-readable storage medium storing executable computer
`
`program instructions for verifying a power behaVior of a module in a hierarchical circuit design,
`
`the instructions executable by a processor and causing the processor to perform a method
`
`comprising:
`
`31
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`22524/41614/FW/10311251.1
`
`
`
`reading the hierarchical circuit design and a power intent file of the hierarchical circuit
`
`design, wherein the hierarchical circuit design specifies that the module includes
`
`one or more sub-modules and the power intent file specifies a power architecture
`
`of power/voltage domains, power supplies and corresponding power devices of
`
`the circuit design;
`
`for each sub-module, determining whether a corresponding up-to-date abstracted power
`
`model exists, wherein the abstracted power model describes a power behavior of
`
`the sub-module while omitting internal logic of the sub-module, the abstracted
`
`power model created as a result of an earlier power verification of the sub-
`
`module,
`
`verifying the power behavior of the module by (a) using the up-to-date abstracted power
`
`models for those sub-modules with up-to-date abstracted power models, and (b)
`
`verifying the power behavior of those sub-modules without up-to-date abstracted
`
`power models,
`
`creating abstracted power models for those sub-modules that were power verified, the
`
`abstracted power models created by performing in any order one or more of: (1)
`
`capture interface supplies, (2) create power domains, (3) identify related supplies,
`
`(4) establish power state tables, (5) model isolation logic, (6) model level shifters,
`
`(7) model feed-through floating ports, and (8) model power switches, and
`
`making the created abstracted power models for sub-modules available for later power
`
`verification of modules that contain the sub-modules.
`
`20.
`
`A power verification system for verifying a power behavior of a module in a hierarchical
`
`circuit design, the system comprising:
`
`32
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`22524/41614/FW/10311251.1
`
`
`
`a storage medium for receiving and storing the hierarchical circuit design and a power
`
`intent file of the hierarchical circuit design, wherein the hierarchical circuit design
`
`specifies that the module includes one or more sub-modules and the power intent
`
`file specifies a power architecture of power/voltage domains, power supplies and
`
`corresponding power devices of the circuit design; and
`
`a processor having access to the storage medium and executing an application program
`
`for a hierarchical power verification tool, wherein the processor executing the
`
`application program:
`
`for each sub-module, determines whether corresponding up-to-date abstracted
`
`power models exist, wherein the abstracted power model describes a
`
`power behavior of the sub-module while omitting internal logic of the sub-
`
`module, the abstracted power model created as a result of an earlier power
`
`verification of the sub-module,
`
`verifies the power behavior of the module by (a) using the up-to-date abstracted
`
`power models for those sub-modules with up-to-date abstracted power
`
`models, and (b) verifying the power behavior of those sub-modules
`
`without up-to-date abstracted power models,
`
`creates abstracted power models for those sub-modules that were power verified,
`
`the abstracted power models created by performing in any order one or
`
`more of: (1) capture interface supplies, (2) create power domains, (3)
`
`identify related supplies, (4) establish power state tables, (5) model
`
`isolation logic, (6) model level shifters, (7) model feed-through floating
`
`ports, and (8) model power switches, and
`
`33
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`22524/41614/FW/10311251.1
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`
`
`makes the created abstracted power models for sub-modules available for later
`
`power verification of modules that contain the sub-modules.
`
`34
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`22524/41614/FW/10311251.1
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`
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