`
`1.
`
`A display device comprising:
`
`a display panel comprising a base film and a circuit layer disposed on the base film, the
`
`circuit layer comprising a plurality of gate lines, a plurality of data lines, a sense driving unit, and
`
`a gate driving unit configured to receive a plurality of gate control signals and provide a gate
`
`signal to the plurality of gate lines, and
`
`a sensing unit comprising a plurality of driving electrodes, a plurality of sensing
`
`electrodes, the sense driving unit configured to receive a plurality of driving control signals and
`
`provide a sense driving signal to the plurality of driving electrodes, and plurality of sensing pads
`
`configured to transfer, to the outside, an electric signal received from each of the plurality of
`
`10
`
`sensing electrodes.
`
`2.
`
`The display device of claim 1, wherein the gate driving unit comprises a plurality
`
`of gate stages, and the sense driving unit comprises a plurality of sense stages, wherein the
`
`plurality of gate stages and the plurality of sense stages are arranged in the same layer.
`
`3.
`
`The display device of claim 2,
`
`wherein the plurality of gate control signals comprise a first clock signal, a second clock
`
`signal, and a frame start signal, and the plurality of driving control signals comprise the first
`
`clock signal and the second clock signal,
`
`wherein a first gate stage among the plurality of gate stages receives the frame start signal.
`
`32
`
`
`
`4.
`
`The display device of claim 3, wherein a first sense stage among the plurality of
`
`sense stages receives a signal output from an nth gate stage (where n is a positive integer) among
`
`the plurality of gate stages.
`
`5.
`
`The display device of claim 3,
`
`wherein the circuit layer further comprises a dummy unit electrically connected to the
`
`gate driving unit and the sense driving unit,
`
`wherein the dummy unit comprises at least one dummy stage connected between an nth
`
`gate stage (where n is a positive integer) among the plurality of gate stages and a first sense stage
`
`among the plurality of sense stages.
`
`6.
`
`The display device of claim 5, wherein the first sense stage receives a signal
`
`output from the dummy stage.
`
`7.
`
`The display device of claim 3,
`
`wherein the plurality of driving control signals further comprise a sense start signal,
`
`wherein a first sense stage among the plurality of sense stages receives the sense start
`
`signal.
`
`8.
`
`The display device of claim 3, wherein the plurality of gate stages and the
`
`plurality of sense stages are electrically connected.
`
`9.
`
`The display device of claim 3, wherein each of the plurality of gate stages and
`
`33
`
`
`
`each of the plurality of sense stages comprise the same circuit structure.
`
`10.
`
`The display device of claim 2,
`
`wherein the plurality of gate control signals comprise a first clock signal, a second clock
`
`signal, and a first frame start signal,
`
`wherein the plurality of driving control signals comprise a third clock signal, a fourth
`
`clock signal, and a second frame start signal different from the first frame start signal,
`
`wherein a first gate stage among the plurality of gate stages receives the first frame start
`
`signal, each of the plurality of gate stages receives the first clock signal and the second clock
`
`signal, a first sense stage among the plurality of sense stages receives the second frame start
`
`signal, and each of the plurality of sense stages receives the third clock signal and the fourth
`
`10
`
`clock signal.
`
`11.
`
`The display device of claim 10, wherein the plurality of driving control signals
`
`further comprise a fifth clock signal, and each of the plurality of sense stages receives the fifth
`
`clock signal.
`
`12.
`
`The display device of claim 11, further comprising a clock generation circuit
`
`configured to generate the fifth clock signal by gating the first clock signal and the second clock
`
`signal.
`
`13.
`
`The display device of claim 12, wherein the clock generation circuit comprises an
`
`AND circuit, a NAND circuit, an XOR circuit, or an XNOR circuit.
`
`34
`
`
`
`14.
`
`The display device of claim 10, wherein the plurality of gate stages and the
`
`plurality of sense stages comprise different circuit structures.
`
`15.
`
`The display device of claim 1,
`
`wherein each of the plurality of driving electrodes extends in a first direction, the
`
`plurality of driving electrodes are arranged in a second direction crossing the first direction, each
`
`of the plurality of sensing electrodes extends in the second direction, and the plurality of sensing
`
`electrodes are arranged in the first direction,
`
`wherein each of the plurality of gate lines extends in the second direction, the plurality of
`
`gate lines are arranged in the first direction, each of the plurality of data lines extends in the first
`
`direction, and the plurality of data lines are arranged in the second direction.
`
`16.
`
`A display device comprising:
`
`a base film,
`
`a circuit layer disposed on the base film, the circuit layer comprising a gate driving unit
`
`and a sense driving unit, the gate driving unit comprises a plurality of gate stages and the sense
`
`driving unit comprises a plurality of sense stages,
`
`a light-emitting element layer disposed on the circuit layer,
`
`a thin-film encapsulation layer covering the light-emitting element layer, and
`
`a sensing unit disposed on the thin-film encapsulation layer, the sensing unit comprising a
`
`plurality of driving electrodes configured to receive a sense driving signal from the sense driving
`
`10
`
`unit, and a plurality of sensing electrodes.
`
`35
`
`
`
`17.
`
`The display device of claim 16, wherein a first sense stage among the plurality of
`
`2
`
`sense stages receives a signal output from an nth gate stage (where n is a positive integer) among
`
`the plurality of gate stages.
`
`18.
`
`The display device of claim 16, wherein the circuit layer further comprises at least
`
`one dummy stage connected between an nth gate stage (where n is a positive integer) among the
`
`plurality of gate stages and a first sense stage among the plurality of sense stages, wherein the
`
`first sense stage among the plurality of sense stages receives a signal output from the dummy
`
`stage.
`
`19.
`
`The display device of claim 16, wherein the plurality of gate stages receive a first
`
`clock signal and a second clock signal, and the plurality of sense stages receive a third clock
`
`signal and a fourth clock signal.
`
`20.
`
`The display device of claim 19, wherein the plurality of sense stages further
`
`receive a fifth clock signal generated by gating the first clock signal and the second clock signal.
`
`36
`
`

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