Amendments to the Claims
`
`
`Claims 1, 7, and ll hav
`b
`n am nd d. Claims 2—6,
`
`8—
`
`13, and 15—20 are unchanged.
`
`
`
`
`The following listing of claims
`
`
`replaces all previous versions of the claims in the application.
`
`
`Listing of Claims
`
`1.
`
`(Currently Amended) A display, comprising:
`
`
`rows and columns of pixels;
`
`
`gate lines that are configured to supply gate
`
`signals to the rows;
`
`data lines including alternating odd and even data
`
`
`lines, wherein the data lines include pairs of data lines each
`
`
`
`including one of the odd data lines and an adjacent one of the
`
`
`
`even data lines, wherein each column of the pixels includes a
`
`
`
`respective one of the pairs of the data lines;
`
`demultiplexer circuitry coupled to the data lines;
`
`and
`
`display driver circuitry coupled to the
`
`
`demultiplexer circuitry, wherein the demultip-exer circuitry is
`
`
`
`configured to provide the pixels of each column with data from
`
`
`
`
`
`the display driver circuitry using the pair of data lines for
`
`
`
`
`that column and wherein the demultiplexer circuitry is configured
`
`to operate alternately in:
`
`
`a first mode in which the demultiplexer
`
`
`
`circuitry provides data from the display driver circuitry to the
`
`2
`
`

`

`odd data lines while the display driver circuitry asserts a gate
`
`
`
`
`line in a "irst o
`
`the rows; and
`
`a second mode in which the demultiplexer
`
`
`circuity provides data from the display driver circuitry to the
`
`
`even data lines while the display driver circuitry asserts a gate
`
`
`line in a second of the rows.
`
`2.
`
`
`
`(Original) The display defined in c'aim 1, wherein
`
`
`
`
`the disp'ay driver circuitry is configured to supply the
`
`
`
`
`
`demultip-exer circuitry with first and second clock signals.
`
`3.
`
`(Original) The display defined in claim 2, wherein
`
`
`
`the demultiplexer circuitry comprises a lz2 demultiplexer in each
`
`column.
`
`4.
`
`
`(Original) The display defined in claim 3 wherein
`
`
`the 1:2 demultiplexer in each column has an input and first and
`
`
`second outputs, wherein the first output is coupled to the odd
`
`
`data line of that column and the second output is coupled to the
`
`
`even data line of that column.
`
`5.
`
`
`(Original) The display defined in claim 4 wherein
`
`
`each of the pixels includes a light—emitting diode.
`
`6.
`
`
`(Original) The display defined in claim 5 wherein
`
`3
`
`

`

`the pixels comprise thin—'
`
`
`
`:ilm transistors having gates controlled
`
`by the gate signals.
`
`7.
`
`(Currently Amended)
`
`A display,
`
`comprising:
`
`rows and
`
`
`columns of
`
`pixels;
`
`gate lines that are con:
`
`
`
`figured to supply gate
`
`signals to the rows;
`
`data lines
`
`including alternating odd and even data
`
`lines,
`
`
`wherein the data lines include pairs of
`
`data lines each
`
`
`
`including one of the odd data lines and an adjacent one of the
`
`
`even data lines,
`
`
`wherein each column of the pi
`
`xels includes a
`
`
`
`respective one of the pairs of the
`
`data lines;
`
`demultiplexer circuitry coupled to the data lines;
`
`and
`
`display driver circuitry coupled to the
`
`
`demultiplexer circuitry,
`
`wherein the demultip' exer circuitry is
`
`
`
`configured to provide the pixels of
`
`each column with data from
`
`the display driver circuitry using the pair of
`
`
`
`
`
`data lines for
`
`
`
`
`that column and wherein the demultiplexer circuitry and display
`
`
`driver circuitry are configured to
`
` a jirst s
`
`operate in:
`
`taLe in which the demultiplexer
`
`
`:a lines and then
`
`:ry provides data
`
`circui
`
`odd da
`
`
`
`from the display driver circuitry to the
`
`leaves the odd data lines floating; and
`
`a second state in which the demultiplexer
`
`circuity provides data
`
`
`from the display driver circuitry to the
`
`4
`
`
`
`
`
`
`

`

`
`
`v n data lines
`even data lines and th n l av s th
`floating.
`
`(Original)
`
`The display defined in claim 7 wherein
`
`:he demultiplexer circuitry and the disp'ay driver circui-
`
`
`further configured to operate in a third state
`
`
`following
`
`:ry are
`
` :he
`
`
`
`
`
`
`
`first and second s
`
`
`:ates in which a given one of
`
`the gate signals
`
`
`on a given one of
`
`she gate lines is asserted
`
`
`
`
`the odd data lines into a
`"irst O
`
`to load data
`
` from
`
`
`
`the rows of pixels associated
`
` from she
`
`
`
`with
`
`
`the given one of
`
`the gate lines and to load data
`
`even
`
`data lines into a second of
`
`the rows 0:
`
`
`
`with
`
`
`the given one of
`
`the
`
`gate lines.
`
`
`
`f pixels associated
`
`(Original)
`
`The display de:
`
`
`
`fined in claim 8 wherein
`
`
`each of
`
`the pixels includes a light—emitting diode.
`
`10.
`
`(Original)
`
`
`
`fined
`in c'aim 8,
`The display de'
`
`wherein
`
`ay driver circuitry is con:
`
`
`
`figured to supply the
`
`
`
`
`
`demultip'
`exer circuitry with
`first and second clock signals.
`
`the disp'
`
`ll.
`
`(Original)
`
`The display de:
`
`fined
`
`in claim 8,
`
`wherein
`
`
`the demultiplexer circuitry comprises a
`
`column.
`
`lz2 demultiplexer in each
`
`
`
`12.
`
`(Original)
`
`
`fined
`The display de'
`
`in claim 11
`
`wherein
`
`the 1:2 demultiplexer in each column has an input and
`
`
`first and
`
`5
`
`

`

`
`second outputs, wherein the first output is coupled to the odd
`
`
`data line of that column and the second output is coupled to the
`
`
`even data line of that column.
`
`13.
`
`
`(Original) The display defined in claim l7 wherein
`
`
`the pixels comprise thin—film transistors having gates controlled
`
`by the gate signals.
`
`14.
`
`(Currently Amended) A display, comprising:
`
`
`rows and columns of pixels;
`
`
`gate lines that are configured to supply gate
`
`signals to the rows;
`
`data lines including alternating odd and even data
`
`
`lines, wherein the data lines include pairs of data lines each
`
`
`
`including one of the odd data lines and an adjacent one of the
`
`
`
`even data lines, wherein each column of the pixels includes a
`
`
`
`respective one of the pairs of the data lines;
`
`demultiplexer circuitry coupled to the data lines;
`
`and
`
`display driver circuitry coupled to the
`
`
`demultiplexer circuitry, wherein the demultip-exer circuitry is
`
`
`
`configured to provide the pixels of each column with data from
`
`
`
` that column and wherein the demultiplexer circuitry and display
`
`the display driver circuitry using the pair of data lines for
`
`
`
`
`driver circuitry are configured to operate in:
`
`6
`
`

`

`
`a first mode in which the demultiplexer
`
`
`
`circuitry provides data from the display driver circuitry to the
`
`
`
`odd data lines; and
`
`
`
`circuity provides data from the display driver circuitry to the
`
`a second mode in which the demultiplexer
`
`
`even data lines; and
`
`data lines and even data lines is loaded into the pixels.
`
`a third mode in which the data on the odd
`
`
`
`15.
`
`
`(Original) The display defined in claim 14 wherein
`
`
`the demultiplexer circuitry and display driver circuitry are
`
`
`configured to:
`
`during the third mode, supply a given gate signal
`
`
`
`
`
`
`
`
`with a given one of the gate lines to load the data on the odd
`
`
`
`data lines and the even data lines into the pixels.
`
`
`(Original) The display defined in claim 14 wherein
`
`
`
`
`
`the
`a given one of the gate lines is associated with a "irst o
`
`16.
`
`
`
`
`rows of pixe's and a second of the rows of pixels, and wherein
`
`
`
`
`the denultip-exer circuitry and display driver circuitry are
`
`
`configured to:
`
`during the third mode, supply a given gate signal
`
`with the given one of the gate lines to load the data on the odd
`
`
`
`
`the rows of pixe's and to load the
`data lines into the "irst o
`
`
`
`
`
`
`
`data on the even data lines into the second of the rows of
`
`
`
`

`

`pixels.
`
`17.
`
`(Original)
`
`
`The display defined in claim 16,
`
`wherein the demultiplexer circuitry comprises a 1:2 demultiplexer
`
`in each column.
`
`18.
`
`(Original)
`
`
`The display defined in claim 17 wherein
`
`
`each of the pixels includes a light—emitting diode.
`
`19.
`
`(Original)
`
`
`The display defined in claim 18,
`
`
`wherein the display driver circuitry is configured to supply the
`
`demultiplexer circuitry with
`
` "IT‘S
`
`c and second clock signals.
`
`
`
`20.
`
`(Original)
`
`
`The display defined in claim 17 wherein
`
`
`the 1:2 demultiplexer in each column has an input and first and
`
`second outputs, wherein the
`
`
`first output is coupled to the odd
`
`
`data line of that column and the second output is coupled to the
`
`even data line 0:
`
`
`
`that column and wherein the pixels comprise
`
`
`thin—film transistors having gates controlled by the gate
`
`
`
`signals.
`
`
`
`

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