DISPLAY DEVICE
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`CROSS REFERENCE TO RELATED APPLICATION
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`[0001] This application claims priority from and the benefit of Korean Patent Application
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`No. 10-2017-0127701, filed on September 29, 2017, which is hereby incorporated by reference
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`for all purposes as if fully set forth herein.
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`BACKGROUND
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`[0002] FIELD
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`[0003] Exemplary embodiments of the invention relate generally to a display device and,
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`more specifically, to a video wall-type display device with reduced or minimized width of non-
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`display area.
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`[0004] DISCUSSION OF THE BACKGROUND
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`[0005] With the advent of the information era, various display devices for displaying an
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`image have emerged as information devices. A liquid crystal display (LCD) device, which is
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`one of the most widely-used flat panel displays, includes two substrates on which field-
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`generating electrodes such as pixel electrodes and a common electrode are formed and a liquid
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`crystal layer which is interposed between the two substrates. The LCD forms an electric field in
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`the liquid crystal layer by applying voltages to the field-generating electrodes to determine the
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`orientation of liquid crystal molecules in the liquid crystal layer and displays an image by
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`controlling the polarization of light incident thereupon using the electric field.
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`[0006] In the meantime, large-sized displays are needed in places such as stadiums,
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`concert halls, shopping malls, and the like where many people gather. However, it is difficult to
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`manufacture large-sized displays as single products because of processing and manufacturing
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`cost problems. Thus, to realize a large-sized display, a video wall capable of displaying a single
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`screen by combining multiple display modules has been developed.
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`[0007] However, a conventional video wall-type display device including a plurality of
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`display modules placed to overlap with one another to display a single image, but may have a
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`problem in that that the bezel of each of the display modules may be viewed as a black band in
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`areas where the display modules overlap with one another.
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`[0008] The above information disclosed in this Background section is only for
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`understanding of the background of the inventive concepts, and, therefore, it may contain
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`information that does not constitute prior art.
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`SUMMARY
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`[0009] Devices constructed according to exemplary embodiments of the invention
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`discloses a display device having a reduced or minimized width of a bezel area between display
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`modules recognizable to a user.
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`[0010] According to one or more embodiments of the invention, a video wall-type
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`display device may include: a plurality of display modules, each of the display modules
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`including: a display area including: a first sub-area, and at least one second sub-area disposed to
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`adjoin and to surround the first sub-area, and a non-display area disposed to surround the display
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`area, wherein the first sub-area may include at least one first pixel unit, the at least one first pixel
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`unit including: a first pixel configured to display a first color, a second pixel configured to
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`display a second color, and a third pixel configured to display a third colors, the first, second,
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`and third colors being different from each another, and wherein the second sub-area may include
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`at least one second pixel unit, the at least one second pixel unit including: the first pixel, the
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`second pixel, and the third pixel; and at least one fourth pixel configured to display a white color.
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`[0011] The at least one fourth pixel of the at least one second pixel unit may be disposed
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`to adjoin the non-display area.
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`[0012] The at least one fourth pixel of the at least one second pixel unit may be disposed
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`between the first pixel, the second pixel, and the third pixel of the at least one second pixel unit
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`and the non-display area.
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`[0013] Each of the first pixel, the second pixel, and the third pixel of the at least one first
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`pixel unit may include two sub-pixels, which display different brightness, respectively.
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`[0014] The first pixel, the second pixel, and the third pixel of the at least one second
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`pixel unit may be configured to display the same brightness.
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`[0015] According to one or more exemplary embodiments of the invention, a Video wall-
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`type display deVice may include: a plurality of display modules, each of the display modules
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`including: a display area configured to display an image, and a non-display area disposed to
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`surround the display area, wherein the display area may include: a first sub-area including at
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`least one first pixel unit, a second sub-area including at least one second pixel unit disposed to
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`adjoin a lower side of the first sub-area, a third sub-area including at least one third pixel unit
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`disposed to adjoin a left side of the first sub-area, a fourth sub-area including at least one fourth
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`pixel unit disposed to adjoin a right side of the first sub-area, and a fifth sub-area including at
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`least one fifth pixel unit disposed to adjoin an upper side of the first sub-area, wherein the at least
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`one first pixel unit may include: a first pixel configured to display a first color, a second pixel
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`configured to display a second color, and a third pixel configured to display a third color, the
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`first, second, and third colors being different from one another, and wherein each of the at least
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`one second pixel unit, the at least one third pixel unit, the at least one fourth pixel unit, and the at
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`least one fifth pixel unit may include: the first pixel, the second pixel, and the third pixel; and at
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`least one fourth pixel configured to display a white color.
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`[0016] The at least one fourth pixel may be disposed to adjoin a lower side of the second
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`sub-area, a left side of the third sub-area, a right side of the fourth sub-area, and an upper side of
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`the fifth sub-area.
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`[0017] The first pixel, the second pixel, and the third pixel of the at least one first pixel
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`unit may be arranged in two rows and three columns, and wherein the first pixel, the second
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`pixel, the third pixel, and the fourth pixel of the at least one second pixel unit, the at least one
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`third pixel unit, the at least one fourth pixel unit, and the at least one fifth pixel unit may be
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`arranged in two rows and three columns.
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`[0018] The first pixel, the second pixel, and the third pixel of the at least one second
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`pixel unit may be sequentially arranged in a first row, and wherein the at least one fourth pixel of
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`the at least one second pixel unit may be sequentially arranged in a second row.
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`[0019] The at least one fourth pixel of the at least one second pixel unit may have the
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`same brightness as the first pixel, the second pixel, and the third pixel disposed in their
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`respective columns.
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`[0020] The at least one third pixel unit, the at least one fourth pixel of the at least one
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`third pixel unit may be sequentially disposed in a first column, and wherein the first pixel, the
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`second pixel, and the third pixel of the at least one third pixel unit may be disposed in second and
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`third columns.
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`[0021] The at least one fourth pixel of the at least one third pixel unit may have the same
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`brightness as the first pixel, the second pixel, and the third pixel adj oined to them in their
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`respective rows.
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`[0022] The first pixel, the second pixel, and the third pixel of the at least one fourth pixel
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`unit may be disposed in first and second columns, and wherein the at least one fourth pixel of the
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`at least one fourth pixel unit may be sequentially disposed in a third column.
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`[0023] The at least one fourth pixel of the at least one fifth pixel unit may be sequentially
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`disposed in a first row, and wherein the first pixel, the second pixel, and the third pixel of the at
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`least one fifth pixel unit may be disposed in a second row.
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`[0024] Areas occupied by the first pixel, the second pixel, the third pixel, and the fourth
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`pixel disposed in the first row of each of the at least one first pixel unit, the at least one second
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`pixel unit, the at least one third pixel unit, and the at least one fourth pixel unit may be larger
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`than areas occupied by the first pixel, the second pixel, the third pixel, and the fourth pixel
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`disposed in the second row of each of the at least one first pixel unit, the at least one second pixel
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`unit, the at least one third pixel unit, and the at least one fourth pixel unit, respectively.
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`[0025] Areas occupied by the first pixel, the second pixel, the third pixel, and the fourth
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`pixel disposed in the first row of the at least one fifth pixel unit may be smaller than areas
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`occupied by the first pixel, the second pixel, the third pixel, and the fourth pixel disposed in the
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`second row of the at least one fifth pixel unit, respectively.
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`[0026] Each of the first pixel, the second pixel, and the third pixel of the at least one first
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`pixel unit may include two sub-pixels, which display different brightness.
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`[0027] Each of the first pixel, the second pixel, and the third pixel of each of the at least
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`one second pixel unit, the at least one third pixel unit, the at least one fourth pixel unit, and the at
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`least one fifth pixel unit may include at least one sub-pixel, which displays a single brightness.
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`[0028] The first color may be a red color, the second color may be a green color, and the
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`third color may be a blue color.
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`[0029] Additional features of the inventive concepts will be set forth in the description
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`which follows, and in part will be apparent from the description, or may be learned by practice of
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`the inventive concepts.
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`[0030] It is to be understood that both the foregoing general description and the
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`following detailed description are exemplary and explanatory and are intended to provide further
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`explanation of the invention as claimed.
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`BRIEF DESCRIPTION OF THE DRAWINGS
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`[0031] The accompanying drawings, which are included to provide a further
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`understanding of the invention and are incorporated in and constitute a part of this specification,
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`illustrate exemplary embodiments of the invention, and together with the description serve to
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`explain the inventive concepts.
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`[0032] FIG. 1 is a schematic view illustrating a video wall-type display device according
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`to an exemplary embodiment of the present invention.
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`[0033] FIG. 2 is a block diagram of a display module according to an exemplary
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`embodiment.
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`[0034] FIG. 3 is a schematic view illustrating the arrangement of pixel units in a display
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`area of a display panel according to an exemplary embodiment.
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`[0035] FIG. 4 is a schematic view illustrating the structure of an exemplary embodiment
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`of a first pixel unit.
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`[0036] FIG. 5 is a schematic view illustrating the structure of an exemplary embodiment
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`of a second pixel unit.
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`[0037] FIG. 6 is a schematic view illustrating the structure of an exemplary embodiment
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`of a third pixel unit.
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`[0038] FIG. 7 is a schematic view illustrating the structure of an exemplary embodiment
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`of a fourth pixel unit.
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`[0039] FIG. 8 is a schematic view illustrating the structure of an exemplary embodiment
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`of a fifth pixel unit.
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`[0040] FIG. 9 is an enlarged layout view of an area A of FIG. 1.
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`[0041] FIG. 10 is a schematic view illustrating the structure of another exemplary
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`embodiment of a fifth pixel unit.
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`DETAILED DESCRIPTION
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`[0042] In the following description, for the purposes of explanation, numerous specific
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`details are set forth in order to provide a thorough understanding of various exemplary
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`embodiments or implementations of the invention. As used herein “embodiments” and
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`“implementations” are interchangeable words that are non-limiting examples of devices or
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`methods employing one or more of the inventive concepts disclosed herein. It is apparent,
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`however, that various exemplary embodiments may be practiced without these specific details or
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`with one or more equivalent arrangements. In other instances, well-known structures and
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`devices are shown in block diagram form in order to avoid unnecessarily obscuring various
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`exemplary embodiments. Further, various exemplary embodiments may be different, but do not
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`have to be exclusive. For example, specific shapes, configurations, and characteristics of an
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`exemplary embodiment may be used or implemented in another exemplary embodiment without
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`departing from the inventive concepts.
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`[0043] Unless otherwise specified, the illustrated exemplary embodiments are to be
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`understood as providing exemplary features of varying detail of some ways in which the
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`inventive concepts may be implemented in practice. Therefore, unless otherwise specified, the
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`features, components, modules, layers, films, panels, regions, and/or aspects, etc. (hereinafter
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`individually or collectively referred to as “elements”), of the various embodiments may be
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`otherwise combined, separated, interchanged, and/or rearranged without departing from the
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`inventive concepts.
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`[0044] The use of cross-hatching and/or shading in the accompanying drawings is
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`generally provided to clarify boundaries between adjacent elements. As such, neither the
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`presence nor the absence of cross-hatching or shading conveys or indicates any preference or
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`requirement for particular materials, material properties, dimensions, proportions, commonalities
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`between illustrated elements, and/or any other characteristic, attribute, property, etc., of the
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`elements, unless specified. Further, in the accompanying drawings, the size and relative sizes of
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`elements may be exaggerated for clarity and/or descriptive purposes. When an exemplary
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`embodiment may be implemented differently, a specific process order may be performed
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`differently from the described order. For example, two consecutively described processes may
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`be performed substantially at the same time or performed in an order opposite to the described
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`order. Also, like reference numerals denote like elements.
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`[0045] When an element, such as a layer, is referred to as being “on,
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`connected to,” or
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`“coupled to” another element or layer, it may be directly on, connected to, or coupled to the other
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`element or layer or intervening elements or layers may be present. When, however, an element
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`or layer is referred to as being “directly on,” “directly connected to,” or “directly coupled to”
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`another element or layer, there are no intervening elements or layers present. To this end, the
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`term “connected” may refer to physical, electrical, and/or fluid connection, with or without
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`intervening elements. Further, the Dl-axis, the D2-axis, and the D3-axis are not limited to three
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`axes of a rectangular coordinate system, such as the X, y, and z — axes, and may be interpreted in
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`a broader sense. For example, the Dl-axis, the D2-axis, and the D3-axis may be perpendicular to
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`one another, or may represent different directions that are not perpendicular to one another. For
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`the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the
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`group consisting of X, Y, and Z” may be construed as X only, Y only, Z only, or any
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`combination of two or more of X, Y, and Z, such as, for instance, XYZ, XYY, YZ, and ZZ. As
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`used herein, the term “and/or” includes any and all combinations of one or more of the
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`associated listed items.
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`[0046] Although the terms “first,” “second,” etc. may be used herein to describe various
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`types of elements, these elements should not be limited by these terms. These terms are used to
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`distinguish one element from another element. Thus, a first element discussed below could be
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`termed a second element without departing from the teachings of the disclosure.
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`[0047] Spatially relative terms, such as “beneath,” “below,
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`under,” “lower,
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`above,”
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`“Upper,
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`over,” “higher,
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`side” (e.g., as in “sidewall”), and the like, may be used herein for
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`descriptive purposes, and, thereby, to describe one elements relationship to another element(s) as
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`illustrated in the drawings. Spatially relative terms are intended to encompass different
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`orientations of an apparatus in use, operation, and/or manufacture in addition to the orientation
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`depicted in the drawings. For example, if the apparatus in the drawings is turned over, elements
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`described as “below” or “beneath” other elements or features would then be oriented “above” the
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`other elements or features. Thus, the exemplary term “below” can encompass both an
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`orientation of above and below. Furthermore, the apparatus may be otherwise oriented (e.g.,
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`rotated 90 degrees or at other orientations), and, as such, the spatially relative descriptors used
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`herein interpreted accordingly.
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`[0048] The terminology used herein is for the purpose of describing particular
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`embodiments and is not intended to be limiting. As used herein, the singular forms,
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`a,
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`an,
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`and “the” are intended to include the plural forms as well, unless the context clearly indicates
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`1ncludes,” and/or “including,”
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`otherwise. Moreover, the terms “comprises,
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`comprising,
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`when used in this specification, specify the presence of stated features, integers, steps,
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`operations, elements, components, and/or groups thereof, but do not preclude the presence or
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`addition of one or more other features, integers, steps, operations, elements, components, and/or
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`groups thereof. It is also noted that, as used herein, the terms “substantially,
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`about,” and other
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`similar terms, are used as terms of approximation and not as terms of degree, and, as such, are
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`utilized to account for inherent deviations in measured, calculated, and/or provided values that
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`would be recognized by one of ordinary skill in the art.
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`[0049] As customary in the field, some exemplary embodiments are described and
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`illustrated in the accompanying drawings in terms of functional blocks, units, and/or
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`modules. Those skilled in the art will appreciate that these blocks, units, and/or modules are
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`physically implemented by electronic (or optical) circuits, such as logic circuits, discrete
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`components, microprocessors, hard-wired circuits, memory elements, wiring connections, and
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`the like, which may be formed using semiconductor-based fabrication techniques or other
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`manufacturing technologies. In the case of the blocks, units, and/or modules being implemented
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`by microprocessors or other similar hardware, they may be programmed and controlled using
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`software (e.g., microcode) to perform various functions discussed herein and may optionally be
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`driven by firmware and/or software. It is also contemplated that each block, unit, and/or module
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`may be implemented by dedicated hardware, or as a combination of dedicated hardware to
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`perform some functions and a processor (e.g., one or more programmed microprocessors and
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`associated circuitry) to perform other functions. Also, each block, unit, and/or module of some
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`exemplary embodiments may be physically separated into two or more interacting and discrete
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`blocks, units, and/or modules without departing from the scope of the inventive
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`concepts. Further, the blocks, units, and/or modules of some exemplary embodiments may be
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`physically combined into more complex blocks, units, and/or modules without departing from
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`the scope of the inventive concepts.
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`[0050] Unless otherwise defined, all terms (including technical and scientific terms) used
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`herein have the same meaning as commonly understood by one of ordinary skill in the art to
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`which this disclosure is a part. Terms, such as those defined in commonly used dictionaries,
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`should be interpreted as having a meaning that is consistent with their meaning in the context of
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`the relevant art and should not be interpreted in an idealized or overly formal sense, unless
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`expressly so defined herein.
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`[0051] FIG. 1 is a schematic view illustrating a video wall-type display device according
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`to an exemplary embodiment.
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`[0052] Referring to FIG. 1, a video wall-type display device DS includes a plurality of
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`display modules PAl, PA2, PA3, and PA4 and an external device MC.
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`[0053] Each of the display modules PAl, PA2, PA3, and PA4 may be connected to the
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`external device MC and may display a video wall image IM based on an image signal received
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`from the external device MC. Each of the display modules PAl, PA2, PA3, and PA4 may
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`display part of the video wall image M by processing a received image signal based on location
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`information, which indicates the relative location of each of the display modules PAl, PA2, PA3,
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`and PA4, and an image signal generated by the external device MC may be provided in parallel
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`and/or in sequence to the display modules PAl, PA2, PA3, and PA4 connected to the external
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`device MC.
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`[0054] FIG. 1 illustrates an example in which the display modules PAl, PA2, PA3, and
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`PA4 receive an image signal from the external device MC, but the present disclosure is not
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`limited thereto. That is, in another example, one of the display modules PAl, PA2, PA3, and
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`PA4 may receive a broadcast signal and may transmit an image signal in parallel and/or in
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`sequence to the other display modules, and each of the display modules PAl, PA2, PA3, and
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`PA4 may display part of a video wall image based on the location information and the image
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`signal.
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`[0055] The configuration of the video wall-type display device DS, particularly, the
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`number of display modules of the video wall-type display device DS and the arrangement of the
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`display modules, are not particularly limited. The video wall-type display device DS may have
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`various arrangements of the display modules PAl, PA2, PA3, and PA4 in accordance with the
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`video wall image M, and the arrangement of the display modules PAl, PA2, PA3, and PA4 is
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`not particularly limited as long as the display modules PAl, PA2, PA3, and PA4 are connected
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`in parallel and/or in sequence.
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`[0056] The structure of the display modules PAl, PA2, PA3, and PA4 of the video wall-
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`type display device D8 will hereinafter be described. Specifically, since the display modules
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`PAl, PA2, PA3, and PA4 have substantially the same structure, the structure of the display
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`modules PAl, PA2, PA3, and PA4 will hereinafter be described, taking one of the display
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`modules PAl, PA2, PA3, and PA4, particularly, the display module PAl.
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`[0057] FIG. 2 is a block diagram of a display module according to an exemplary
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`embodiment.
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`[0058] Referring to FIG. 2, the display module PAl includes a gate driver 110, a data
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`driver 120, a signal controller 130, and a display panel 140.
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`[0059] The display panel 140 may be divided into a display area AA and a non-display
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`area NA. The display area AA may refer to an area where an image is displayed, and the non-
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`display area NA may refer to an area in which an image is not displayed and various components
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`driven to display an image in the display area AA are disposed. The non-display area NA may
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`be arranged to surround the display area AA. In particular, the non-display areas NA of a pair of
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`adjacent display modules may be viewed together as a bezel area, which may appear as a black
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`band.
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`[0060] A plurality of pixel units PXU may be disposed in the display area AA. The pixel
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`units PXU may correspond to minimum units that can display an arbitrary color independently of
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`one another to form an image visible to a user. The pixel units PXU may be arranged in a matrix
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`having m rows and 11 columns.
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`[0061] Each of the pixel units PXU may include a plurality of pixels PX. The
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`arrangement and the colors of the pixels PX may vary and will be described later.
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`[0062] In the display area AA, a plurality of gate lines Gl through Gm may extend in a
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`first direction drl, and a plurality of data lines Dl through Dn may extend in a second direction
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`dr2.
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`[0063] The first direction drl refers to the column direction of the pixel units PXU (i.e.,
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`the direction in which the number of columns increases). The second direction dr2, which is a
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`direction intersecting the first direction drl, refers to the row direction of the pixel units PXU
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`(i.e., the direction in which the number of rows increases).
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`[0064] The gate lines G1 through Gm may receive gate signals from the gate driver 110,
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`and the data lines Dl through Dn may receive data signals from the data driver 120. Each of the
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`pixels PX may be surrounded by some of the gate lines Gl through Gm and some of the data
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`lines Dl through Dn, but the present disclosure is not limited thereto. That is, alternatively, the
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`pixels PX may all be surrounded at the same time by some of the gate lines Gl through Gm and
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`some of the data lines Dl through Dn.
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`[0065] Each of the pixels PX may uniquely display one of primary colors to implement a
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`color display. Examples of the primary colors include red, green and blue colors. Also, some of
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`the pixels PX may display a white color. Pixels PX displaying a red color will hereinafter be
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`referred to as red pixels, pixels PX displaying a green color will hereinafter be referred to as
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`green pixels, pixels PX displaying a blue color will hereinafter be referred to as blue pixels, and
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`pixels PX displaying a white color will hereinafter be referred to as white pixels. By grouping
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`red, green, blue, and white pixels and controlling the brightness of the red, green, blue, and white
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`pixels, an arbitrary color other than red, green, and blue colors can be displayed. The
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`arrangement of the pixels PX may vary depending on whether the pixels PX are red, green, or
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`blue pixels or white pixels and will be described later.
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`[0066] The signal controller 130 may receive an image signal from the external device
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`MC and controls the gate driver 110 and the data driver 120. The signal controller 130 may
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`receive first video data DATAl and input control signals CONTl for controlling the display of
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`the first video data DATAl, from the external device MC and may output gate driver control
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`signals CONT2, control signals CONT3, and second video data DATAZ. The first image data
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`DATAl includes information on the gray levels of the pixels PX and may be divided into
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`frames.
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`[0067] The input control signals CONTl are transmitted to the signal controller 130, and
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`may include, for example, a vertical synchronization signal, a horizontal synchronization signal,
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`a main clock, and a data enable signal, but the present disclosure is not limited thereto. That is,
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`the input control signals CONTl may also include various types of signals other than those set
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`forth herein, and each of the vertical synchronization signal, the horizontal synchronization
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`signal, the main clock, and the data enable signal may be omitted. The signal controller 130 may
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`be implemented by an integrated circuit (IC).
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`[0068] The gate driver control signals CONT2 may be signals for controlling the
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`operation of the gate driver 110 and may be generated by the signal controller 130. The gate
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`driver control signals CONT2 may include a scan initiation signal and a clock signal, but the
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`present disclosure is not limited thereto. The gate driver 110 may generate gate signals, which
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`are capable of activating the pixels PX, in accordance with the gate driver control signals
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`CONT2 and may provide the generated gate signals to the gate lines Gl through Gn. The gate
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`driver 110 may be implemented by an IC and may be realized as a circuit using an amorphous
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`silicon gate (ASG) that uses an amorphous silicon (a-Si) thin-film transistor (TFT), an oxide
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`semiconductor, a crystalline semiconductor, or a polycrystalline semiconductor.
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`[0069] The data driver control signals CONT3 may be signals for controlling the
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`operation of the data driver 120 and may be generated by the signal controller 130. The data
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`driver 120 may generate data signals in accordance with the data driver control signals CONT3
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`and may provide the generated data signals to the data lines Dl through Dn. The data driver 120
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`may be implemented by an IC.
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`[0070] The gate driver 110, the data driver 120, and the signal controller 130 may be
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`disposed in the non-display area NA.
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`[0071] In exemplary embodiments, the gate driver 110, the data driver 120, and the
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`signal controller 130, and/or one or more components thereof, may be implemented via one or
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`more general purpose and/or special purpose components, such as one or more discrete circuits,
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`digital signal processing chips, integrated circuits, application specific integrated circuits,
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`microprocessors, processors, programmable arrays, field programmable arrays, instruction set
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`processors, and/or the like.
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`[0072] According to one or more exemplary embodiments, the features, functions,
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`processes, etc., described herein may be implemented via software, hardware (e.g., general
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`processor, digital signal processing (DSP) chip, an application specific integrated circuit (ASIC),
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`field programmable gate arrays (FPGAs), etc.), firmware, or a combination thereof. In this
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`manner, the gate driver 110, the data driver 120, and the signal controller 130, and/or one or
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`more components thereof may include or otherwise be associated with one or more memories
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`(not shown) including code (e.g., instructions) configured to cause the gate driver 110, the data
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`driver 120, and the signal controller 130, and/or one or more components thereof to perform one
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`or more of the features, functions, processes, etc., described herein.
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`[0073] The memories may be any medium that participates in providing code to the one
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`or more software, hardware, and/or firmware components for execution. Such memories may be
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`implemented in any suitable form, including, but not limited to, non-volatile media, volatile
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`media, and transmission media. Non-volatile media include, for example, optical or magnetic
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`disks. Volatile media include dynamic memory. Transmission media include coaxial cables,
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`copper wire and fiber optics. Transmission media can also take the form of acoustic, optical, or
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`electromagnetic waves. Common forms of computer-readable media include, for example, a
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`floppy disk, a flexible disk, hard disk, magnetic tape, any other magnetic medium, a compact
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`disk-read only memory (CD-ROM), a rewriteable compact disk (CD-RW), a digital Video disk
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`(DVD), a rewriteable DVD (DVD-RW), any other optical medium, punch cards, paper tape,
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`optical mark sheets, any other physical medium with patterns of holes or other optically
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`recognizable indicia, a random-access memory (RAM), a programmable read only memory
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`(PROM), and erasable programmable read only memory (EPROM), a FLASH-EPROM, any
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`other memory chip or cartridge, a carrier wave, or any other medium from which information
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`may be read by, for example, a controller/processor.
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`[0074] The arrangement of pixel units PXU, and the arrangement of pixels PX in each of
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`the pixel units PXU, which are disposed in the display area AA, will hereinafter be described.
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`[0075] FIG. 3 is a schematic View illustrating the arrangement of pixel units in a display
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`area of a display panel according to an exemplary embodiment, FIG. 4 is a schematic View
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`illustrating the structure of an exemplary first pixel unit, FIG. 5 is a schematic View illustrating
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`the structure of an exemplary second pixel unit, FIG. 6 is a schematic View illustrating the
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`structure of an exemplary third pixel unit, FIG. 7 is a schematic View illustrating the structure of
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`an exemplary fourth pixel unit, and FIG. 8 is a schematic View illustrating the structure of an
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`exemplary fifth pixel unit.
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`[0076] Referring to FIG. 3, the display area AA includes a first sub area SAl, a second
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`sub area SA2, a third sub area SA3, a fourth sub area SA4, and a fifth sub-area SA5. In each of
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`the first, second, third, fourth and fifth sub-areas SAl, SA2, SA3, SA4, and SAS, a plurality of
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`pixel units may be disposed, and the structure of the plurality of pixel units included in each of
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`the first, second, third, fourth and fifth sub-areas SAl, SA2, SA3, SA4, and SAS may differ from
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`one sub-area to another sub-area.
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`[0077] The first sub-area SAl may be disposed at the center of the display area AA and
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`may be surrounded by the second, third, fourth and fifth sub-areas SA2, SA3, SA4, and SAS.
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`That is, the second, third, fourth and fifth sub-areas SA2, SA3, SA4, and SAS may be disposed
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`along the sides of the display area AA.
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`[0078] In the first sub-area SAl, a plurality of first pixel units PXUl may be arranged in
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`a matrix of a plurality of rows and a plurality of columns. Each of the first pixel units PXUl
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`may include a plurality of