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MEMORY SYSTEM ARCHITECTURES USING A SEPARATE SYSTEM CONTROL PATH OR CHANNEL FOR PROCESSING ERROR INFORMATION

15/865,250 | U.S. Patent Application

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Location ELECTRONIC
Filed Jan. 8, 2018
Examiner JOSEPH R KUDIRKA
Class 714
Art Group 2114
Patent No. 10,824,499
Case Type Utility - 714/006100
Status Patented Case
Parent 14/678,977 Patented
Parent 62/75,231 Expired
Parent 14/594,049 Abandoned
Parent 62/39,396 Expired
Parent 14/678,968 Patented
Parent 62/57,199 Expired
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Last Updated: 3 years, 6 months ago
Date # Transaction