UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`.
`SAMSUNG ELECTRONICS CoO., LTD.,
`MICRON TECHNOLOGY,INC., and SK HYNIX INC.
`Petitioners
`
`Vv.
`
`ELM 3DS INNOVATIONS,LLC,
`Patent Owner
`
`Case IPR2016-00387
`Patent 8,841,778
`
`PETITIONERS’ NOTICE OF APPEAL
`
`fiwig!i
`cuPEDGol
`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`.
`SAMSUNG ELECTRONICS CoO., LTD.,
`MICRON TECHNOLOGY,INC., and SK HYNIX INC.
`Petitioners
`
`Vv.
`
`ELM 3DS INNOVATIONS,LLC,
`Patent Owner
`
`Case IPR2016-00387
`Patent 8,841,778
`
`PETITIONERS’ NOTICE OF APPEAL
`
`fiwig!i
`cuPEDGol
`
`
`
`Case IPR2016-00387
`
`Pursuant to 37 C.F.R § 90.2(a) and 35 U.S.C.§ 142, Petitioners Samsung
`
`Electronics Co., Ltd., Micron Technology, Inc., and SK hynixInc.(“Petitioners”’)
`
`hereby respectfully give Notice that they appeal the Patent Trial and Appeal
`Board’s (“Board”) Final Written Decision, dated June 23, 2017 (Paper 63),
`‘concluding that claims1, 2, 8, 14, 31, 32, 44, 46, and 52-54 ofUS. Patent No.
`
`8,841,778 have not been shown to be unpatentable to the United States Court of
`
`Appeals for the Federal Circuit, and from all underlying orders, decisions, rulings
`
`and opinionsthat are adverse to Petitioners, including, withoutlimitation, those.
`
`within the Decision on Institution ofInter Partes Review, entered June 30, 2016
`
`(Paper 13).
`
`|
`
`For the limited purpose of providing the Director with the information
`requested in 37 C.F.R § 90.2(a)(3)(i), issues on Petitioners’ appeal may include,
`
`but are not limited to, the construction of the “substantially flexible” terms,
`
`including the Board’s constructionof these terms; the Board’s interpretation ofits
`
`construction and application ofits construction to the prior art; the Board’s
`
`determination of patentability of claims 1, 2, 8, 14, 31, 32, 44, 46, and 52-54 of
`
`U.S. Patent No. 8,841,778 under 35 U.S.C § 103, which is factually incorrect, not
`
`supported by law or substantial evidence, was not the result of a logical and
`rational process, and is incorrect as a matter oflaw; any findings supporting that
`
`determination, including findings regarding motivation to combine and a
`
`
`
`Case IPR2016-00387
`
`reasonable expectation of success; the Board’s failure to consider evidence of
`
`record fully and properly; the Board’s legal errors in undertaking its obviousness
`
`analysis; the Board’s findings that conflict with the evidence of record and are not
`
`supported by substantial evidence; any finding or determination supporting or
`
`related to those issues; and any other issues decided adversely to Petitioners in any
`
`orders, decisions, rulings and opinions.
`
`Simultaneous with this submission, a copy of the Notice ofAppealis being.
`
`filed electronically with the Patent Trial and Appeal Board. In addition, a copy of
`
`this Notice ofAppeal, along with the required docketing fees, are being filed
`
`electronically with the Clerk’s Office for the United States Court of Appeals for
`
`the Federal Circuit.
`
`—
`
`Date:
`
`_August 24, 2017
`
`Respectfully submitted,
`
`/Naveen Modi/
`Naveen Modi (Reg. No. 46,224)
`Paul Hastings LLP
`875 15th,St. N.W.
`Washington, D.C., 20005
`Tel.: 202.551.1700
`Fax: 202.551.1705
`PH-Samsung-ELM-IPR@paulhastings.com
`
`Attorneyfor Petitioners
`
`
`
`Case IPR2016-00387
`
`CERTIFICATE OF SERVICE
`
`In accordance with 37 CFR § 90.2(a)(1) and § 104.2, I herebycertify that on
`
`August 24, 2017,in addition to being filed electronically through the Board’s E2E
`
`System,theoriginal version of the foregoing Petitioners’ Notice of Appeal was
`
`filed by hand on the Directorof the United States Patent and Trademark Office, at
`
`the following address:
`
`Director of the United States Patent and Trademark Office
`c/o Office of the General Counsel
`Madison Building East, 10B20
`600 Dulany Street
`_ Alexandria, VA 22314-5793
`
`CERTIFICATE OF SERVICE
`
`[herebycertify that on August 24, 2017,a true and correct copy ofthe
`
`foregoing Petitioners’ Notice of Appeal, along with a copyof the Final Written
`
`| Decision, was filed electronically with the Clerk’s Office of the United States
`
`Court of Appealsfor the Federal Circuit, at the following address:
`
`United States Court of Appeals for the Federal Circuit
`717 Madison Place, N.W., Suite 401
`Washington, DC 20005
`
`
`
`CERTIFICATE OF SERVICE
`
`Case IPR2016-00387
`
`Pursuant to 37 CFR § 42.6(e)(1), the undersignedcertifies that on August
`
`24, 2017, a complete and entire copy ofthe Petitioners’ Notice of Appeal was
`
`provided via email, to the Patent Ownerby serving the email correspondence
`
`addresses of record as follows:
`
`William A. Meunier
`Michael T. Renaud
`Mintz, Levin, Cohn, Ferris,
`Glovsky and Popeo,P.C.
`One Financial. Center
`Boston, MA 02111
`
`James Carmichael
`Carmichael IP, PLLC
`8000 Towers Crescent Drive, 13" Floor
`Tysons Corner, VA 22182
`
`Email: WAMeunier@mintz.com
`Email: mtrenaud@mintz.com
`Email: mcnewman@mintz.com
`Email: ELM 3DS JPRs@mintz.com
`Email:
`jim@carmichaelip.com
`
`/Naveen Modi/
`Naveen Modi
`
`
`
`Trials@uspto.gov
`571-272-7822
`
`Paper 63
`Entered: June 23, 2017
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`SAMSUNG ELECTRONICSCO., LTD.,
`MICRONTECHNOLOGY,INC., and SK HYNIX,INC.,
`Petitioner,
`
`Vv.
`
`ELM 3DS INNOVATIONS, LLC,
`Patent Owner.
`
`Case IPR2016-00386 Patent 8,653,672 B2
`Case IPR2016-00387 Patent 8,841,778 B2
`Case JPR2016-00388 Patent 7,193,239 B2
`
`Before GLENN J. PERRY, BARBARA A. BENOIT,and
`FRANCESL. IPPOLITO, Administrative Patent Judges.
`
`BENOIT, Administrative Patent Judge.
`
`DECISION
`Final Written Decision
`35 U.S.C. § 318(a) and 37 CER. § 42.73
`
`
`
`IPR2016-00386 Patent 8,653,672 B2 IPR2016-00387 Patent 8,841,778 B2
`IPR2016-00388 Patent 7,193,239 B2
`
`I, INTRODUCTION
`
`These inter partes reviews, instituted pursuant to 35 U.S.C. § 314,
`
`challenge the patentability of certain claims of U.S. Patent
`
`Nos. 8,653,672 B2 (“the °672 patent’), 8,841,778 B2 (“the ’778 patent”),
`and 7,193,239 B2 (“the *239 patent),! each of which shares the same written
`description. All of the challenged patents are owned by Elm 3DS
`
`Innovations, LLC (“Patent Owner”). We havejurisdiction under 35 U.S.C.
`§ 6. This Final Written Decision is entered pursuant to 35 U.S.C. § 318(a)
`and 37 C.F.R. § 42.73. This Decision is issued concurrently with a Final
`
`Written Decision in IPR2016-00393, which also challenges the patentability
`of claims 10-12, 18-20, 60-63, 67, 70-73, and 77 ofthe ’239 patent.
`For the reasons discussed herein, Petitioner has not shown by a
`
`preponderance ofthe evidence that the challenged claimsin any of the
`
`challenged patents are unpatentable.
`
`A. Procedural History
`
`In IPR2016-00386, Petitionerfiled a Petition seeking inter partes
`review ofcertain claims ofthe ’672 patent and weinstituted a review.
`IPR386-Paper 1 (“IPR386-Petition” or “IPR386-Pet.”); IPR386-Paper 14
`(“IPR386-Institution Decision” or “IPR386-Inst. Dec.”). In IPR2016-00387,
`
`Petitioner filed a Petition seeking inter partes review ofcertain claims of the
`
`°778 patent, and weinstituted a review. IPR387-Paper 1 (“IPR387-Petition”
`
`' The challenged patent is Exhibit 1001 in each proceeding. Citations may
`be preceded by “IPR386”to designate IPR2016-00386, “IPR387”to
`designate IPR2016-00387, or “IPR388” to designate IPR2016-00388.
`2
`
`
`
`IPR2016-00386 Patent 8,653,672 B2 IPR2016-00387 Patent 8,841,778 B2
`IPR2016-00388 Patent 7,193,239 B2
`
`or “IPR387-Pet.”); IPR387-Paper 13 (“IPR387-Institution Decision” or
`“IPR387-Inst. Dec.”). In IPR2016-00388,Petitioner filed a Petition seeking
`interpartes review ofcertain claims ofthe ’239 patent, and weinstituted a
`review. IPR388-Paper 4 (“IPR388-Petition”or “IPR388-Pet.”);
`|
`IPR388-Paper11 (“IPR388-Institution Decision” or “IPR388-Inst. Dec.”).
`In our Decisionsto Institute, we did not agree with Patent Owner that the
`Petitions were barred under 35 U.S.C. § 315(b) because, according to Patent
`Owner, the Office lacked authority to treat certain days on which the Office
`experienced an emergencysituation, such that manyof its online and
`information technology systems were shut down, asfederal holidays.
`IPR386-Inst. Dec. 4-5; IPR387-Inst. Dec. 3-4; IPR388-Inst. Dec. 4—5.
`
`Patent Ownerhas notraised this issue subsequentto institution in any of the
`
`three proceedings.
`In responseto an orderto clarify the claim construction standard to be
`applied in each proceeding (IPR386-Paper 18; IPR387-Paper 16; IPR388-
`Paper 14), Patent Ownercertified that each of the challenged patents in these
`three proceedings would expire prior to the deadline for issuinga final
`written decision and, therefore, contendedthat the claim construction
`standardset forth in Phillips v. AWH Corp., 415 F.3d 1303 (Fed. Cir. 2005),
`should be applied (IPR386-Paper 23; IPR387-Paper 21; IPR388-Paper19).
`Petitioner concurred with Patent Owner’s contention. IPR386-Paper 25; .
`
`IPR387-Paper 23; IPR388-Paper 21. We agreed with the parties and issued
`an order indicating that the Phillips claim construction standard should be
`
`
`
`IPR2016-00386 Patent 8,653,672 B2 IPR2016-00387 Patent 8,841,778 B2
`IPR2016-00388 Patent 7,193,239 B2
`
`applied in each of these three proceedings. IPR386-Paper 28; IPR387-
`
`Paper 26; IPR388-Paper 24.
`
`Subsequentto institution, Patent Ownerfiled a Patent Owner
`
`Response to the Petition in each case. IPR386-Paper 55 (“IPR386-PO
`
`Resp.”); IPR387-Paper 50 (“IPR387-PO Resp.”); IPR388-Paper 47
`
`(“IPR388-PO Resp.”). Petitioner filed a Reply to Patent Owner’s Response
`
`to the Petition in each case. IPR386-Paper 61 (“IPR386-Pet. Reply”);
`
`IPR387-Paper 56 (“IPR387-Pet. Reply”); IPR388-Paper 53 (“IPR388-Pet.
`
`Reply”).
`
`Weheld a consolidated hearing for the inter partes reviews. A
`transcript ofthe oral hearing is included in the record of each proceeding.
`IPR3 86-Paper 67; IPR3 87-Paper 62; IPR388-Paper 59 (collectively “Tr.”).
`
`B. Related Matters
`
`Asrequired by 37 C.F.R. § 42.8(b)(2), each party identifies various
`| judicial or administrative matters that would affect or be affected by a
`decision in this proceeding. IPR386-Pet. 1-2; IPR386-Paper 9 (Patent
`Owner’s Mandatory Notices); IPR387-Pet. 1-2: IPR387-Paper 8 (Patent
`Owner’s Mandatory Notices); IPR388-Pet. 1-2; IPR388-Paper 7 (Patent
`Owner’s Mandatory Notices). Petitioner indicates that the challenged
`patents are involved in the following United States District Court
`
`proceedings: Elm 3DS Innovations, LLC v. Samsung Elecs. Co., No. 1:14-
`
`cv-01430 (D. Del.); Elm 3DS Innovations, LLC v. Micron Tech., Inc.,
`
`No. 1:14-cv-01431 (D. Del.); and Llm 3DS Innovations, LLC v. SK Hynix
`
`Inc., No. 1:14-cv-01432 (D. Del.).
`
`
`
`IPR2016-00386 Patent 8,653,672 B2 IPR2016-00387 Patent 8,841,778 B2
`IPR2016-00388 Patent 7,193,239 B2
`
`The °239 patent, which is challenged in IPR2016-00388,also is the
`subject of inter partes review IPR2016-00393. Additionally, patents related
`to the challengedpatent are the subjects of petitionsfiled in IPR2016-00389
`(U.S. Patent No. 8,035,233); IPR2016-00390 (U.S. Patent No. 8,629,542);
`IPR2016-00391 (U.S. Patent No.8,796,862); IPR2016-00394 (U.S. Patent
`No. 8,410,617); IPR2016-00395 (US Patent No. 7,504,732); 1PR2016-00687
`(U.S. Patent No. 8,928,119); IPR20 16-00691 (U.S. Patent No. 7,474,004);
`IPR2016-00708 (U.S. Patent No. 8,907,499); IPR2016-00770 (U.S.Patent
`No.8,907,499); and IPR2016-00786 (U.S. Patent No. 8,933,570). Wealso
`note that Petitionerfiled two additional petitions requesting inter partes
`review of U.S. Patent No. 8,791,581 (IPR2016-00703 and IPR2016-00706)
`
`for which wedid notinstitute a review.
`
`C. The Written Description ofthe Challenged Patents’
`The challenged patents identify Glenn J. Leedy as sole inventor ofthe
`claimed subject matter. The patents each claim the benefit of the filing date
`of April 4, 1997 throughaseries of continuationor divisional applications.
`Accordingly, the patents share a common written description.
`Thepatents generally relate to a three-dimensional structure (3DS)
`for integrated circuits that allows for physical separation of memory circuits
`and control logic circuits on different layers. Ex. 1001, Abstract. Figure la
`is reproduced below.
`
`2 For brevity, citations to the written description refer to the °672 patent at
`issue in JPR2016-00386.
`
`5
`
`
`
`IPR2016-00386 Patent 8,653,672 B2 IPR2016-00387 Patent 8,841,778 B2
`IPR2016-00388 Patent 7,193,239 B2
`
`
`
`Figure la
`
`Figure 1a shows 3DS memory device 100 having a stack of
`
`integrated circuit layers with a “fine-grain inter-layer vertical interconnect”
`
`betweenall circuit layers. Id. at 3:64-67. Layers shown include controller
`
`circuit layer 101 and memory arraycircuit layers 103. Jd. at 4:17-19. The
`
`written description discloses that “each memory array circuit layer is a
`
`thinned and substantially flexible circuit with net low stress, less than 50 um
`
`and typically less than 10 um in thickness.” Jd. at 4:22-24. The written
`
`description further discloses that the “thinned (substantially flexible)
`
`substratecircuit layers are preferably made with dielectrics in low stress
`(less than 5x 108 dynes/cm) such as lowstress silicon dioxide and silicon
`
`nitride dielectrics as opposed to the more commonly used higherstress
`
`dielectrics of silicon oxide andsilicon nitride used in conventional memory
`
`circuit fabrication.” Id. at 8:45—50.
`
`Figure 1b is reproduced below.
`
`
`
`IPR2016-00386 Patent 8,653,672 B2 IPR2016-00387 Patent 8,841,778 B2
`_IPR2016-00388 Patent 7,193,239 B2
`
`
`
`LAUSK?
`(PLLLLLA V2PSLLL1LLL
`lot
`
`
`x
`
`PL2222) Yee 22 eLLLg
`?
`STI ZiLtli LittllL
`
`
`
`
`
`LOOhe LLOLLLLLili ffLLL
`
`[PLLLLLA
`5
`(LELLLLLLALLLLLL
`
`
`
`Figure lb
`
`Figure 1b of written description showsa cross-section of a 3DS
`integrated circuit with metal bonding interconnect between thinnedcircuit
`layers. Id. at 3:38-40. Bond and interconnect layers 105a, 105b, 105c are
`shown between circuit layers 103a and 103b. Id. at Fig. 1b. The written
`description discloses that pattern 107a, 107b, 107c in the bond and
`interconnect layers 105a, 105b, 105c defines the vertical interconnect
`contacts betweenthe integrated circuit layers and servesto electrically
`isolate these contacts from each other and the remaining bond material. Id.
`
`at 4:11-15. Additionally, the written description teaches that the pattern
`takes the form of voidsordielectric filled spaces in the bondlayers. Jd. at
`
`4:15-16.
`
`
`
`IPR2016-00386 Patent 8,653,672 B2 IPR2016-00387 Patent 8,841,778 B2
`IPR2016-00388 Patent 7,193,239 B2
`
`Further, the writtendescription teaches that the “term fine-grained
`
`inter-layer vertical interconnect is used to mean electrical conductors that
`
`pass througha circuit layer with or without an intervening device element
`
`and havea pitch of nominally less than 100 um... .” Jd. at 3:67-4:4. The
`
`'
`
`fine-grained inter-layer vertical interconnect functions to bond together
`
`variouscircuit layers. Id. at 4:5—7.
`
`D. Instituted Grounds of Unpatentability
`Weinstituted interpartes reviews ofthe challenged patents based on
`Petitioner’s asserted grounds involving the following references:? (i) U.S.
`Patent No. 5,202,754, issued April 13, 1993 (Ex. 1004, “Bertin ’754”);
`(ii) U.S. Patent No. 5,354,695, issued Oct. 11, 1994 (Ex. 1006,
`©
`“Leedy ’695”); (iii) U.S. Patent No. 5,162,251, issued Nov. 10, 1992 (Ex.
`
`1005, “Poole”); (iv) Yu,et al., Real-Time Microvision System with Three-
`
`Dimensional Integration Structure, Proceedings of the 1996 IEEE/SICE/RSJ
`
`International Conference on Multisensor Fusion and Integration for
`
`Intelligent Systems, 1996 (Ex. 1009, “Yuw”); and (v) U.S. Patent No.
`
`5,627,106, issued May 6, 1997 (Ex. 1008, “Hsu”).
`
`Weinstituted inter partes reviews of the challenged patents based on
`35 U.S.C. § 1034 on theparticular following grounds:
`
`3 The priorart references have the same exhibit numbersin each proceeding.
`* The Leahy-Smith America Invents Act (“AIA”), Pub. L. No. 112-29, 125
`Stat. 284, 287-88 (2011), revised 35 U.S.C. § 103, effective March 16,
`2013. Because the challenged patent was filed before March 16, 2013, we
`refer to the pre-AIA version of § 103 in this decision.
`8
`
`
`
`IPR2016-00386 Patent 8,653,672 B2 IPR2016-00387 Patent 8,841,778 B2
`IPR2016-00388 Patent 7,193,239 B2
`
`Case
`
`
`
`
`
`
`
`
`
`
`Claims Challenged
`Claims 17, 18, 22, 84, 95,
`IPR2016-00386 Bertin 754, Poole,
`“| 129-132, 145, 146, and 152
`and Leedy 695
`
`IPR2016-00386|Yu and Leedy *695 Claims 17, 18, 22, 84, 95,
`_
`129-132,145, 146, and 152
`
`IPR2016-00387|Bertin 154 and Claims1, 2, 8, 14, and 52
`Leedy ’695
`
`IPR2016-00387|Bertin ’754, Poole, Claims2, 8, 31, 32, 44, 46,
`and Leedy 7695
`and 52-54
`Claims1, 2, 8,.14, 31, 32,
`
`IPR2016-00387
`
` PR?O16-00387 Hsu andLeedy °695|4446, and 52-54
`Claims 10—12, 18-20, 60-
`>
`IPR2016-00388
`Yu and Leedy "695|6367, 70-73, and 77
`
`>
`
`IPR386-Inst. Dec. 40; IPR387-Inst. Dec. 34; IPR388-Inst. Dec. 28.
`
`II. DISCUSSION?
`
`A. Principles ofLaw
`1. Principles of Claim Construction
`Thepatents challengedin these three proceedings have expired. See
`IPR386-Paper 23 (Patent Owner’s Notice of Patent Expiration indicating the
`°672 patent would expire on April 4, 2017); IPR387-Paper 21 (indicating
`that the °778 patent would expire on Apmil 4, 2017), IPR388-Paper 19
`indicating that the 239 patent would expire on April 4, 2017. For claims of
`an expiredpatent, the Board’s claim construction analysis is similar to that
`of a district court. See In re Rambus, Inc., 694 F.3d 42, 46 (Fed. Cir. 2012);
`see, e.g., IPR386-Paper 28 (determininga district court-type claim
`
`5 The discussion in this section, unless otherwise noted, addresses issues
`relevant to IPR2016-00386, IPR2016-00387, and IPR2016-00388.
`9
`
`
`
`IPR2016-00386 Patent 8,653,672 B2 IPR2016-00387 Patent 8,841,778 B2
`IPR2016-00388 Patent 7,193,239 B2
`
`construction approach following Phillips is to be applied during IPR2016-
`IPR00386, IPR2016-00387, and IPR2016-00388). In this context, claim
`
`terms “are generally given their ordinary and customary meaning”as
`
`understood by a person ofordinary skill in the art in question at the time of —
`
`the invention. Phillips v. AWH Corp., 415 F.3d 1303, 1312-13 (Fed.Cir.
`
`2005) (en banc). “In determining the meaning of the disputed claim
`
`limitation, we look principally to the intrinsic evidence of record, examining
`
`the claim languageitself, the written description, and the prosecution
`
`history, if in evidence.” DePuy Spine, Inc. v. Medtronic Sofamor Danek,
`
`Inc., 469 F.3d 1005, 1014 (Fed. Cir. 2006) (citing Phillips, 415 F.3d at
`1312-17). Extrinsic evidence, such as expert testimony anddictionary
`definitions, can be helpful but is “less significant than the intrinsic record in
`determining the legally operative meaning of claim language.” Phillips, 415
`F.3d at 1317. Also, extrinsic evidence is to be considered withinthe context
`of the intrinsic evidence. Jd. A claim term may be construed contrary to its
`ordinary and customary meaning only “under two circumstances: ‘(1) when
`a patentee sets out a definition andacts as [its] own lexicographer, or (2)
`
`whenthe patentee disavowsthe full scope of a claim term either in the
`
`specification or during prosecution.”” Aventis Pharma S.A. v. Hospira, Inc.,
`
`675 F.3d 1324, 1330 (Fed. Cir. 2012) (quoting Thorner v. Sony Computer
`
`Entm’t Am. LLC, 669 F.3d 1362, 1365 (Fed. Cir. 2012)); Hill-Rom Svcs, Inc.
`
`v. Stryker Corp., 755 F.3d 1367, 1371 (Fed. Cir. 2014).
`In each proceeding, we construe the challenged claims according to
`these principles.
`
`10
`
`
`
`IPR2016-00386 Patent 8,653,672 B2 IPR2016-00387 Patent 8,841,778 B2
`IPR2016-00388 Patent 7,193,239 B2
`
`—
`
`2. Principles ofLaw Concerning Demonstrating Unpatentability
`To prevail in challenging Patent Owner’s claims, Petitioner must
`demonstrate by a preponderanceofthe evidencethat the claims are
`unpatentable. 35 U.S.C. § 316(e); 37 C.F.R. § 42.1(d). “In an [inter partes
`review], the petitioner has the burden from the onset to show with
`.
`particularity why the patent it challenges is unpatentable.” Harmonic Inc. v.
`Avid Tech., Inc., 815 F.3d 1356, 1363 (Fed. Cir. 2016)(citing 35 U.S.C.
`§ 312(a)(3) (requiring inter partes review petitionsto identify “with
`particularity .
`.
`. the evidence that supports the groundsfor the challenge to
`each claim”)). This burden nevershifts to Patent Owner. See Dynamic
`Drinkware, LLC v. Nat’l Graphics,Inc., 800 F.3d 1375, 1378 (Fed.
`Cir. 2015) (citing Tech. Licensing Corp. v. Videotek, Inc., 545 F.3d 1316,
`1326-27 (Fed. Cir. 2008)) (discussing the burden of proofin inter partes
`review). Furthermore, Petitioner cannotsatisfy its burden ofproving
`obviousness by employing “mere conclusory statements.” In re Magnum
`Oil Tools Int’l, Ltd., 829 F.3d 1364, 1380 (Fed. Cir. 2016).
`Petitioner asserts that certain claims ofthe challenged patents are |
`unpatentable under 35 U.S.C. § 103(a) as obvious over various combinations
`of references. A claim is unpatentable under 35 U.S.C. § 103(a) if the
`differences between the claimed subject matter and theprior art are such that
`the subject matter, as a whole, would have been obviousat the time of the
`invention to a person havingordinary skill in the art. KSR Int'l Co.v.
`Teleflex, Inc., 550 U.S. 398, 406 (2007). The question of obviousnessis
`resolved onthe basis of underlying factual determinations including: (1) the
`
`c
`
`11
`
`
`
`IPR2016-00386 Patent 8,653,672 B2 IPR2016-00387 Patent 8,841,778 B2
`IPR2016-00388 Patent 7,193,239 B2
`
`scope and content of the priorart; (2) any differences between the claimed
`
`subject matter and theprior art; (3) the level of ordinary skill in the art; and
`
`(4) objective evidence of nonobviousness. Graham v. John Deere Co., 383
`
`U.S. 1, 17-18 (1966). Consideration of the Graham factors “helps inform
`
`the ultimate obviousness determination.” Apple v. Samsung Elecs. Co., 839
`
`F.3d 1034, 1048 (Fed. Cir. 2016) (en banc).
`
`B. Level ofOrdinary Skill
`
`In determining whether an invention would have been obviousat the
`
`. time it was made, 35 U.S.C. § 103 requires us to resolve the level of
`ordinary skill in the pertinentart at the time of the invention. Graham, 383
`
`U.S. at 17. “The importanceofresolving the level of ordinary skill in the art
`
`lies in the necessity of maintaining objectivity in the obviousnessinquiry.”
`
`Ryko Mfg. Co. v. Nu-Star, Inc., 950 F.2d 714, 718 (Fed. Cir. 1991). The
`
`. person of ordinary skill in the art is a hypothetical person who is presumed
`to have known the relevantart at the time of the invention. In re GPAC,
`Inc., 57 F.3d 1573, 1579 (Fed. Cir. 1995). Factors that may be consideredin
`
`determiningthe level of ordinary skill in the art include, but are not limited
`
`to, the types of problems encountered inthe art, the sophistication of the
`
`technology, and educationallevel of active workers in the field. GPAC, 57
`F.3d at 1579. In a given case, one or more factors may predominate. Id.
`Generally, it is easier to establish obviousness undera higherlevel of
`
`ordinary skill in the art. Innovention Toys, LLC v. MGA Entm’t, Inc.,
`
`637 F.3d 1314, 1323 (Fed. Cir. 2011) (“A less sophisticated level of skill
`
`12
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`
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`IPR2016-00386 Patent 8,653,672 B2 IPR2016-00387 Patent 8,841,778 B2
`IPR2016-00388 Patent 7,193,239 B2
`
`generally favors a determination of nonobviousness. . . while a higher level
`of skill favors the reverse.”).
`|
`Petitioner, with support of its declarant Paul D. Franzon, Ph.D.,
`contendsthat one ofordinary skill in the art at the time of the inventions of
`the challenged patents “would havehadat least a B.S. degree in electrical
`engineering, material science, or equivalentthereof, and at least 3-5 years of
`-experience in the relevantfield, e.g., semiconductor processing.” [PR386-
`Pet. 5 (citing Ex. 1002 99 52-53); see IPR387-Pet. 4 (citing Ex. 1002 ff 52-
`53); IPR388-Pet. 4 (citing Ex. 1002 {fj 52-53). According to Dr. Franzon,
`his testimonyas to the level of ordinary skill is based on considering “the
`types of problems encounteredin theart, priorart solutions to those
`problems, the rapidity with which innovations are made,the sophistication
`ofthe technology, and the educational level of active workersin the field.”
`IPR386-Ex. 1002 4 53; see IPR387-Ex. 1002 4 53; IPR388-Ex. 1002 4 53.
`Patent Owner did not propose expressly a particular level of ordinary skill.
`See, e.g., generally IPR386 PO Resp.; IPR386 Ex. 2166 (Patent Owner’s
`expert’s declaration). At the oral hearing, however, Petitioner indicated that
`there did not seem to be any dispute as to the correct level of ordinary skill.
`Tr. 112:11-14 (“I don’t think there was any dispute about whether [Dr.
`|
`Franzon’s proposed level of ordinary skill] was the correct level of skill,
`although Patent Owner can correct me.”).
`
`13
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`
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`IPR2016-00386 Patent 8,653,672 B2 IPR2016-00387 Patent 8,841,778 B2
`IPR2016-00388 Patent 7,193,239 B2
`Having reviewed the prior art asserted in these proceedings(see, e.g.,
`Exs. 1004—07, 1009, 2160°), we determinethat the level of ordinary skill
`
`proposed by Petitioner’s declarant is consistent with the challenged patents
`
`and the referencedprior art, and we adoptthat definition of the level of
`
`ordinary skill in the art for the purposesofthe analysis below.
`
`C. Disclosures ofPrior Art References®
`1. Disclosure ofBertin ’754
`
`Bertin °754 is a United States Patent that describes an improvementto
`
`a known multichip package as shown in its “prior art” Figure 1, reproduced
`
`below.
`
`6 The exhibit numbers for the asserted prior art references are the ssame in
`IPR2016-00386, IPR2016-00387, and IPR2016-00388.
`14
`
`
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`IPR2016-00386 Patent 8,653,672 B2 IPR2016-00387 Patent 8,841,778 B2
`IPR2016-00388 Patent 7,193,239 B2
`
`Bertin ’754’s Figure 1 is an exploded perspective view ofa basic prior
`
`art multichip package. Ex. 1004, 2:43-44.
`Bertin ’754 describes “[a] fabrication methodandresultant three-
`dimensional multichip package having a densely stacked array of
`semiconductorchips.” Jd. at Abstract. Morespecifically, Bertin ’754 relates
`to a methodfor fabricating a three-dimensional multichip package having a
`densely stacked array of semiconductorchips interconnected at least
`partially by meansofa plurality of metallized trenches in the semiconductor
`chips. Ex. 1004, 1:10-15. Figure 3a is reproduced below.
`5
`
`fig.
`
`5a
`
`82
`
`Referring first to FIG. 3a of Bertin °754, which depicts a three-
`dimensional multichip package, processing begins with semiconductor
`device 50 (preferably comprising a wafer) having substrate 52 andactive
`layer 54, which is typically positionedat least partially therein. Layer 54
`maybetotally or partially defused into substrate 52 and/orpartially or
`totally built up from substrate 52 using conventional semiconductor
`processing techniques known to thoseskilled in the art. Id. at 3:50-57
`(emphasis added). Layer 54 is adjacent to first, upper planar surface 56 of
`device 50. Id. at 3:57—-58. Second, lowerplanar surface 58 of stacked chip
`50 is positioned substantially parallel to first planar surface 56. Id. at 3:59—
`60. Stacked chip 50 includes semiconductor“substrate 52”(id. at 3:50-4:3),
`whichis thinned to 20 um orless(id. at 3:25—46, 5:10—22). Bertin °754
`
`15
`
`
`
`IPR2016-00386 Patent 8,653,672 B2 JPR2016-00387 Patent 8,841,778 B2
`IPR2016-00388 Patent 7,193,239 B2
`further teaches that “dielectric layer 60, for example, SiO, is grown over
`active layer 54 of device 50.” Id. at 3:60-62, Fig. 3a. Additionally, Bertin.
`
`°754 teachesthat the multichip package includesverticalelectrical
`
`interconnections(e.g., metallized trenches) that pass completely through
`
`substrates 52. Id. at Abstract, 1:62-2:12, 4:11—52, Figs. 3c, 3b, 3e, 3g.
`
`2. Disclosure ofLeedy ’695
`Leedy °695 is a United States Patent naming Glenn J. Leedy as sole
`inventor andtitled “Membrane DielectricIsolation IC Fabrication.”
`
`Ex. 1006 [54], [76]. In its Abstract, the patent indicates that the disclosed
`integrated circuits are fabricated “from flexible membranes formed of very
`thin low stress dielectric materials, such as silicon dioxideorsilicon nitride,
`and semiconductorlayers.” Jd. at Abstract. Leedy ’695 is incorporated by
`
`reference into the written description of the °672, ’778, and ’239 patents
`
`(and the entire Elm 3DSpatent family). IPR386-Ex. 1001, 2:21—23
`
`(“Assembling die in a stacked or three dimensional (3D) manneris disclosed
`
`in [Leedy °695] of the present inventor, incorporated herein by reference.”);
`
`IPR387-Ex. 1001, 2:21-23; IPR388-Ex. 1001, 2:34-36. Leedy *695
`
`discloses forming a “tensile low stress dielectric membrane” on a
`
`semiconductorlayer as part ofits integrated circuit structure. Id. at 1:53-58.
`Leedy °695 defines “[l]ow stress .
`.
`. relative to the silicon dioxide and
`silicon nitride deposition made with the Novellusequipment as being less
`than 8 x 108 dynes/cm?(preferably 1 x 10’ dynes/cm”) in tension.” Jd. at
`
`11:33-37. Additionally, Leedy °695 discloses two chemical vapor
`
`deposition (CVD)process recipes for manufacturing “structurally enhanced
`
`16
`
`
`
`IPR2016-00386 Patent 8,653,672 B2 IPR2016-00387 Patent 8,841,778 B2
`IPR2016-00388 Patent 7,193,239 B2
`
`low stress dielectric circuit membranes.” Jd. at 11:51-65.
`
`Referring to Figure 8,Leedy ’695 discloses a three dimensional
`circuit membrane. Jd. at 4:43. Figure 8 is reproduced below.
`
`
`
`Fig_8
`
`Figure 8 showsthe vertical bonding of two or more circuit membranes
`
`to form a three dimensionalcircuit structure. Id. at 16:38—40.
`
`Interconnection between circuit membranes 160a, 160b, 160c including SDs
`
`162, 164, 166 is by compression bonding of circuit membrane surface
`
`electrodes 168a, 168b, 168c, 168d (pads). Jd. at 16:40-43. Bonding 170
`
`between MDIcircuit membranesis achieved by aligning bond pads 168c,
`168d(typically between 4 pm and 25 um in diameter) on the surface of two
`circuit membranes 160b, 160c and using a mechanical or gas pressure source
`
`to press bond pads 168c, 168d together. Jd. at 16:43-49.
`
`3. Disclosure ofPoole
`Poole is a United States Patent that describes techniques for making
`charge-coupled devices, which are thinned to allow illumination of the
`
`17
`
`
`
`IPR2016-00386 Patent 8,653,672 B2 IPR2016-00387 Patent 8,841,778 B2
`IPR2016-00388 Patent 7,193,239 B2
`
`backside of the device to improve quantum efficiency and UV spectral
`
`response. Ex. 1005, Abstract, 1:8-11. It describes a two-step methodfor
`
`thinning the backside ofa silicon semiconductor substrate that includes
`integrated circuitry previously formed on the front side. Jd. at Abstract, 1:7—
`18, 3:12—25. First, “[t]he bulk silicon is thinned to 75 um with a 700 micro-
`
`grit aluminum oxide abrasive”(id. at 3:21—25; see alsoid. at Abstract, 3:33—
`
`34, 5:60-6:35), and “is then thinned and polished to 10 um using 80 nm grit
`colloidal silica” (id. at 3:21—25; see alsoid. at Abstract, 3:33-34, 6:37-46).
`Theresult is a surface “almosttotally free of work damage.” Jd. at 5:64-65;
`see also id. at 3:44—-46.
`
`4. Disclosure of Yu
`Yu is a paper published in the proceedings of a technical conference
`
`é
`
`sponsored by IEEE Industrial Electronics Society, the IEEE Robotics and
`.Automation Society, the Society of Instrument and Control Engineers, and
`the Robotics Society of Japan. Ex. 1009, 3. Yu describes a three-
`
`dimensionalintegrated circuit structure for implementing a real-time
`
`microvision system. Ex. 1009, 831-32. “The system consists of a number
`
`of 2D LSIs vertically stacked using 3D LSI technology... .” Jd. at 832.
`
`Yu’s Figure 1 is reproduced below.
`
`18
`
`
`
`IPR2016-00386 Patent 8,653,672 B2 IPR2016-00387 Patent 8,841,778 B2
`IPR2016-00388 Patent 7,193,239 B2
`
`Gain
`
`.
`
`Image Sensor
`Array
`,
`
`Amplifier &
`AD Converter
`
`‘Data Latch
`& Masking
`
`Processor Array .
`& Output Circuit
`
`Figure |: Basic concept of real-time microvision system
`with 3D integration structure
`,
`.
`Figure 1 shows a basic concept of a real-time microvision system with
`a 3D integration structure.
`In Yu’s microvision system, substrates are ground and polished to thin
`the substrates to about 30 microns. Jd. at 831-32 (“The Si substrate of the
`
`2D-LSI whichhas the basiccircuits is ground and polished to make thin
`wafer.”); id. at Abstract (“In fabrication, grinding and chemical-mechanical
`polishing techniques are used to thin the wafer to 30 pum.’’). Wafers then are
`bondedtogether using a combination of conductive microbumps and a UV-
`hardening adhesive. Id. at 834-35 (“The thinned waferis bonded to a thick
`wafer using In/Au micro-bumps with the minimum size of 5 wm x 5um and
`UV hardening adhesive layer with thickness of 1 sm byforcing the z
`direction pressure after careful wafer alignment.”). The microbumps
`connect to buried interconnectstructures that form vertical interconnects
`betweenvertically stacked circuitry. Id. at Fig. 8. Figure 1 shows a basic
`concept ofa real-time microvision system with a 3D integration structure.
`
`19
`
`
`
`a
`
`IPR2016-00386 Patent 8,653,672 B2 IPR2016-00387 Patent 8,841,778 B2
`IPR2016-00388 Patent 7,193,239 B2
`In Yu's microvision system, substrates are ground andpolishedto thin
`the substrates to about 30 microns. Id. at 831-32 (“The Si substrate of the
`2D-LSI which has the basic circuits is ground and polished to make thin
`wafer.”); id. at Abstract (“In fabrication, grinding and chemical-mechanical
`
`polishing techniques are used to thin the wafer to 30 um.”’). Wafers then are
`
`bond
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