Trials@uspto.gov
`571-272-7822
`
`Paper 63
`Entered: June 23, 2017
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`SAMSUNG ELECTRONICS CO., LTD.,
`MICRON TECHNOLOGY,INC., and SK HYNIX,INC.,
`Petitioner,
`
`Vv.
`
`ELM 3DS INNOVATIONS, LLC,
`Patent Owner.
`
`;
`
`Case IPR2016-00386 Patent 8,653,672 B2
`Case IPR2016-00387 Patent 8,841,778 B2
`Case IPR2016-00388 Patent 7,193,239 B2
`
`Before GLENN J. PERRY, BARBARA A. BENOIT, and
`FRANCESL. IPPOLITO, Administrative Patent Judges.
`
`BENOIT, Administrative Patent Judge.
`
`DECISION
`Final Written Decision
`35 US.C. § 318(a) and 37 CFR. § 42.73
`
`
`571-272-7822
`
`Paper 63
`Entered: June 23, 2017
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`SAMSUNG ELECTRONICS CO., LTD.,
`MICRON TECHNOLOGY,INC., and SK HYNIX,INC.,
`Petitioner,
`
`Vv.
`
`ELM 3DS INNOVATIONS, LLC,
`Patent Owner.
`
`;
`
`Case IPR2016-00386 Patent 8,653,672 B2
`Case IPR2016-00387 Patent 8,841,778 B2
`Case IPR2016-00388 Patent 7,193,239 B2
`
`Before GLENN J. PERRY, BARBARA A. BENOIT, and
`FRANCESL. IPPOLITO, Administrative Patent Judges.
`
`BENOIT, Administrative Patent Judge.
`
`DECISION
`Final Written Decision
`35 US.C. § 318(a) and 37 CFR. § 42.73
`
`
`
`IPR2016-00386 Patent 8,653,672 B2 IPR2016-00387 Patent 8,841,778 B2
`IPR2016-00388 Patent 7,193,239 B2
`
`I. INTRODUCTION
`
`These inter partes reviews, instituted pursuant to 35 U.S.C. § 314,
`
`challenge the patentability of certain claims of U.S. Patent
`
`Nos. 8,653,672 B2 (“the ’672 patent”), 8,841,778 B2 (“the 778 patent”),
`and 7,193,239 B2 (“the ’239 patent),! each of which shares the same written
`description. All of the challenged patents are owned by Elm 3DS
`
`Innovations, LLC (“Patent Owner”). We havejurisdiction under 35 U.S.C.
`
`§ 6. This Final Written Decision is entered pursuant to 35 U.S.C. § 318(a)
`
`and 37 C.F.R. § 42.73. This Decision is issued concurrently with a Final
`
`Written Decision in IPR2016-00393, which also challenges the patentability
`
`of claims 10-12, 18-20, 60-63, 67, 70-73, and 77 of the ’239 patent.
`
`For the reasons discussed herein, Petitioner has not shownby a
`
`preponderanceof the evidence that the challenged claims in any of the
`
`challenged patents are unpatentable.
`
`A. Procedural History
`
`In IPR2016-00386, Petitioner filed a Petition seeking inter partes
`
`review ofcertain claims of the °672 patent and weinstituted a review.
`
`IPR386-Paper | (“IPR386-Petition” or “IPR386-Pet.”); IPR386-Paper 14
`
`(“IPR386-Institution Decision” or “IPR386-Inst. Dec.”). In IPR2016-00387,
`
`Petitioner filed a Petition seeking inter partes review ofcertain claimsof the
`
`778 patent, and weinstituted a review. IPR387-Paper 1 (“IPR387-Petition”
`
`' The challenged patent is Exhibit 1001 in each proceeding. Citations may
`be preceded by “IPR386”to designate IPR2016-00386, “IPR387”to
`designate JPR2016-00387, or “IPR388” to designate IPR2016-00388.
`2
`
`
`
`IPR2016-00386 Patent 8,653,672 B2 IPR2016-00387 Patent 8,841,778 B2
`IPR2016-00388 Patent 7,193,239 B2
`
`or “IPR387-Pet.”); IPR387-Paper 13 (“IPR387-Institution Decision”or
`
`“IPR387-Inst. Dec.”). In IPR2016-00388, Petitioner filed a Petition seeking
`
`inter partes review ofcertain claims of the ’239 patent, and weinstituted a
`
`review. IPR388-Paper 4 (“IPR388-Petition” or “IPR388-Pet.’’);
`
`IPR388-Paper 11 (“IPR388-Institution Decision” or “IPR388-Inst. Dec.”).
`
`In our Decisionsto Institute, we did not agree with Patent Ownerthat the
`
`Petitions were barred under 35 U.S.C. § 315(b) because, according to Patent
`
`Owner, the Office lacked authority to treat certain days on whichthe Office
`
`experienced an emergencysituation, such that many ofits online and
`
`information technology systems were shut down,as federal holidays.
`
`IPR386-Inst. Dec. 4-5; IPR387-Inst. Dec. 3-4; IPR388-Inst. Dec. 4—5.
`
`Patent Ownerhasnotraised this issue subsequentto institution in any of the
`
`three proceedings.
`
`In responseto an orderto clarify the claim construction standard to be
`
`applied in each proceeding (IPR386-Paper 18; IPR387-Paper 16; IPR388-
`
`Paper 14), Patent Ownercertified that each of the challenged patents in these
`
`three proceedings would expire prior to the deadline for issuing a final
`
`written decision and, therefore, contendedthat the claim construction
`
`standardset forth in Phillips v. AWH Corp., 415 F.3d 1303 (Fed. Cir. 2005),
`
`should be applied (IPR386-Paper 23; IPR387-Paper 21; IPR388-Paper19).
`
`Petitioner concurred with Patent Owner’s contention. IPR386-Paper25;
`
`IPR387-Paper 23; IPR388-Paper 21. We agreed with the parties and issued
`
`an order indicating that the Phillips claim construction standard should be
`
`
`
`IPR2016-00386 Patent 8,653,672 B2 IPR2016-00387 Patent 8,841,778 B2
`IPR2016-00388 Patent 7,193,239 B2
`
`applied in each of these three proceedings. IPR386-Paper 28; IPR387-
`
`Paper 26; IPR388-Paper 24.
`
`Subsequentto institution, Patent Ownerfiled a Patent Owner ©
`
`Responseto the Petition in each case. IPR386-Paper 55 (“IPR386-PO
`
`Resp.”); IPR387-Paper 50 (“IPR387-PO Resp.”); IPR388-Paper 47
`
`(“IPR388-PO Resp.”). Petitioner filed a Reply to Patent Owner’s Response
`
`to the Petition in each case. IPR386-Paper 61 (“IPR386-Pet. Reply”);
`
`IPR387-Paper 56 (“IPR387-Pet. Reply”); IPR388-Paper 53 (“IPR388-Pet.
`
`Reply”).
`
`Weheld a consolidated hearing for the inter partes reviews. A
`
`transcript of the oral hearing is includedin the record of each proceeding.
`IPR386-Paper 67; IPR387-Paper 62; IPR388-Paper 59 (collectively “Tr.”).
`
`B. Related Matters
`
`Asrequired by 37 C.F.R. § 42.8(b)(2), each party identifies various
`
`judicial or administrative matters that would affect or be affected by a
`
`decision in this proceeding. IPR386-Pet. 1-2; IPR386-Paper 9 (Patent
`
`Owner’s Mandatory Notices); IPR387-Pet. 1-2; IPR387-Paper 8 (Patent
`Owner’s Mandatory Notices); IPR388-Pet. 1-2; IPR388-Paper 7 (Patent
`Owner’s Mandatory Notices). Petitioner indicates that the challenged
`
`patents are involvedin the following United States District Court
`
`proceedings: Elm 3DS Innovations, LLC v. Samsung Elecs. Co., No. 1:14-
`
`cv-01430 (D. Del.); Elm 3DS Innovations, LLC v. Micron Tech., Inc.,
`
`No. 1:14-cv-01431 (D. Del.); and Elm 3DS Innovations, LLC v. SK Hynix
`
`Inc., No. 1:14-cv-01432 (D. Del.).
`
`
`
`IPR2016-00386 Patent 8,653,672 B2 IPR2016-00387 Patent 8,841,778 B2
`IPR2016-00388 Patent 7,193,239 B2
`
`The ’239 patent, which is challenged in IPR2016-00388, also is the
`
`subject of inter partes review IPR2016-00393. Additionally, patents related
`
`to the challenged patent are the subjects of petitions filed in IPR2016-00389
`
`(U.S. Patent No. 8,035,233); IPR2016-00390 (U.S. Patent No. 8,629,542);
`
`IPR2016-00391 (U.S. Patent No. 8,796,862); IPR2016-00394 (U.S. Patent
`
`No. 8,410,617); IPR2016-00395 (US Patent No. 7,504,732); IPR2016-00687
`(U.S. Patent No. 8,928,119); IPR2016-00691 (U.S. Patent No. 7,474,004);
`
`IPR2016-00708 (U.S. Patent No. 8,907,499); IPR2016-00770 (U.S. Patent
`
`No. 8,907,499); and IPR2016-00786 (U.S. Patent No. 8,933,570). We also
`
`note that Petitioner filed two additional petitions requesting inter partes
`
`review of U.S. Patent No. 8,791,581 (IPR2016-00703 and IPR2016-00706) -
`
`for which wedid not institute a review.
`
`C. The Written Description ofthe Challenged Patents”
`The challenged patents identify Glenn J. Leedy as sole inventor of the
`
`claimed subject matter. The patents each claim the benefit of the filing date
`
`of April 4, 1997 through a series of continuation or divisional applications.
`
`Accordingly, the patents share a commonwritten description.
`
`The patents generally relate to a three-dimensionalstructure (3DS)
`
`for integrated circuits that allows for physical separation of memorycircuits
`
`and control logic circuits on different layers. Ex. 1001, Abstract. Figure la
`
`is reproduced below.
`
`* For brevity, citations to the written description refer to the ’°672 patentat
`issue in IPR2016-00386.
`
`5
`
`
`
`IPR2016-00386 Patent 8,653,672 B2 IPR2016-00387 Patent 8,841,778 B2
`IPR2016-00388 Patent 7,193,239 B2
`
`
`
`Figure la
`
`Figure 1a shows 3DS memory device 100 having a stack of
`
`integrated circuit layers with a “fine-grain inter-layer vertical interconnect”
`
`betweenall circuit layers. Jd. at 3:64-67. Layers shownincludecontroller
`circuit layer 101 and memoryarraycircuit layers 103. Jd. at 4:17-19. The
`written description discloses that “each memoryarraycircuit layer is a
`
`thinned and substantially flexible circuit with net low stress, less than 50 pm
`
`and typically less than 10 pm in thickness.” Jd. at 4:22—24, The written
`
`description further discloses that the “thinned (substantially flexible)
`
`substrate circuit layers are preferably made with dielectrics in low stress
`(less than 5x 10® dynes/cm’)such as lowstress silicon dioxide andsilicon
`
`nitride dielectrics as opposed to the more commonly usedhigherstress
`
`dielectrics of silicon oxide andsilicon nitride used in conventional memory
`
`circuit fabrication.” Jd. at 8:45—50.
`
`Figure 1b is reproduced below.
`
`
`
`IPR2016-00386 Patent 8,653,672 B2 IPR2016-00387 Patent 8,841,778 B2
`IPR2016-00388 Patent 7,193,239 B2
`
`Lé2 SSSSLTTTISILA
`
`(POLLLLLULE
`
`101
`
`Figure 1b
`
`Figure 1b of written description showsa cross-section of a 3DS
`
`integrated circuit with metal bonding interconnect betweenthinnedcircuit
`
`layers. Id. at 3:38-40. Bond andinterconnect layers 105a, 105b, 105c are
`
`shown betweencircuit layers 103a and 103b. Jd. at Fig. 1b. The written
`
`description discloses that pattern 107a, 107b, 107c in the bond and
`interconnect layers 105a, 105b, 105c defines the vertical interconnect
`contacts betweenthe integrated circuit layers and servesto electrically
`
`isolate these contacts from each other and the remaining bond material. Jd.
`
`at 4:11-15. Additionally, the written description teaches that the pattern
`
`takes the form of voids or dielectric filled spaces in the bond layers. Jd. at
`
`4:15-16.
`
`
`
`IPR2016-00386 Patent 8,653,672 B2 IPR2016-00387 Patent 8,841,778 B2
`IPR2016-00388 Patent 7,193,239 B2
`
`Further, the written description teaches that the “term fine-grained
`
`inter-layer vertical interconnect is used to meanelectrical conductors that
`
`pass througha circuit layer with or without an intervening device element
`
`and have a pitch of nominally less than 100 pm....” Jd. at 3:67-4:4. The
`
`fine-grained inter-layer vertical interconnect functions to bond together
`
`various circuit layers. Id. at 4:5—7.
`
`D. Instituted Grounds of Unpatentability
`
`Weinstituted inter partes reviews of the challenged patents based on
`Petitioner’s asserted grounds involving the following references:? (i) U.S.
`
`Patent No. 5,202,754, issued April 13, 1993 (Ex. 1004, “Bertin ’754”);
`
`(ii) U.S. Patent No. 5,354,695, issued Oct. 11, 1994 (Ex. 1006,
`
`“Leedy 695”); (iii) U.S. Patent No. 5,162,251, issued Nov. 10, 1992 (Ex.
`
`1005, “Poole”’); (iv) Yu,et al., Real-Time Microvision System with Three-
`
`Dimensional Integration Structure, Proceedings of the 1996 IEEE/SICE/RSJ
`
`International Conference on Multisensor Fusion and Integration for
`
`Intelligent Systems, 1996 (Ex. 1009, “Yu’); and (v) U.S. Patent No.
`
`5,627,106, issued May6, 1997 (Ex. 1008, “Hsu’’).
`
`Weinstituted inter partes reviews of the challenged patents based on
`
`35 U.S.C. § 1034 on the particular following grounds:
`
`3 The prior art references have the same exhibit numbers in each proceeding.
`4 The Leahy-Smith America Invents Act (“AIA”), Pub. L. No. 112-29, 125
`Stat. 284, 287-88 (2011), revised 35 U.S.C. § 103, effective March 16,
`2013. Because the challenged patent was filed before March 16, 2013, we
`refer to the pre-AJA version of § 103 in this decision.
`8
`
`
`
`IPR2016-00386 Patent 8,653,672 B2 IPR2016-00387 Patent 8,841,778 B2
`IPR2016-00388 Patent 7,193,239 B2
`
`
`
`
`
`
`Claims 17, 18, 22, 84, 95,
`IPR2016-00386 Bertin 754, Poole,
`129-132, 145, 146, and 152
`and Leedy
`°695
`
`IPR2016-00386|Yu and Leedy *695 Claims 17, 18, 22, 84, 95,
`po| 1297132,145, 146, and152|
`
`IPR2016-00387|Bertin ’754 and ;
`
`
`
`
`
`IPR2016-00387|Bertin ’754, Poole, Claims 2, 8, 31, 32, 44, 46,
`
`
`
`
`and Leedy ’695
`and 52-54
`
`
`Claims1, 2, 8, 14, 31, 32,
`IPR2016-00387
`;
`
`
`i
`| Hsu and Leedy ’695
`44, 46, and 52-54
`
`
`
`
`
`
`PRN08SYu and Leedy "099|63, 67, 70-73, and 77
`IPR2016-00388
`|. 4, 4scene |Claims 10-12, 18-20,60—_|
`
`
`
`IPR386-Inst. Dec. 40; IPR387-Inst. Dec. 34; IPR388-Inst. Dec. 28.
`
`II. DISCUSSION°
`
`A. Principles ofLaw
`
`1. Principles ofClaim Construction
`The patents challenged in these three proceedings have expired. See
`
`IPR386-Paper 23 (Patent Owner’s Notice of Patent Expiration indicating the
`
`’672 patent would expire on April 4, 2017); IPR387-Paper 21 (indicating
`
`that the ’778 patent would expire on April 4, 2017), IPR388-Paper 19
`
`indicating that the ’239 patent would expire on April 4, 2017. For claims of
`
`an expired patent, the Board’s claim construction analysis is similar to that
`
`of a district court. See In re Rambus, Inc., 694 F.3d 42, 46 (Fed. Cir. 2012);
`
`see, e.g., IPR386-Paper 28 (determininga district court-type claim
`
`> The discussion in this section, unless otherwise noted, addresses issues
`relevant to IPR2016-00386, IPR2016-00387, and IPR2016-00388.
`9
`
`
`
`IPR2016-00386 Patent 8,653,672 B2 IPR2016-00387 Patent 8,841,778 B2
`IPR2016-00388 Patent 7,193,239 B2
`
`_
`
`construction approach following Phillips is to be applied during IPR2016-
`
`IPR00386, IPR2016-00387, and IPR2016-00388). In this context, claim
`
`terms “are generally given their ordinary and customary meaning” as
`
`understood by a person of ordinary skill in the art in question at the time of
`
`the invention. Phillips v. AWH Corp., 415 F.3d 1303, 1312-13 (Fed. Cir.
`
`2005) (en banc). “In determining the meaning of the disputed claim
`
`limitation, we look principally to the intrinsic evidence of record, examining
`
`the claim languageitself, the written description, and the prosecution
`history, if in evidence.” DePuy Spine, Inc. v. Medtronic Sofamor Danek,
`
`Inc., 469 F.3d 1005, 1014 (Fed. Cir. 2006) (citing Phillips, 415 F.3d at
`
`1312-17). Extrinsic evidence, such as expert testimony and dictionary
`
`definitions, can be helpful butis “less significant than the intrinsic record in
`
`determining the legally operative meaning of claim language.” Phillips, 415
`
`F.3d at 1317. Also, extrinsic evidence is to be considered within the context
`
`of the intrinsic evidence. Jd. A claim term may be construed contrary to its
`
`ordinary and customary meaning only “under two circumstances: ‘(1) when
`
`a patentee sets out a definition andacts as [its] own lexicographer, or (2)
`
`whenthe patentee disavowsthe full scope of a claim term either in the
`999
`specification or during prosecution.’” Aventis Pharma S.A. v. Hospira, Inc.,
`
`675 F.3d 1324, 1330 (Fed. Cir. 2012) (quoting Thorner v. Sony Computer
`
`Entm’t Am. LLC, 669 F.3d 1362, 1365 (Fed. Cir. 2012)); Hill-Rom Svcs, Inc.
`
`v. Stryker Corp., 755 F.3d 1367, 1371 (Fed. Cir. 2014),
`
`In each proceeding, we construe the challenged claims according to
`these principles.
`
`10
`
`
`
`IPR2016-00386 Patent 8,653,672 B2 IPR2016-00387 Patent 8,841,778 B2
`IPR2016-00388 Patent 7,193,239 B2
`
`2. Principles ofLaw Concerning Demonstrating Unpatentability
`
`To prevail in challenging Patent Owner’s claims, Petitioner must
`
`demonstrate by a preponderance of the evidencethatthe claims are
`unpatentable. 35 U.S.C. § 316(e); 37 C.F.R. § 42.1(d). “In an [inter partes
`
`review], the petitioner has the burden from the onset to show with
`
`particularity why the patentit challenges is unpatentable.” Harmonic Inc. v.
`
`Avid Tech., Inc., 815 F.3d 1356, 1363 (Fed. Cir. 2016) (citing 35 U.S.C.
`
`§ 312(a)(3) (requiring inter partes review petitions to identify “with
`
`particularity .. . the evidence that supports the groundsfor the challenge to
`
`each claim”)). This burden nevershifts to Patent Owner. See Dynamic
`
`Drinkware, LLC v. Nat’l Graphics, Inc., 800 F.3d 1375, 1378 (Fed.
`
`Cir. 2015) (citing Tech. Licensing Corp. v. Videotek, Inc., 545 F.3d 1316,
`
`1326-27 (Fed. Cir. 2008)) (discussing the burden of proofin inter partes
`
`review). Furthermore, Petitioner cannotsatisfy its burden of proving
`
`obviousness by employing “mere conclusory statements.” Jn re Magnum
`
`Oil Tools Int’l, Ltd., 829 F.3d 1364, 1380 (Fed. Cir. 2016).
`
`Petitioner asserts that certain claims of the challenged patents are
`
`unpatentable under 35 U.S.C. § 103(a) as obvious over various combinations
`
`of references. A claim is unpatentable under 35 U.S.C. § 103(a) if the
`
`differences between the claimed subject matter and the prior art are such that
`
`the subject matter, as a whole, would have been obviousat the time of the
`
`invention to a person having ordinary skill in the art. KSR Jnt’] Co. v.
`
`Teleflex, Inc., 550 U.S. 398, 406 (2007). The question of obviousnessis
`resolved on the basis of underlying factual determinations including: (1) the
`
`1]
`
`
`
`IPR2016-00386 Patent 8,653,672 B2 IPR2016-00387 Patent 8,841,778 B2
`IPR2016-00388 Patent 7,193,239 B2
`
`scope and contentofthe prior art; (2) any differences between the claimed
`
`subject matter and the priorart; (3) the level of ordinary skill in the art; and
`
`(4) objective evidence of nonobviousness. Graham v. John Deere Co., 383
`
`US. 1, 17-18 (1966). Consideration of the Graham factors “helps inform
`
`the ultimate obviousness determination.” Apple v. Samsung Elecs. Co., 839
`
`F.3d 1034, 1048 (Fed. Cir. 2016) (en banc).
`
`B. Level of Ordinary Skill
`
`In determining whether an invention would have been obviousat the
`
`time it was made, 35 U.S.C. § 103 requires us to resolve the level of
`
`ordinary skill in the pertinentart at the time of the invention. Graham, 383
`
`U.S. at 17. “The importanceof resolving the level of ordinary skill in the art
`
`lies in the necessity of maintaining objectivity in the obviousness inquiry.”
`
`Ryko Mfg. Co. v. Nu-Star, Inc., 950 F.2d 714, 718 (Fed. Cir. 1991). The
`person of ordinary skill in the art is a hypothetical person whois presumed
`
`to have knownthe relevantart at the time of the invention. Jn re GPAC,
`Inc., 57 F.3d 1573, 1579 (Fed. Cir. 1995). Factors that may be consideredin
`
`determining the level of ordinary skill in the art include, but are not limited
`
`to, the types of problems encountered in the art, the sophistication of the
`
`technology, and educational level of active workers in the field. GPAC, 57
`
`F.3d at 1579. In a given case, one or more factors may predominate. Id.
`
`Generally, it is easier to establish obviousness undera higher level of
`
`ordinary skill in the art. Jnnovention Toys, LLC v. MGA Entm’t, Inc.,
`
`637 F.3d 1314, 1323 (Fed. Cir. 2011) (“A less sophisticated level of skill
`
`12
`
`
`
`IPR2016-00386 Patent 8,653,672 B2 IPR2016-00387 Patent 8,841,778 B2
`IPR2016-00388 Patent 7,193,239 B2
`
`generally favors a determination of nonobviousness. .
`
`. while a higherlevel
`
`of skill favors the reverse.”).
`
`Petitioner, with support of its declarant Paul D. Franzon, Ph.D.,
`
`contendsthat one of ordinary skill in the art at the time of the inventions of
`
`the challenged patents “would have hadat least a B.S. degree in electrical
`
`engineering, material science, or equivalent thereof, and at least 3-5 years of
`
`experience in the relevantfield, e.g., semiconductor processing.” IPR386-
`
`Pet. 5 (citing Ex. 1002 4] 52-53); see IPR387-Pet. 4 (citing Ex. 1002 Yq 52—
`
`53); IPR388-Pet. 4 (citing Ex. 1002 Jf 52-53). According to Dr. Franzon,
`
`his testimonyasto the level of ordinary skill is based on considering “the
`
`types of problems encountered.in theart, prior art solutions to those
`
`problems,the rapidity with which innovations are made, the sophistication
`
`of the technology, and the educational level of active workers in the field.”
`
`IPR386-Ex. 1002 4 53; see IPR387-Ex. 1002 4 53; IPR388-Ex. 1002 4 53.
`
`Patent Ownerdid not propose expressly a particular level of ordinary skill.
`
`See, e.g., generally IPR386 PO Resp.; IPR386 Ex. 2166 (Patent Owner’s
`
`expert’s declaration). At the oral hearing, however, Petitioner indicated that
`
`there did not seem to be any dispute as to the correct level of ordinary skill.
`
`Tr. 112:11—14 (“I don’t think there was any dispute about whether [Dr.
`
`Franzon’s proposedlevel of ordinary skill] wasthe correct level of skill,
`although Patent Ownercan correct me.”).
`
`13
`
`
`
`IPR2016-00386 Patent 8,653,672 B2 IPR2016-00387 Patent 8,841,778 B2
`IPR2016-00388 Patent 7,193,239 B2
`
`Having reviewedthepriorart asserted in these proceedings(see, e.g.,
`Exs. 1004-07, 1009, 2160°), we determinethat the level of ordinary skill
`
`proposedby Petitioner’s declarant is consistent with the challenged patents
`
`and the referencedprior art, and we adopt that definition of the level of
`
`ordinary skill in the art for the purposesof the analysis below.
`
`C. Disclosures ofPrior Art References®
`1. Disclosure ofBertin ’754
`Bertin ’754 is a United States Patent that describes an improvement to
`
`a known multichip package as shownin its “prior art” Figure 1, reproduced
`
`below.
`
`6 The exhibit numbersfor the asserted prior art references are the samein
`IPR2016-00386, IPR2016-00387, and IPR2016-00388.
`14
`
`
`
`IPR2016-00386 Patent 8,653,672 B2 IPR2016-00387 Patent 8,841,778 B2
`IPR2016-00388 Patent 7,193,239 B2
`
`Bertin ’754’s Figure 1 is an exploded perspective view ofa basic prior
`
`art multichip package. Ex. 1004, 2:43-44.
`
`Bertin ’754 describes “[a] fabrication method andresultant three-
`
`dimensional multichip package having a densely stacked array of
`
`semiconductor chips.” Jd. at Abstract. More specifically, Bertin ’754 relates
`
`to a methodfor fabricating a three-dimensional multichip package having a
`
`densely stacked array of semiconductor chips interconnectedat least
`
`partially by meansofa plurality of metallized trenches in the semiconductor
`
`chips. Ex. 1004, 1:10-15. Figure 3a is reproduced below.
`
`
`
`Referring first to FIG. 3a of Bertin ’754, which depicts a three-
`
`dimensional multichip package, processing begins with semiconductor
`
`device 50 (preferably comprising a wafer) having substrate 52 and active
`
`layer 54, whichis typically positioned at least partially therein. Layer 54
`
`maybetotally or partially defused into substrate 52 and/orpartially or
`
`totally built up from substrate 52 using conventional semiconductor
`
`processing techniques knownto those skilled in the art. Jd. at 3:50-57
`
`(emphasis added). Layer 54 is adjacentto first, upper planar surface 56 of
`
`device 50. Jd. at 3:57-58. Second, lower planar surface 58 of stacked chip
`
`50 is positioned substantially parallel to first planar surface 56. Id. at 3:59-
`
`60. Stacked chip 50 includes semiconductor“substrate 52” (id. at 3:50-4:3),
`
`whichis thinned to 20 um orless(id. at 3:25—46, 5:10—22). Bertin ’754
`
`15
`
`
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`IPR2016-00386 Patent 8,653,672 B2 IPR2016-00387 Patent 8,841,778 B2
`IPR2016-00388 Patent 7,193,239 B2
`
`further teaches that “dielectric layer 60, for example, Si0Oy, is grown over
`active layer 54 of device 50.” Jd. at 3:60-62, Fig. 3a. Additionally, Bertin
`
`754 teachesthat the multichip package includesvertical electrical
`
`interconnections(e.g., metallized trenches) that pass completely through
`
`substrates 52. Id. at Abstract, 1:62-2:12, 4:11-52, Figs. 3c, 3b, 3e, 3g.
`
`2. Disclosure ofLeedy ’695
`Leedy ’695 is a United States Patent naming Glenn J. Leedy as sole
`
`inventor andtitled “Membrane Dielectric Isolation IC Fabrication.”
`
`Ex. 1006 [54], [76]. In its Abstract, the patent indicates that the disclosed
`
`integrated circuits are fabricated “from flexible membranes formedof very
`
`thin low stress dielectric materials, such as silicon dioxide orsilicon nitride,
`
`and semiconductorlayers.” Jd. at Abstract. Leedy ’695 is incorporated by
`
`reference into the written description of the ’672, 778, and ’239 patents
`
`(and the entire Elm 3DSpatent family). IPR386-Ex. 1001, 2:21—23
`
`(“Assembling die in a stacked or three dimensional (3D) manneris disclosed
`
`in [Leedy ’695] of the present inventor, incorporated herein by reference.”);
`
`IPR387-Ex. 1001, 2:21—23; IPR388-Ex. 1001, 2:34-36. Leedy °695
`
`discloses forming a “tensile low stress dielectric membrane”on a
`
`semiconductorlayeras part of its integrated circuit structure. /d. at 1:53-58.
`
`Leedy ’695 defines “[l]ow stress .
`
`.
`
`. relative to the silicon dioxide and
`
`silicon nitride deposition made with the Novellus equipment as being less
`
`than 8 x 108 dynes/cm?(preferably 1 x 10’ dynes/cm’) in tension.” Jd. at
`
`11:33-37. Additionally, Leedy ’695 discloses two chemical vapor
`
`deposition (CVD)process recipes for manufacturing “structurally enhanced
`
`16
`
`
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`IPR2016-00386 Patent 8,653,672 B2 IPR2016-00387 Patent 8,841,778 B2
`IPR2016-00388 Patent 7,193,239 B2
`
`low stress dielectric circuit membranes.” Jd. at 11:51-65.
`
`Referring to Figure 8, Leedy 695 discloses a three dimensional
`
`circuit membrane.
`
`/d. at 4:43. Figure 8 is reproduced below.
`
`cows Lid
`ae 1688
`
`=
`| Ay
`
`TESeAHH
`
`Figure 8 showsthe vertical bonding of two or more circuit membranes
`
`to form a three dimensionalcircuit structure. Jd. at 16:38—40.
`
`Interconnection between circuit membranes 160a, 160b, 160c including SDs
`
`162, 164, 166 is by compression bonding of circuit membrane surface
`
`electrodes 168a, 168b, 168c, 168d (pads). Jd. at 16:40-43. Bonding 170
`
`between MDIcircuit membranesis achieved by aligning bond pads 168c,
`
`168d (typically between 4 um and 25 um in diameter) on the surface of two
`
`circuit membranes 160b, 160c and using a mechanical or gas pressure source
`
`to press bond pads 168c, 168d together. Jd. at 16:43-49.
`
`3. Disclosure ofPoole
`
`Poole is a United States Patent that describes techniques for making
`
`charge-coupled devices, which are thinnedto allow illumination ofthe
`
`17
`
`
`
`IPR2016-00386 Patent 8,653,672 B2 IPR2016-00387 Patent 8,841,778 B2
`IPR2016-00388 Patent 7,193,239 B2
`
`backside of the device to improve quantum efficiency and UV spectral
`
`response. Ex. 1005, Abstract, 1:8-11. It describes a two-step method for
`
`thinning the backside of a silicon semiconductor substrate that includes
`
`integrated circuitry previously formed on the front side. Jd. at Abstract, 1:7—
`
`18, 3:12-25. First, “[t]he bulk silicon is thinned to 75 um with a 700 micro-
`
`grit aluminum oxide abrasive”(id. at 3:21—25; see also id. at Abstract, 3:33—
`
`34, 5:60-6:35), and “is then thinned and polished to 10 ym using 80 nm grit
`
`colloidal silica” (id. at 3:21—25; see also id. at Abstract, 3:33-34, 6:37—-46).
`
`The result is a surface “almost totally free of work damage.” Id. at 5:64—-65;
`
`see also id. at 3:44—46.
`
`4. Disclosure of Yu
`
`Yu is a paper published in the proceedingsof a technical conference
`
`sponsored by IEEE Industrial Electronics Society, the IEEE Robotics and
`
`Automation Society, the Society of Instrument and Control Engineers, and
`
`the Robotics Society of Japan. Ex. 1009, 3. Yu describes a three-
`
`dimensional integrated circuit structure for implementing a real-time
`
`microvision system. Ex. 1009, 831-32. “The system consists of a number
`
`of 2D LSIs vertically stacked using 3D LSI technology. ...” Jd. at 832.
`
`Yu’s Figure 1 is reproduced below.
`
`18
`
`
`
`IPR2016-00386 Patent 8,653,672 B2 IPR2016-00387 Patent 8,841,778 B2
`IPR2016-00388 Patent 7,193,239 B2
`
`
`
`Image Sensor
`
`Amplifier &
`AD Converter
`
`- Data Latch
`& Masking
`
`et
`
`PASI
`
`& Output Circuit
`
`Figure 1: Basic conceptof rea}-time microvision system
`with 3D integration structure
`.
`
`Figure 1 showsa basic conceptofa real-time microvision system with
`
`a 3D integration structure.
`
`In Yu’s microvision system, substrates are ground and polishedto thin
`
`the substrates to about 30 microns. Jd. at 831-32 (“The Si substrate of the
`
`2D-LSI whichhasthe basic circuits is ground and polished to make thin
`
`wafer.”); id. at Abstract (“In fabrication, grinding and chemical-mechanical
`
`polishing techniques are used to thin the wafer to 30 um.”). Wafers then are
`
`bondedtogether using a combination of conductive microbumpsand a UV-
`
`hardening adhesive. Jd. at 834-35 (“The thinned wafer is bondedto a thick
`
`wafer using In/Au micro-bumpswith the minimum size of 5 um x 5 um and
`
`UV hardening adhesive layer with thickness of 1 um by forcing the z
`
`direction pressure after careful wafer alignment.”). The microbumps
`
`connect to buried interconnectstructures that form vertical interconnects
`
`betweenvertically stacked circuitry. Jd. at Fig. 8. Figure 1 showsa basic
`
`conceptof a real-time microvision system with a 3D integration structure.
`
`19
`
`
`
`IPR2016-00386 Patent 8,653,672 B2 IPR2016-00387 Patent 8,841,778 B2
`IPR2016-00388 Patent 7,193,239 B2
`
`In Yu’s microvision system, substrates are groundand polishedto thin
`
`the substrates to about 30 microns. Jd. at 831-32 (“The Si substrate of the
`
`2D-LSI whichhasthe basic circuits is ground and polished to make thin
`
`wafer.”); id. at Abstract (“In fabrication, grinding and chemical-mechanical
`
`polishing techniquesare usedto thin the wafer to 30 um.”). Wafers then are
`
`bondedtogether using a combination of conductive microbumpsand a UV-
`
`hardening adhesive.
`
`/d. at 834-35 (“The thinned wafer is bondedto a thick
`
`wafer using In/Au micro-bumps with the minimum size of 5 um x 5 wm and
`
`UV hardening adhesivelayer with thickness of 1 um by forcing the z
`
`direction pressure after careful wafer alignment.”). The microbumps
`
`connect to buried interconnect structures that form vertical interconnects
`
`between vertically stacked circuitry. Jd. at Fig. 8.
`
`5. Disclosure ofHsu
`
`Hsu is a United States Patent that relates generally to a “method of
`
`connecting three-dimensionalintegrated circuit chips using trench
`
`technology.” Ex. 1008, Abstract, 1:8-11. Referring to Figures 2-8, Hsu’s
`
`fabrication process starts with etching deep trenches 16 onsilicon substrate
`
`10, which Hsu indicates can be composed of monocrystalline silicon. Id. at
`
`2:50-61. Hsu’s integrated circuits consist of “one master chip and some
`
`subordinate chips.” Jd. at 1:20—21. According to Hsu, the master chip and
`
`subordinate chip each consist of a semiconductor substrate, preferably
`
`composed of monocrystalline silicon. Jd. at 2:51-54, 3:42-45. These chips
`
`can be “stacked by interconnection through [a] pad window[. .
`
`.] during
`
`integrated circuit processing.” Jd. at 1:28-31. Hsu further describes that the
`
`20
`
`
`
`IPR2016-00386 Patent 8,653,672 B2 IPR2016-00387 Patent 8,841,778 B2
`IPR2016-00388 Patent 7,193,239 B2
`
`“bottom surface of the [subordinate] substrate is ground and polished so that
`
`only a thin portion of the substrate remains.” Jd. at 3:21-23.
`
`II. IPR2016-00386’—CLAIM CONSTRUCTION
`AND GROUNDS OF UNPATENTABILITY
`
`In its IPR2016-00386 Petition, Petitioner contends(1) claims 17, 18,
`
`22, 84, 95, 129-132, 145, 146, and 152 are unpatentable under 35 U.S.C.
`
`§ 103 over Bertin ’754, Poole, and Leedy ’695 and(11) claims 17, 18, 22, 84,
`95, 129-132, 145, 146, and 152 are unpatentable under 35 U.S.C. § 103 over
`
`Yu and Leedy ’695. Pet. 17-42, 46-57. Patent OwneropposesPetitioner’s
`
`contentions. PO Resp. 1-3, 36-66.
`
`A. Illustrative Claim ofthe Challenged Patent
`
`Of the challenged claims in IPR2016-00386, claims 17, 84, and 129
`
`are independent. Priorto institution, Patent Ownerstatutorily disclaimed
`
`claims 143, 144, and 151 (Ex. 2140), and we did notinstitute an inter partes
`
`review of claims 143, 144, and 151 on any ground. See 37 C.F.R. § 107(e)
`
`(prohibiting institution of an inter partes review based on disclaimed
`
`claims). Claim 145, however, depends from claim 144, which,in turn,
`
`depends from claim 143. Claim 145, therefore, requires all the limitations
`
`recited in disclaimed claims 143 and 144. See 35 U.S.C. § 112 (d) (“A claim
`
`in dependent form shall be construed to incorporate by reference all the
`
`limitations of the claim to whichit refers.”). Similarly, claim 152 depends
`
`7 Unless otherwise noted, references to papers and exhibits in this section
`refer to those of record in IPR2016-00386.
`21
`
`
`
`IPR2016-00386 Patent 8,653,672 B2 IPR2016-00387 Patent 8,841,778 B2
`IPR2016-00388 Patent 7,193,239 B2
`
`from disclaimed claim 151 and so requiresall the limitations recited by that
`
`claim. Accordingly, we will include a discussion ofthe limitations recited in
`disclaimed claims 143, 144, and 151 as necessary to our discussionofthis
`asserted ground. Claim 17 isillustrative of the claimed subject matter:
`
`17. An integrated circuit structure comprising:
`
`a first substrate having topside and bottomside surfaces,
`wherein the topside surface of the first substrate supports
`interconnect contacts;
`
`a substantially flexible semiconductor second substrate
`having topside and bottom-side surfaces, wherein at least one of
`the topside surface and the bottom-side surface of the second
`substrate supports
`interconnect contacts, and wherein the
`bottom-side surface of the second substrate is formed by
`removing semiconductor material from the second substrate and
`is smoothed or polished after removal of the semiconductor
`material; and
`
`conductive paths between the interconnect contacts
`supported by the topside surface of the first substrate and the
`interconnect contacts supported by the second substrate; wherein
`the first substrate and the second substrate overlap fully or
`partially in a stacked relationship; and
`
`wherein at least one of:
`
`the first and second substrates are bonded
`i.)
`together in fixed relationship to one another at
`least
`predominantly with metal, or at least predominantly with
`silicon- based dielectric material and metal; and
`
`ii.) the integrated circuit structure further
`comprises a low-stress silicon-based dielectric material
`having a stress of 5x10
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