Trials@uspto.gov
`Tel: 571-272-7822
`
`Paper 13
`Entered: June 30, 2016
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`SAMSUNG ELECTRONICS CoO., LTD.,
`MICRON TECHNOLOGY,INC., and SK HYNIX, INC.,
`Petitioner,
`
`Vv.
`
`ELM 3DS INNOVATIONS,LLC,
`Patent Owner.
`
`Case IPR2016-00387
`Patent 8,841,778 B2
`
`Before GLENN J. PERRY, BARBARA A. BENOIT,and
`FRANCESL. IPPOLITO, Administrative Patent Judges.
`
`BENOIT, Administrative Patent Judge.
`
`DECISION
`Institution of Inter Partes Review
`37 CER. § 42.108
`
`
`Tel: 571-272-7822
`
`Paper 13
`Entered: June 30, 2016
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`SAMSUNG ELECTRONICS CoO., LTD.,
`MICRON TECHNOLOGY,INC., and SK HYNIX, INC.,
`Petitioner,
`
`Vv.
`
`ELM 3DS INNOVATIONS,LLC,
`Patent Owner.
`
`Case IPR2016-00387
`Patent 8,841,778 B2
`
`Before GLENN J. PERRY, BARBARA A. BENOIT,and
`FRANCESL. IPPOLITO, Administrative Patent Judges.
`
`BENOIT, Administrative Patent Judge.
`
`DECISION
`Institution of Inter Partes Review
`37 CER. § 42.108
`
`
`
`IPR2016-00387
`Patent 8,841,778 B2
`
`I. INTRODUCTION
`
`SamsungElectronics Co., Ltd.; Micron Technology, Inc.; and SK
`
`HynixInc. (collectively “Petitioner”) filed a Petition for inter partes review
`of claims1, 2, 8, 14, 31, 32, 44, 46, and 52-54 of U.S. Patent
`
`No. 8,841,778 B2 (Ex. 1001, “the 778 patent” or “the challenged patent”).
`
`(Paper1, “Pet.”). Patent Owner, Elm 3DSInnovations, LLC,filed a
`
`Preliminary Responseto the Petition (Paper 10, “Prelim. Resp.”).
`
`Wehavejurisdiction under 35 U.S.C. § 314, which providesthat an
`
`inter partes review maybeauthorized onlyif “the information presented in
`the petition . .. and any [preliminary] response .
`.
`. showsthat there is a
`reasonable likelihood that the petitioner would prevail with respect to at least
`
`1 of the claims challenged in the petition.” 35 U.S.C. § 314(a).
`
`Uponconsideration of the information presented in the Petition and
`
`Preliminary Response, we determine that the information presented shows
`
`there is a reasonablelikelihood that Petitioner would prevail in establishing
`
`the unpatentability of at least one ofclaims 1, 2, 8, 14, 31, 32, 44, 46, and
`
`52-54 (‘the challenged claims”).
`
`A. Related Proceedings
`Asrequired by 37 C.F.R. § 42.8(b)(2), each party identifies various
`judicial or administrative matters that would affect or be affected by a
`decision in this proceeding. Pet. 1-2; Paper 8 (Patent Owner’s Mandatory
`Notices). Petitioner indicates that the challenged patent is involved in the
`following United States District Court proceedings: Elm 3DS Innovations,
`LLC v. Samsung Elecs. Co., No. 1:14-cv-01430 (D.Del.); Elm 3DS
`Innovations, LLC v. Micron Tech., Inc., No. 1:14-cv-01431 (D. Del.); and
`Elm 3DS Innovations, LLC v. SK Hynix Inc., No. 1:14-cv-01432 (D. Del.).
`
`2
`
`
`
`IPR2016-00387
`' Patent 8,841,778 B2
`
`Additionally, patents related to the challenged patent are the subjects
`ofpetitions filed in IPR2016-00386 (U.S. Patént No. 8,653,672), IPR2016-
`00388 and IPR2016-00393 (U.S. Patent No. 7,193,239); IPR2016-00389
`
`(U.S. Patent No.:8,035,233); IPR2016-00390 (U.S. Patent No. 8,629,542);
`IPR2016-00391 (U.S. Patent No. 8,796,862); IPR2016-00394 (U.S. Patent
`No. 8,410,617); IPR2016-00395 (US Patent No. 7,504,732); IPR2016-00687
`(U.S. Patent No. 8,928,119); IPR2016-00691 (U.S. Patent No. 7,474,004);
`IPR2016-00703 (U.S. Patent No. 8,791,581); IPR2016-00706 (U.S. Patent
`No. 8,791,581); IPR2016-00786 (U.S. Patent No. 8,933,570); IPR2016-
`00708 (U.S. Patent No. 8,907,499); and IPR2016-00770 (U.S. Patent No.
`8,907,499).
`|
`
`B. Time Bar under 35 U.S.C. § 315(b)
`Patent Owner argues that Petitioner is time-barred under 35 U.S.C.
`§ 315(b) because twoofthe real-parties-in-interest, Samsung Austin
`
`Semiconductor, LLC (“SAS”) and Samsung Semiconductor,Inc. (“SSI”),
`- were servedwitha complaintalleging infringement ofthe challenged patent -
`on December 24, 2014. Prelim. Resp. 5—10; see Pet. 1 (identifying real
`parties-in-interest). Patent Owner contendsthat the Petition was filed on
`December 28, 2015, which wasfour days after the statutory one year period
`for SAS and SSIhad expired. Id. at 6; see Paper 5 (Accordingfiling date of
`December 28, 2015 to the Petition).
`|
`In the Petition, Petitioner explained thatit filed its Petition on
`December28, 2015 because the Office considered December 22-24, 2015,
`
`.
`
`|
`
`to be a “Federal holiday within the District of Columbia” pursuant to 35
`U.S.C. § 21. Pet. 3. On December22, 2015, the Office experienced a major
`poweroutageatits headquarters in Alexandria, Virginia, resulting in
`
`3
`
`
`
`IPR2016-00387
`Patent 8,841,778 B2
`_ damaged equipmentthat required the subsequent shutdown of many USPTO
`online and information technology systems. On December28, 2015, the »
`
`,
`°
`—
`_ Office announced that
`[iJn light of this emergency situation, the USPTO will consider each
`day from Tuesday, December 22, 2015, through Thursday, December
`24, 2015, to be a “Federal holiday within the District of Columbia”
`under 35 U.S.C. § 21 and 37 C-F.R. §§ 1.6, 1.7, 1.9, 2.2(d), 2.195, and
`2.196. Anyactionor fee due on these days will be considered as
`’ timely for the purposesof, e.g., 15 U.S.C. §§ 1051(b), 1058, 1059,
`1062(b), 1063, 1064, and 1126(d), or 35 U.S.C. §§ 119, 120, 133, and
`151, if the action is taken, or the fee paid, on the next succeeding
`business day on which the USPTOis open (37 C.F.R. §§ 1.7(a) and
`2.196).
`Ex. 3001 (emphasis added). Section 21(b) states that “[w]hen the day;
`or the last day, for taking any action or paying any fee in the United
`States Patent andTrademark Office falls on Saturday, Sunday, or a
`federal holiday within the District of Columbia, the action may be
`taken, or the fee paid, on the next succeeding secular or. business ©
`day.” Emphasis added.
`Petitioner has complied with the requirements of § 315(b) given the
`circumstances of the power outage during the December 22-24, 2015 period
`and the announcementsby the Office regarding the same. December 28,
`2015, which was a Monday,was the next succeeding business day after
`December 24, 2015, becauseFriday, December 25, 2015, was a federal ”
`holiday. Moreover, we disagree with Patent Owner’s arguments that the
`Office lacks the authority to treat December 22-24, 2015 as federal holidays.
`See Prelim. Resp. 7-8.
`
`
`
`IPR2016-00387
`Patent 8,841,778 B2
`
`C. The Challenged Patent
`The challenged patentrelates generally to a three-dimensional
`
`structure (3DS)for integrated circuits that allows for physical separation of
`
`memory circuits and controllogic circuits on different layers. Ex. 1001,
`
`Abstract. Figure la is reproduced below.
`
`
`
`Figure la
`
`Figure 1a shows 3DS memory device 100 having a stack of integrated
`circuit layers with a “fine-grain inter-layer vertical interconnect” betweenall
`circuit layers. Jd. at 3:66-4:3. Layers showninclude controller circuit
`layer 101 and memoryarray circuit layers 103. Id. at 4:19-21. The
`challenged patent discloses that “each memory arraycircuit layeris a
`thinned and substantially flexible circuit with net low stress, less than 50 um
`and typically less than 10 um in thickness.” Jd. at 4:24-27. The challenged
`patent further discloses that the “thinned (substantially flexible) substrate
`circuit layers are preferably made with dielectrics in low stress (less than
`5108 dynes/cm?) such as low stress silicon dioxide andsilicon nitride
`dielectrics as opposed to the more commonly used higherstress dielectrics
`of silicon oxide and silicon nitride used in conventional memorycircuit
`
`fabrication.” /d. at 8:47-52.
`
`
`
`IPR2016-00387
`Patent 8,841,778 B2 .
`
`Figure 1b is reproduced below.
`
`
`
`VPLKRkA
`Sovaa)
`
`
`EBees. a
`
`
`
`
`» BP2LLZ2Z
`[22
`LLLLLL LLL
`
`1073
`Laeeeen7 GPITS
`
`
`Figure 1b
`
`\
`Figure 1b of the challenged patent shows a cross-section of a 3DS
`integrated circuit with metal bonding interconnect between thinnedcircuit
`layers. Id. at 3:40-42. Bond andinterconnect layers 105a, 105b, 105c are
`shown betweencircuit layers 103a and 103b. Jd. at Fig. 1b. The challenged
`patent discloses that pattern 107a, 107b, 107c in the bond andinterconnect
`layers 105a, 105b, 105c definesthe vertical interconnect contacts between
`the integrated circuit layers and servesto electrically isolate these contacts
`from each other and the remaining bond material. Id. at 4:13—17.
`Additionally, the challenged patent teaches that the pattern takes the form of
`voids or dielectric filled spaces in the bond layers.
`/d. at 4:17-18.
`Further, the challenged patent teaches that the “term fine-grained
`inter-layer vertical interconnect is used to mean electrical conductors that
`pass througha circuit layer with or without an intervening device element
`. and haveapitch of nominally less than 100 pm... .” Jd. at 4:2-5. The fine-
`grain inter-layer vertical interconnect functions to bond together various
`
`circuit layers. Id. at 4:8-9.
`
`
`
`IPR2016-00387
`Patent 8,841,778 B2
`
`D. Illustrative Claim
`
`Ofthe challenged claims, claims 1, 8, and 14 are independent.
`
`Claim1is illustrative of the claimed subject matter:
`
`is of one piece and
`
`1. A circuit layer comprising:
`a semiconductor substrate that
`monocrystalline;
`interconnect conductors passing vertically through the
`semiconductor substrate; and
`insulators passing vertically
`silicon-based dielectric
`substrate
`around the vertical
`through the
`semiconductor
`interconnect conductors, the silicon-based dielectric insulators
`having a stress of less than 5x10° dynes/cm’tensile.
`Ex. 1001, 12:58-67 (paragraphing added).
`
`E. The Asserted Grounds of Unpatentability
`Petitioner contendsthat claims 1, 2, 8, 14, 31, 32, 44, 46, and 52-54
`
`of the challenged patent are unpatentable under 35 U.S.C. § 103 based on
`the following specific grounds (Pet. 3-4, 19-59):
`
`
`
`IPR2016-00387
`Patent 8,841,778 B2
`
`
`
`References
`
`Bertin ’754! and Leedy *695?
`Bertin ’754, Poole,’ and
`Leedy
`°695
`
`
`
`
` Hsu! and Leedy ’695
`
`Hsu and Kowa?
`
`Claims Challenged
`
`1, 2, 8, 14, and 52
`2, 8, 31, 32, 44, 46, and 52-54
`
`ey 8, 14, 31, 32, 44, 46, and 52~-
`ey 8, 14, 31, 32, 44, 46, and 52-
`
`
`
`
`
`
`
`
`
`II. DISCUSSION
`
`A. Claim Construction
`
`Weinterpret claims of an unexpired patent using the “broadest
`
`reasonable construction in light of the specification of the patent in which
`
`[the claims] appear[].” 37 C.F.R. § 42.100(b); see Cuozzo Speed
`
`Techs., LLC v. Lee, No. 15-446, 2016 WL 3369425, at *12 (U.S. June 20,
`
`2016) (concluding the broadest reasonable construction “regulation
`
`represents a reasonable exercise of the rulemaking authority that Congress
`
`delegated to the Patent Office”). Under that standard, claim terms are
`presumedto be given their ordinary and customary meaning as would be
`understood by oneofordinary skill in the art in the context of the entire
`
`disclosure. In re Translogic Tech., Inc., 504 F.3d 1249, 1257 (Fed. Cir.
`
`'U.S. Patent No. 5,202,754, issued April 13, 1993 (Ex. 1004,
`“Bertin ’754”).
`2U.S. Patent No. 5,354,695, issued Oct. 11, 1994 (Ex. 1006, “Leedy *695”).
`3U.S. Patent No. 5,162,251, issued Nov. 10, 1992 (Ex. 1005, “Poole’’).
`4U.S. Patent No. 5,627,106, issued May 6, 1997 (Ex. 1008, “Hsu”).
`> JP Patent Application Publication No. H3-151637, published June 27, 1991
`(Ex. 1007, “Kowa”). Petitioner has provided a certified English translation.
`Ex. 1007, 13.
`
`8
`
`
`
`Ne
`
`IPR2016-00387
`Patent 8,841,778 B2
`2007). Any special definition for a claim term mustbe set forth with
`reasonableclarity, deliberateness, and precision. Jn re Paulsen, 30 F.3d
`1475, 1480 (Fed. Cir. 1994). Further, “[t]he PTO should also consult the
`
`&
`
`patent’s prosecution history in proceedings in which the patent has been.
`
`brought back to the agency for a second review.” Microsoft Corp.v.
`
`Proxyconn, Inc., 789 F.3d 1292, 1298 (Fed. Cir. 2015). Moreover, the
`
`Board may not “construe claims during IPR so broadly thatits
`constructions are unreasonable under general claim construction
`principles.” Jd.
`
`Petitioner proposes a construction for “substantially flexible”
`
`modifying “semiconductorsubstrate.” Pet. 9-12. Patent Owner contends
`that Petitioner’s proposed constructionis irrelevant to this proceeding and
`that Petitioner has acknowledged that these claim termsare not
`determinative in this case. Prelim. Resp. 15—16. For purposesofthis
`decision, we construe “substantially flexible” modifying “semiconductor
`
`substrate.” - We determine that no other terms require express construction ©
`
`. for this decision.
`
`“substantiallyflexible” modifying “semiconductor substrate”’
`Claims 2, 8, 31, 32, 44, and 52 each recites “substantially flexible”
`modifying “semiconductor substrate.” The term “substantially flexible”is
`a term of degree that lacks clear meaning absent context because the words
`“substantially flexible” do not provide any measure to compare against
`prior artand potentially infringing substrates. See Playtex Prods., Inc.v.
`Procter. & Gamble Co., 400 F.3d 901, 908 (Fed. Cir. 2005)
`
`(‘Substantially flattenedsurface’ is clearly a comparative term.
`
`
`
`IPR2016-00387:
`Patent 8,841,778 B2
`
`Comparison requires a reference point. Therefore, to flatten something,one
`must flatten it with respect to either itself or some other object.”).
`Petitioner urges that in light ofthe intrinsic record, the broadest
`reasonable construction of “substantially flexible” modifying
`
`“semiconductor substrate” is “a semiconductorsubstrate that has been
`
`thinned to a thicknessof less than 50 um and subsequently polished or
`|
`smoothed.” Pet. 11.
`-
`.
`Petitioner argues that the Patent Owneracted as its own lexicographer
`in defining “substantially flexible” in the written description of the
`challenged patent when“substantially flexible”is used to describe a
`semiconductor substrate or how to makea substantially flexible substrate:
`Grind the backside... of the second circuit substrate to a
`thickness of less than 50 pm and then polish or smooth the
`surface. The thinned substrate is now a substantially flexible
`substrate.
`
`Pet. 10 (citing Ex. 1001, 9:3-6); see id. at 12 (citing 9:5-8).
`Petitioner furthcr argues that Patent Owner(then, Applicant)
`confirmed this definition during prosecution of related patents and
`applications. For example, during prosecution of related U.S. Patent
`No.8,907,499 (“the ’499 patent”), the Examiner objected to certain claims
`as indefinite for including the term “substantially flexible.” Pet. 10 (citing
`Ex. 1018, 4). Petitioner notes that Applicant overcamethe objection by
`arpuiny (hal “substantially flexible” is unambiguous becauseit is “clearly
`explained in the specification.” Jd. at 10-11 (citing Ex. 1019, 9; Ex. 1020,
`18:1—3 (Portion of the Application that issued as the °499 patent
`corresponding to Ex. 1001, 9:5-8). Thus, according to Petitioner, Applicant
`clearly and unmistakably set forth a definition of the term “substantially
`
`10
`
`
`
`IPR2016-00387,
`Patent 8,841,778 B2
`
`flexible” when used to modify semiconductor substrate and Applicant
`expressed anintent to define the term.
`/d. at 11.
`Onthis record, weagree in large part with Petitioner’s proposed
`construction. Looking to the Specification, however, we notethatthe
`Summary ofthe Invention section in the challenged patent doesnotlimit the
`meaning of a “substantially flexible substrate” to those substrates that have
`been polished. Morespecifically, the challenged patent teaches “/t/hinning
`ofthe memory circuit to less than about 50 um in thicknessforming a
`substantiallyflexible substrate with planar processed bond surfaces and
`bonding the circuit to the circuit stack while still in wafer substrate form.”
`Ex. 1001, 3:5-8 (emphasis added). In other words, the Specification does
`not require polishing for “forming a substantially flexible substrate.” Jd.
`|
`Accordingly, given the statements in the Summary of Invention
`section of the Specification and considering the prosecution history for a
`related patent, we preliminarily construe “substrate is substantially flexible”
`as “a semiconductor substrate that has been thinnedto a thickness ofless
`than 50 pm.” Cf Microsoft, 789 F.3d at 1298 (“The PTO should also
`consult the patent’s prosecution history in proceedings in whichthe patent
`has been brought back to the agency for a second review.”).
`Claim constructions may changeas a result of the record developing
`during trial. We note, for example, that Patent Ownerhasnotyet filed its
`response under 37 C.F.R. § 42.120or any newtestimonial evidence.
`
`'B. Asserted Ground ofObviousness over Hsu and Leedy ’695
`Petitioner contends that claims 1, 2, 8, 14, 31, 32, 44, 46, and 52-54
`
`of the challenged patent are unpatentable under 35 U.S.C. § 103 as obvious
`over Hsu and Leedy 695. Pet. 44-57. Petitioner supports its contentions
`|
`ee
`
`\
`
`
`
`IPR2016-00387
`Patent 8,841,778 B2
`withcitationsto thereferénces and with declaration testimony ofPaul
`D. Franzon, Ph.D. (Ex. 1002). Jd. Patent Owner opposes. See, e.g., Prelim.
`Resp. 2-4, 16-34, 50-58.
`"OS
`A claim is unpatentable as obvious“if the differences between the
`subject matter sought to be patented andthe prior art are such that the
`subject matter as a whole would have been obviousat the time the invention
`was madeto a person having ordinary skill in the art.” 35 U.S.C. § 103. “In
`an [inter partes review], the petitioner has the burden from the onset to show
`with particularity why the patentit challengesis unpatentable.” Harmonic
`Inc. v. Avid Tech., Inc., 815 F.3d 1356, 1363 (Fed. Cir. 2016) (citing
`35. U.S.C. § 312(a)(3) (requiring inter partes review petitions to identify
`“with particularity .. . the evidence that supports the grounds for the
`challenge to each claim”)).
`
`1. Summary ofHsu
`Hsurelates generally to a “method of connecting three-dimensional
`integrated circuit chips using trench technology.” Ex. 1008, Abstract, 1:8—
`- 11. Referring to Figures 2-8, Hsu’s fabrication process starts with etching
`deep trenches 16 onsilicon substrate 10, which Hsuindicates can be
`composed of monocrystalline silicon.
`/d. at 2:50-61. Hsu’s integrated
`circuitsconsist of “one master chip and some subordinate chips.” Jd.
`at 1:20-21. According Hsu, the master chipand subordinate chip each
`consist of a semiconductor substrate, preferably composed of
`monocrystalline silicon. Jd. at 2:51-54, 3:42-45. These chips can be
`“stacked by interconnection through [a] pad window [.. .] during integrated
`circuit processing.” Id. at 1:28-31. Hsu further describes that the “bottom
`surface of the [subordinate] substrate is ground.and polished so that only a
`
`|
`
`12
`
`
`
`IPR2016-00387
`Patent 8,841,778 B2 -
`
`thin portion of the substrate remains.” Jd. at 3:21—23.
`
`2. Summary ofLeedy ’695
`_
`Leedy695 is a United States Patent that relates to the fabrication of
`integrated circuits and interconnect metallization structures from membranes
`of dielectric and semiconductor materials. Ex. 1006, 1:38-41. In its
`’ Abstract, Leedy ’695 indicates that the disclosed integrated circuits are
`
`fabricated from flexible membranes“formed of very thin low stress
`
`dielectric materials, such as silicon dioxideorsilicon nitride, and
`
`semiconductor layers.” Jd. at Abstract. Leedy 695 also discloses forming a
`“tensile low stress dielectric membrane” on a semiconductorlayer as part of
`its integrated circuit structure. Jd. at 1:53-58. Leedy ’695 defines “low
`stress .. . relative to the silicon dioxide and silicon nitride deposition made
`with the Novellus equipmentas being less than 8 x 108 dynes/cm?
`(preferably 1 x 107 dynes/cm’) in tension.” Jd. at 11:33-37. Additionally,
`Leedy °695 discloses two chemical vapor deposition (CVD)process recipes
`for manufacturing “structurally enhanced lowstress diclectric circuit
`
`membranes.” Jd. at 11:51-65.
`Referring to Figure 8, Leedy ’695 discloses a three dimensional
`circuit membrane. Jd. at 4:43. Figure 8 is reproduced below.
`
`13
`
`
`
`IPR2016-00387
`Patent 8,841,778 B2
`
`
`
`166
`
`+
`
` 168¢
`
`168d
`
`140
`
`Fig_8
`
`Figure 8 showsthe vertical bonding of two or more circuit membranesto
`
`form a three dimensionalcircuit structure. Jd. at 16:38-40. Interconnection
`
`between circuit membranes 160a, 160b, 160c including SDs 162, 164, 166 is
`
`by compression bondingof circuit membrane surface electrodes 168a, 168b,
`168c, 168d (pads). Jd. at 16:40-43. Bonding 170 between MDIcircuit
`membranesis achieved by aligning bond pads 168c, 168d (typically between
`
`4 wm and 25 ym in diameter) on the surface of two circuit membranes 160b,
`160c and using a mechanicalor gas pressure source to press bond pads 168c,
`
`168d together. Jd. at 16:43-49.
`
`3. Petitioner’s Contentions
`
`Petitioner, with support of its declarant, Dr. Franzon, provides
`
`analysis purporting to explain how the combination of Hsu and Leedy 695
`
`would have conveyed to oneofordinary skill in the art the limitations
`recited in claims 1, 2, 8, 14, 31, 32, 44, 46, and 52-54. Pet. 47-57; Ex. 1002
`(Franzon Declaration). Also with support of Dr. Franzon, Petitioner
`provides reasons whyoneofordinary skill in the art would have combined
`the teachings of the references. See, e.g., id. at 44-47; Ex. 1002.
`
`14
`
`
`
`IPR2016-00387
`Patent 8,841,778 B2
`
`a. Limitations Recited in Independent Claim 1
`Turningfirst to the limitations recited in the challenged claims 1, 2,8,
`14, 31, 32, 44, 46, and 52-54,Petitioner relies on Hsu for describing most of
`
`the limitations recited in the challenged claims. /d. at 44 (“Hsu disclosesall
`
`but a few of the features recited in claims 1, 2, 8, 14, 31, 32, 44, 46, and 52—
`
`54.”). For example, regarding independent claim 1, Petitioner relies on
`Hsu’s description of“a semiconductor substrate 10, preferably composed of
`monocrystalline silicone” for the “semiconductorsubstrate that is of one
`piece and monocrystalline,” as recited in claim 1.
`/d. at 48 (citing Ex. 1008,
`2:54-56, 3:45—47, Figs. 3, 4, 7; Ex. 1002 § 136, 1a). Hsu’s Figure7, as
`
`annotated by Petitioner, is reproduced below.
`
`
`
`FFfd G °
`
`7
`
`Vertical Interconnect
`Conductors
`
`Pet. 49. Figure 7 showsa cross-sectional representation of a subordinate
`chip being prepared for a connection, including semiconductorsubstrate 10.
`
`Ex. 1008, 2:32-34.
`
`Forthe recited “interconnect conductors passing vertically through the
`
`semiconductor substrate,” Petitioner relies on Hsu’s conductive material
`
`15
`
`
`
`IPR2016-00387
`Patent 8,841,778 B2
`layer 20. Id. at 48-49, Petitionerrelies on Hsu’s description of“trenches
`filled with conductive material (tungsten), deposited using CVD [chemical
`vapor deposition] techniques.” Pet, 48 (citing Ex. 1008, 2:60-63, 3:5-7,
`|
`Figs. 3, 4). In other words, Hsu describes “[a] conductive material layer 20
`is deposited by selective tungsten chemical vapor deposition (CVD)
`techniques.” Ex. 1008, 3:5—7. Hsu also refers to conductive material |
`layer 20 as “tungsten-filled trenches 20.” Compare Ex. 1008, 3:5—7, withid.
`at 3:23.
`|
`)
`Forthe recited “silicon-based dielectric insulators,” Petitionerrelies
`
`on a combination of Hsu and Leedy ’695. Pet. 49-50. Petitioner relies on
`
`. formed onthe entire
`.
`Hsu’s descriptionofa “silicon dioxide film 18 .
`surface of the substrate” 10 for the required “silicon-based dielectric
`insulators passing vertically through the semiconductor.” Id. at 49. Fora
`dielectric ofthe tensile stress required by claim 1, Petitioner relies on
`Leedy °695’s “processes for depositing silicon oxideor silicon nitride
`dielectric films having tensile strength of preferably 1 x 10’ dynes/cm?that
`are compatible with conventional integrated circuit fabrication methods.”
`Id. (citing Ex. 1006 at 11:33-37, 45:49— 46:26;see alsoid. at 1:53-58,
`2:40-45, 3:9-11, 7:1-9:63, 9:28-31, 11:25-65, 47:46-5S1, 48:45—50.).
`
`—
`
`Petitioner, with support of Dr. Franzon, contends that “providing
`Leedy "695’s low tensile stress dielectric as the layer 18 of Hsu teaches or
`suggests this limitation. Id. at 50 (citing Ex. 1002 4 136, 1c).
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`Forthe dielectric conformingto the stress limitation (5 x 10°
`dynes/cm7) required by independent claim 1, Petitioner relies on Leedy ’695.
`Id. at 49-50. Petitioner indicates that Leedy ’695 describes forming a
`
`“tensile low stress dielectric membrane” on a semiconductorlayeras part of
`
`its integrated circuit structure. Jd. at 18 (quoting Ex. 1006, Abstract; see
`
`also id. at 1:53-58). Petitioner further contends that Leedy ’695 teaches that
`
`“(t]he dielectric may be ‘silicon dioxide’ or ‘silicon nitride’ deposited with a
`stress of ‘less than 8 x 10° dynes/cm?.’” Jd. (citing Ex. 1006, 11:33-37
`
`. relative to the silicon dioxide andsilicon nitride
`.
`(stating “[l]ow stress .
`deposition made with the Novellus equipmentas beingless than 8 x 10°
`dynes/cm? (preferably 1 x 10’ dynes/cm?) in tension”); see Ex. 1006, 1:53-
`58, 2:40-45, 3:9-11, 7:1-9:63, 9:28-31, 11:25-65, 47:46-51, 48:45—S0).
`
`b. Rationale for Combining Hsu and Leedy ’695
`Asdescribed above, Petitioner contends that it would have been
`
`obviousat the time of the invention “to modify Hsu such that its dielectric
`layer 18 is a dielectric characterized by a tensile strength of 5 x 10°
`dynes/cm?or less based on Leedy °695.” Jd. at 44; see id. at 44-47.
`Whenan obviousness determination relies on the combination of two
`or more references, as here, there must be some suggestion or motivation to
`
`combine the references. WMS Gaming, Inc. v. Int’l Game Tech., 184 F.3d
`1339, 1355 (Fed. Cir. 1999); see also Dome Patent L.P. v. Lee, 799 F.3d
`1372, 1380 (Fed. Cir. 2015) (“If all elements of a claim are found in the
`prior art, as is the case here, the factfinder must further consider the factual
`questions of whether a personof ordinary skill in the art would be motivated
`to combine those references, and whether in making that combination, a
`
`person of ordinary skill would have had a reasonable expectation of
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`Patent 8,841,778 B2
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`success.”). It is axiomatic that an asserted ground of obviousness must
`demonstrate articulated reasoning with rational underpinning to support the
`legal conclusion of obviousness. In re Kahn, 441 F.3d 977, 988 (Fed.
`Cir. 2006); see KSR Int’l v. Teleflex Inc., 550 U.S. 398, 418 (2007) (quoting
`In re Kahn). Mere conclusory statements are not sufficient. In re Kahn, 441
`F.3d at 988. Furthermore, “[c]are must be taken to avoid hindsight
`reconstruction by using ‘the patent in suit as a guide through the mazeof-
`' prior art references, combiningthe right references in the right way so as to
`achievethe result of the claimsin suit.” Grain Processing Corp. v. Am.
`Maize-Prods. Co., 840-F.2d 902, 907 (Fed. Cir. 1988) (quoting Orthopedic
`_ Equip. Co. v. United States, 702 F.2d 1005, 1012 (Fed. Cir. 1983)).
`With support of Dr. Franzon,Petitioner provides reasons why one of
`ordinary skill in the art would have combined the teachings of Hsu and
`Leedy 695 in the manner proposed by Petitioner. See, e.g., id. at 44-47.
`For example, Petitioner contends, with support of Dr. Franzon,that
`Leedy ’695 “provides express motivations to incorporate its low tensile
`stress dielectric material in Hsu.” Pet. 45 (citing Ex. 1002 §] 110-12).
`Petitioner indicates Leedy °695describes that low tensile stressis important
`because otherwise “surface flatness and membranestructural integrity will in
`
`many casesbe inadequate for subsequent device fabrication steps or the
`ability to form a sufficiently durable free standing membrane.” Jd. at 45 |
`(citing Ex. 1006 at 5:63-6:5; Ex. 1002 7 110). Petitioner also indicates
`Leedy *695 explains that “such dielectrics can advantageously be used to
`. insulate circuit devices and interconnect metallization while increasing
`
`structural integrity and durability.” Jd. at 45 (citing Ex. 1006 at Abstract,
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`1:53-62, 2:9-31, 2:66-3:3, 3:56-4:13, 30:36-42, 45:49-46:26, 46:52-47:33,
`
`.
`Figs. 32a—32d).
`Petitioner further reasons, with support ofDr. Franzon, that in light of
`Leedy ’695’s description of “alternative processes for depositing dielectrics
`that are able ‘to withstand a wide range of IC processing techniques and
`
`processing temperatures(of at least 400° C.) without noticeable deficiency
`in performance,”” one of ordinary skill in the art would have reasonably
`expected success combining the teachings of Hsu and Leedy *695. Jd.at 46
`
`(citing Ex. 1006 at 2:37-40; see also Ex. 1008 at 1:50—-52, 5:32-33;
`
`Ex. 1002 4 113).
`
`4. Patent Owner’s Contentions
`
`In response, Patent Owner contendsthatthere is not areasonable
`likelihood that Petitioner’s proposed combination would have rendered
`
`obviousclaims1, 2, 8, 14, 31, 32, 44, 46, and 52-54. See, e.g., Prelim.
`
`Resp. 50-59.
`First, Patent Owner contendsthat Petitioner’s reasons for making
`
`Petitioner’s proposed dielectric substitution “gloss over” technical details
`and do not address technical reasons that would dissuade one of ordinary
`
`skill in the art form combining Leedy 695 with Hsu in the manner proposed
`by Petitioner. Prelim. Resp. 16-34, 50-59. Patent Owner argues that
`semiconductor fabrication development is complex and unpredictable, and
`that one of ordinary skill cannot simply substitute one dielectric with another
`dielectric and have a reasonable expectation of success. Jd. at 2-5, 23-34,
`
`44-45.
`
`Second, Patent Ownerfurther contends that one of ordinary skill in
`
`the art would not have had reason to combine Leedy ’695 with Hsu because
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`(i) Leedy ’695 lackscritical information regardingits dielectric (id. at 30—
`
`31), (ii) the prior art teaches away from Petitioner’s combination involving
`
`the use of Leedy ’695’s “unconventional”tensile dielectrics (id. at 31-33),
`
`(iii) the benefits identified in Leedy ’695 on which Petitioner’s relied do not
`
`relate to low tensile stress dielectrics, and Petitioner allegedly
`
`mischaracterizes the benefits Leedy ’695 would provide (id. at 53-56), and
`
`(iv) Petitioners do not identify a need or problem in Hsu (id. at 56-57).
`
`For support of these arguments, Patent Ownerrelies on a declaration
`
`from Dr. Alain Harrus, which indicates that it was “unconventional”for
`
`customers of Novellus to request low tensile stress dielectrics. Id. at 32
`(citing Ex. 2137, 3). In addition to the Harrus declaration, Patent Owner
`relies on citations to a 600-page bookdescribing fabricating integrated
`circuits. Id. at 19-20, 31-32 (citing Ex. 1040°). Patent Owneralsorelies on
`
`a 1995 journalarticle noting that with the chemical vapor deposition process
`
`PECVD “film properties degrade at lower power;e.g., film stress becomes
`
`tensile” as teaching away from usingtensile dielectrics. Jd. at 32 (citing
`
`Ex. 2133,” 447).
`
`5. Analysis
`Onthe present record and for purposesof institution, we determine
`
`that Petitioner has madea sufficient showing that the combination of Hsu
`
`and Leedy ’695 would have conveyedto oneofordinary skill in the art the
`
`6 Wolf, et al., Silicon Processingfor the VLSI Era, Volume I — Process
`Technology, Lattice Press, 1986 (Ex. 1040, “Wolf’).
`7 Cote, et al., “Low-temperature chemical vapor deposition processes and
`dielectrics for microelectronic circuit manufacturing at IBM,” JBM Journal
`- ofResearch Developments, 437-464 July 1995 (Ex. 2133).
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`limitations of independent claim 1. As described in detail previously (see
`
`section II.B.3a (Petitioner’s Contentions)), Petitioner has described
`
`sufficiently its proposed combination, with citations to the references and
`
`supported by declaration testimony of Dr. Franzon.
`
`Regarding Petitioner’s proffered rationale for combining the
`
`references in the manner proposedby Petitioner and Patent Owner’s
`challenge ofthe purported rationale, we recognizethat Patent Ownerhas not
`yet had an opportunity to submit new testimonial evidence.®
`After weighing Patent Owner’s arguments and evidence as currently
`developedin its Preliminary Response against the Petition with its citations
`to declaration testimony of Dr. Franzon, we determinethat, based on the
`
`current record and for the purposesofinstitution, Petitioner has explained
`
`sufficiently with the support of Dr. Franzonthat one of ordinary skill in the
`
`art would have understoodthat it would be beneficial to make the proffered
`substitution of Leedy °695’s dielectric for Hsu’s dielectric. Pet. 44-47
`(citing Ex. 1002). See, e.g. Yorkey v. Diab, 601 F.3d 1279, 1284 (Fed. Cir.
`2010) (holding the Board has discretion to give more weight to one item of
`evidence over another “unless no reasonabletrier of fact could have done
`
`so”); In re Am. Acad. ofSci. Tech Ctr., 367 F.3d 1359, 1368 (Fed. Cir. 2004)
`(“[T]he Boardis entitled to weigh the declarations and concludethat the lack
`of factual corroboration warrants discounting the opinions expressed in the
`
`declarations.”’).
`
`8 See 37 C.F.R. § 42.107(c) (July 1, 2013) (“The preliminary responseshal]
`not present new testimony evidence beyondthat already of record, except as
`authorized by the Board.”).
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`Moreover, we do not agree with Patent Owner’s argumentsthat
`
`Petitioners do not identify a need or problem in Hsu. An obviousness
`analysis does not require the prior art references themselvesto explicitly
`state a reason (including identifying a need or problem) for the combination
`of the disclosed teachings. A reason to combine teachings from thepriorart
`
`“may be foundin explicit or implicit teachings within the references
`themselves, from the ordinary knowledgeof those skilled in the art, or from
`
`the nature of the prob
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