`
`CERTIFICATE OF CORRECTION
`
`PATENT NO.
`APPLICATION NO.
`
`: 8,841,778 B2
`: 13/963149
`
`DATED
`INVENTOR(S)
`
`: September 23, 2014
`: Leedy
`
`Page 1 of 2
`
`It is certified that error appears in the above-identified patent and that said Letters Patent is hereby corrected as shownbelow:
`
`In the Claims
`
`Column 14, lines 11-30, should read,
`
`14.
`
`A stacked circuit layer structure comprising:
`
`a first circuit layer comprising at least one of contacts, interconnects, and circuitry; and
`
`a second circuit layer stacked with the first circuit layer, the second circuit layer comprising:
`
`a semiconductor substrate that is of one piece and is monocrystalline;
`
`at least one of contacts, interconnects, and circuitry integrated with the
`semiconductor substrate;
`
`interconnect conductors extending vertically through the semiconductor substrate
`and connected between the at least one of contacts, interconnects, and circuitry of the
`secondcircuit layer and the at least one of contacts, interconnects, and circuitry of the
`first circuit layer; and
`
`silicon-based dielectric insulators around the interconnect conductors and passing
`vertically through the semiconductor substrate, the silicon-based dielectric insulators
`having a stress of less than 5 x 10° dynes/cm’tensile.
`
`Column 14, lines 37-44, should read,
`
`16.
`
`The stacked circuit layer structure of claim 15, wherein the secondcircuit layer
`is substantially flexible based on the semiconductor substrate being substantially flexible and the
`stress ofthe silicon-based dielectric film being less than 5 x 10° dynes/cm’tensile.
`
`Signed and Sealed this
`Twentieth Day of January, 2015
`
`Wivebstlhe Fo Lea
`
`Michelle K. Lee
`
`Deputy Director ofthe United States Patent and Trademark Office
`
`
`
`CERTIFICATE OF CORRECTION(continued)
`U.S. Pat. No. 8,841,778 B2
`
`Page 2 of 2
`
`17.
`
`The stacked circuit layer structure of claim 15, wherein:
`
`the secondcircuit layer is less than 50 micronsthick.
`
`
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